A8670 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK Features and Benefits Description • High efficiency integrated FETs optimized for lower duty cycle voltage conversion: 180 mΩ high side, 40 mΩ low side • Adjustable output voltage, down to 0.6 V • Extremely short minimum controllable on-time; example: allows 12 V conversion to 0.6 V at >1 MHz • Reference accuracy of ±1% throughout temperature range ¯T̄ ¯ and Power OK pins for operating and protection • F̄¯Ā¯Ū¯L̄ modes: ▫ Normal operation ▫ VFB low or high ▫ Overcurrent ▫ UVLO ▫ Thermal warning prior to TSD ▫ Thermal shutdown (TSD) ▫ LX–GND short protection ▫ Timing resistor open circuit protection The A8670 is a synchronous buck converter capable of delivering up to 2 A. The A8670 utilizes valley current mode control, allowing very short on-times to be achieved. This makes it ideal for applications that require very low output voltages relative to the input voltage, combined with high switching frequencies. Valley current mode control inherently provides improved transient response over traditional switcher schemes, through the use of a voltage feedforward loop and frequency modulation during large signal load changes. The A8670 includes a comprehensive set of diagnostic flags, allowing the host platform to react to a myriad of different conditions. A fault output indicates when either the temperature is becoming unusually high, or a single point failure has occurred; for example, the switching node (LX) shorted to ground, or the timing resistor going open-circuit. A Power OK (POK) output is also provided after a fixed delay, to indicate when the output voltage is within regulation. The A8670 is a rugged solution, offering protection against input undervoltages, Continued on the next page… Package: 20-contact QFN with exposed thermal pad (suffix ES) Continued on the next page… Applications • Servers • Point of load supplies • Network and telecom • Storage Approximate size Typical Application Diagram C2 10 nF VIN 12 V BOOT VIN C1 10 μF R1 63.4 k Ω LX L1 3.6 μH A8670 C3 10 μF TON ILIM Vpull-up R3 20 kΩ POK FAULT R5 10 kΩ FB POK COMP C6 100 nF BIAS R6 10 kΩ R4 12 k Ω FAULT SS AGND PGND C7 1 nF C8 39 pF VIN = 12 V, VOUT = 1.2 V, and fSW = 700 kHz For additional examples, see the Typical Applications section A8670-DS, Rev. 2 C4 10 μF EN R2 20 kΩ C5 10 nF VOUT 1.2 V Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Features and Benefits (continued) Description (continued) •Adjustable switching frequency and current limit to optimize efficiency and external component sizing •Externally adjustable soft-start time •Shutdown supply current only 1 μA •Pre-bias start-up capability •Input voltage range: from 7 to 16 V output overvoltages, overtemperature, output overloads, shortcircuits, current source overloads and any single point failures. The A8670 is extremely flexible, with external loop compensation, on-time select (switching frequency), programmable soft-start, and current limit. The selectable pulse-by-pulse current limit avoids the requirement to oversize the inductor to cope with large fault currents. The switching frequency can be chosen, between 200 kHz and 1 MHz. The device package (ES) is a 20-contact, 4 mm × 4 mm, 0.75 mm nominal overall height QFN with exposed thermal pad. The package is lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number Packing* A8670EESTR-T 7-in. reel, 1500 pieces/reel, 12-mm carrier tape *Contact Allegro® for additional packing options Absolute Maximum Ratings Characteristic VIN, TON, and EN Pin Voltage LX Pin Voltage Symbol VI VLX BOOT Pin Voltage VBOOT BIAS Pin Voltage Rating Unit With respect to GND Notes –0.3 to 18 V With respect to GND –0.6 to VIN + 0.3 V –1.0 V VLX – 0.3 to VLX + 8.0 V t < 50 ns, with respect to GND With respect to GND VBIAS –0.3 to 8.0 V All Other Pins – –0.3 to 7.0 V Operating Ambient Temperature TA –40 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature E temperature range Table of Contents Functional Block Diagram 3 Pin-out Diagram and Terminal List 4 Functional Description 7 Basic Operation Output Voltage Selection Switch On-Time and Switching Frequency Inductor Selection Output Capacitor Selection Input Capacitor Selection 7 7 7 8 9 9 Soft-Start and Output Overloads Fault Handling and Reporting Control Loop Control Loop Design Approach Thermal Considerations Regulator Efficiency 10 11 13 14 17 18 Layout 19 Typical Applications 20 Package Outline Drawing 26 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Functional Block Diagram VIN BOOT BIAS Linear Regulator LX Sleep Circuit EN Driver On Timer TON Control Logic Driver BIAS Off Timer ILIM + Current Amplifier + VIN UVLO FB OV FB UV TOT FB OV - Regulator Comparator Fault Reporting and Shutdown Offset + Overvoltage Comparator TSD POK FAULT + FB UV Undervoltage Comparator - PGND 0.69 V Ref gm Amplifier 0.54 V Ref - FB + Soft Start and Delay 0.6 V Ref SS AGND FB COMP Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Package Thermal Resistance (Junction to Ambient) RθJA Package Thermal Resistance (Junction to Pad) RθJP Test Conditions* On 4-layer PCB based on JEDEC standard Value Unit 37 ºC/W 2 ºC/W *Additional thermal information available on the Allegro website Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 16 LX 17 EN 18 ILIM 19 AGND 20 PGND Pin-out Diagram PGND 1 15 LX PGND 2 14 LX VIN 3 13 LX BIAS 4 12 BOOT TON 5 11 FAULT 9 SS POK 10 8 FB 6 AGND COMP 7 PAD Terminal List Table Number Name Function 1,2,20 PGND 3 VIN 4 BIAS Internal bias decoupling capacitor. Refer to the see Typical Applications section circuit diagrams, for recommended capacitors. 5 TON On-Time pin. The resistor connected between this pin and VIN defines the on-time of the regulator. This in turn defines the switching frequency for a given output voltage. 6,19 AGND Analog ground. Connect to common ground. This pin should be used as the FB resistor divider ground reference for optimal accuracy (see Typical Applications section circuit diagrams). 7 COMP Output of the error amplifier and compensation node. Connect a series R-C network from this pin to GND for control loop regulation. 8 FB Feedback input pin of the error amplifier. Connect a resistor divider from the converter output voltage node, VOUT, to this pin to set the converter output voltage. 9 SS Soft-start ramp pin. The capacitor connected to this pin defines the rate of rise of the output voltage and the effective inrush current. 10 POK Open drain Power Okay (power good) output. This pin will be a logic low if any fault (as defined in table 3) occurs, other than an overtemperature condition (TJ > 140°C). 11 ¯ĀŪ¯L̄¯T̄ ¯ F̄ ¯ĀŪ¯L̄¯T̄ ¯ output. This pin will be logic low if the on-time exceeds a certain value, if the LX node is Open drain F̄ shorted to ground, or if the thermal shutdown threshold has been reached (TJ > 160°C). See table 3. 12 BOOT High-side gate drive supply input. This pin supplies the drive for the high-side switching MOSFET switch. Connect a 10 nF ceramic bootstrap capacitor between BOOT and LX. 13,14, 15,16 LX The source of the internal high-side switching MOSFET. The output inductor and BOOT capacitor should be connected to this pin (see Typical Applications section circuit diagrams). 17 EN Enable pin. This pin is a logic input that turns the converter on or off. When EN > VENHI , the part turns on. 18 ILIM Pulse-by-pulse current limit setting. Leave this pin unconnected for maximum current from the regulator, or set this pin to GND for 50% current reduction. – PAD Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the PCB for proper operation and should be connected to the ground plane by through-hole vias. See Layout section for further details. Power ground. Connect to common ground. Power input for the control circuits and the drain of the internal high-side MOSFET. This pin must be locally bypassed (see Typical Applications section circuit diagrams). Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 ELECTRICAL CHARACTERISTICS1 Valid at TJ = –20°C to 125°C and VIN = 12 V; unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit 7 – 16 V – – 4 mA General Input Voltage Range VIN Input Quiescent Current IIN Feedback Voltage VFB VEN = 5 V, VFB = 1.2 V, no switching VIN = 16 V, VEN = 0 V 7.0 V ≤ VIN ≤ 16 V, VFB = VCOMP – 1 10 μA 0.594 0.600 0.606 V Maximum Switching Frequency fsw(max) – 1000 – kHz Minimum Switching Frequency fsw(min) – 200 – kHz –10 – 10 % On-Time Tolerance Δton RTON = 60 kΩ Maximum On-Time Period ton(max) 2.5 3.5 4.5 μs Minimum On-Time Period ton(min) – 50 90 ns Minimum Off-Time Period High-Side MOSFET On-Resistance High-side MOSFET Leakage Current2 Low-side MOSFET On-Resistance Low-side MOSFET Leakage Current2 Soft Start Source Current2 Soft Start Threshold Soft Start Ramp Time toff(min) RDS(on)HS IlkgHS RDS(on)LS IlkgLS ISS – – 350 ns IDS = 0.2 A – 180 – mΩ VDS = 12 V, EN = low – – 2 μA IDS = 0.2 A – 40 – mΩ VDS = 12 V, EN = low – – 3 μA VSS > VSSPWM – –10 – μA VSS rising – 600 – mV tSS CSS = 10 nF – 600 – μs IFB VFB = 0.6 V – ±50 ±250 nA – 61 – dB 600 800 1000 μA/V VSSPWM Amplifier and Power Stage Gain Feedback Input Bias Current2 Error Amplifier Open Loop Voltage Gain AVEA Error Amplifier Transconductance gmCOMP ICOMP = ±20 μA Error Amplifier Maximum Source/Sink Current2 ICOMP(max) VFB = VFB0 ±0.4 V – ±52 – μA COMP Voltage to Current Gain gmPOWER – 1.3 – A/V VENHI 1.8 – – V Enable Enable High Threshold Enable Low Threshold VENLO – – 0.8 V Enable Hysteresis VENHYS 150 250 – mV – 50 – μA Enable Current2 IEN VEN = 3.3 V Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 ELECTRICAL CHARACTERISTICS1 (continued) Valid at TJ = –20°C to 125°C and VIN = 12 V; unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit Feedback voltage relative to reference voltage, POK = high 85 90 95 % POKHYS POK= low – 5 – % POKLO Feedback voltage relative to reference voltage, POK = low 110 115 120 % Fault Reporting and Power OK Undervoltage Threshold (Rising) Undervoltage Hysteresis Overvoltage Threshold (Rising) POK Rising Delay ¯ĀŪ¯L̄¯T̄ ¯ Overtemperature F̄ ¯ĀŪ¯L̄¯T̄ ¯ Overtemperature Hysteresis F̄ ¯ĀŪ¯L̄¯T̄ ¯ Output Voltage POK and F̄ Minimum VIN for correct operation of ¯ĀŪ¯L̄¯T̄ ¯ POK and F̄ ¯ĀŪ¯L̄¯T̄ ¯ Leakage2 POK and F̄ POKHI POKdelay – 90 – μs Temperature rising – 140 – °C TOTHYS Fault release = TOT – TOTHYS – 20 – °C VPOK IPOK = 10 mA, fault asserted – – 500 mV ¯ĀŪ¯L̄¯T̄ ¯ pull-up of 2 kΩ to 5 V POK and F̄ – 3.5 – V VPOK = 5.5 V, fault not asserted – – 1 μA ILIM = open 2.1 2.7 3.3 A ILIM = GND 1.0 1.30 1.6 A – 50 – μs – 300 – μs TOT VINPOK IPOK Protection Pulse-by-Pulse Valley Current Limit ILIM Hiccup Overload Duration tHICOC Valley current limit reached Hiccup Shutdown Duration tHICSD Pulse-by-Pulse Negative Valley Current Limit INLIM Load acting as a current source –700 – –500 mA High-Side Switch Protection Current IHIPRO LX node short-circuited to GND – 9 – A High-Side Switch Protection Voltage VHIPRO LX node short-circuited to GND 1.8 2.0 2.2 V VIN Undervoltage Lockout VUVLO VIN rising 6.0 6.4 6.8 V VIN Undervoltage Lockout Hysteresis VUVLOHYS Thermal Shutdown Threshold TSD Thermal Shutdown Hysteresis TSDHYS – 400 – mV Temperature rising – 160 – °C Recovery = TSD – TSDHYS – 15 – °C 1Specifications 2Positive throughout the junction temperature, TJ , range of –20ºC to 125ºC are assured by design and characterization unless otherwise noted. current is into the node or pin, negative current is out of the node or pin. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Functional Description Basic Operation At the beginning of a switching cycle, the high-side switch is turned on for a duration determined by the current flowing into TON. The magnitude of current is determined by the value of the input voltage and the value of the on-time resistor (RTON, R1 in the Typical Applications section circuit diagrams). During the on-time period, the current builds up through the inductor at a rate determined by the voltage developed across it and the inductance value. When the on-time period elapses, the output of an RS latch resets, turning off the high-side switch. After a small dead-time delay, the low-side switch is turned on. The current through the inductor decays at a rate determined by the output voltage and the inductance value. The current is sensed through the low-side switch and is compared to the current demand signal. The current demand signal is generated by comparing the output voltage (stepped down to the FB pin) with an accurate reference voltage. When the current through the low-side switch drops to the current demand level, the low-side switch is turned off. After a further dead-time delay, the high-side switch is turned on again, and the process is repeated. Output Voltage Selection The output voltage (VOUT) of the converter is set by selecting the appropriate feedback resistors using the following formula: VOUT = VFB where: R5 + 1 + IFB R6 R5 R6 R5 + R6 (1) VFB is the reference voltage, R5 and R6 are as shown in the Typical Applications section circuit diagrams, and IFB is the reference bias current. It is important to consider the tolerance of the feedback resistors, because they directly affect the overall setpoint accuracy of the output voltage. It is also important to consider the actual resistor values selected and consider the trade-offs. High value resistors will minimize the shunt current flowing through the feedback network, enhancing efficiency. However, the offset error produced by the refer- ence bias current will increase, affecting the regulation. In addition, high value resistors are more prone to noise pick-up effects which may affect performance. As some kind of compromise, it is recommended that R6 be in the region of 10 kΩ. Switch On-Time and Switching Frequency The switching frequency of the converter is selected by choosing the appropriate on-time. The on-time can be estimated to a first order by using the following formula: ton = VOUT VIN 1 fSW (2) where: VOUT is the output voltage, fSW is the switching frequency, and VIN is the nominal input voltage. To factor-in the effects of resistive voltage drops in the converter circuit, the following formula can be used to produce a more accurate estimate of what the on-time has to be for a required switching frequency: ton = VOUT + (RDS(on)LS + DCRL ) IOUT VIN + (RDS(on)LS – RDS(on)HS ) IOUT 1 fSW (3) where: RDS(on)LS is the low-side MOSFET on-resistance, RDS(on)HS is the high-side MOSFET resistance, and DCRL is the inductive resistance. The switching frequency will vary slightly as the resistive voltage drops in the circuit change, either due to temperature effects or to input voltage variations. Note that when selecting the switching frequency, care should be taken to ensure the converter does not operate near either the minimum on-time (50 ns) or the minimum off-time (350 ns). Minimum on-times will typically occur in combinations of maximum input voltage, minimum output voltage with minimum load, and maximum switching frequency. Minimum off-times will typically occur in combinations of minimum input voltage, maximum output voltage with maximum load, and maximum switching frequency. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 The ton from either of the above formulae can be used to determine the TON resistor value, RTON (R1 in Typical Applications section circuit drawings): RTON = (VIN – 0.67) ton – 8 ×10–9 – 500 25 ×10–12 (4) Table 1 provides preferred resistor values for a given output voltage at target switching frequencies of 500 kHz, 700 kHz, and 1 MHz: Table 1. Recommended RTON Resistor Values (6) Note that the inductor manufacturer tolerances on the inductance value should be taken into account. This can be as high as ±30%. It is recommended that gapped ferrite solutions be used as opposed to powdered iron solutions. This is because powdered iron cores exhibit relatively high core losses, especially at higher switching frequencies. Higher core losses do have a detrimental impact on the long term reliability of the component. Inductors are typically specified at two current levels: Switching Frequency, fSW 500 kHz The required (minimum) inductance can be found: V –V 1 L(min) = IN OUT D(min) Iripp fSW 700 kHz 1 MHz • Saturation Current (Isat) The worst case maximum peak cur- 5.0 374 5.0 267 5.0 182 3.3 243 3.3 174 3.3 121 2.5 187 2.5 133 2.5 90.9 1.8 137 1.8 95.9 1.8 64.9 rent should not exceed the saturation current and indeed some margin should be allowed. The maximum peak current in an inductor occurs during an overload condition where the circuit operates in current limit. The typical valley current limit (ILIM) is 2.7 A. The peak current through the inductor is effectively the valley current limit plus the ripple current: 1.5 113 1.5 80.6 1.5 VOUT (V) RTON (kΩ) VOUT (V) RTON (kΩ) VOUT (V) RTON (kΩ) 54.9 Isat > ILIM + Iripp 1.2 90.9 1.2 63.4 1.2 43.2 1.0 76.8 1.0 52.3 1.0 35.7 0.8 60.4 0.8 42.2 0.8 28.7 0.6 44.2 0.6 30.9 0.6 23.2 • Rms Current (Irms) It is important to understand how the rms current level is specified in terms of ambient temperature. Some manufacturers quote an ambient whilst others quote a temperature that includes a self-temperature rise. For example, if an inductor is rated for 85°C and includes a self-temperature rise of 25°C at maximum load, then the inductor cannot be safely operated beyond an ambient temperature of 60°C at full load. Inductor Selection The main factor in selecting the inductance value is the ripple current. The ripple current affects the output voltage ripple and current limit. A reasonable figure of merit for the ripple current (Iripp) is 25% of the maximum load. So for a maximum load of 2 A, the peak-to-peak ripple current should be 500 mA. The maximum peak-to-peak ripple current occurs at the maximum input voltage. To a reasonable approximation, the minimum duty cycle can be found: D(min) = VOUT VIN (max) (5) (7) The rms current through the inductor should not exceed the rating for the inductor, taking into account the maximum ambient temperature. The maximum rms current is effectively the valley current limit (ILIM) plus half of the ripple current: Irms(max) > ILIM + Iripp / 2 (8) A final consideration in the selection of the inductor is the series resistance (DCR). A lower DCR will reduce the power loss and enhance power efficiency. The trade-off in using an inductor with a relatively low DCR is the physical size is typically larger. Recommended inductors include the NR8040 or NR6045 series manufactured by Taiyo Yuden. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Table 2 provides preferred inductor values for a given output voltage, 2 A output at target switching frequencies of 500 kHz, 700 kHz, and 1 MHz. When using ceramic capacitors, it is important to consider the effects of capacitance reduction due to the E-field. To avoid this voltage bias effect, it is recommended that the capacitor rated voltage be at least twice that of the actual output voltage. So for example, with a 5 V output, the capacitor should be rated to 10 V. Table 2. Recommended Inductor Values Switching Frequency, fSW 500 kHz VOUT (V) 700 kHz L (μH) VOUT (V) For the majority of applications, a 20 μF output capacitor is recommended. 1 MHz L (μH) 10 VOUT (V) L (μH) 5.0 6.8 5.0 10 5.0 3.3 10 3.3 6.8 3.3 4.7 2.5 10 2.5 4.7 2.5 3.6 1.8 6.8 1.8 4.7 1.8 3.6 1.5 4.7 1.5 3.6 1.5 3.6 1.2 4.7 1.2 3.6 1.2 2 1.0 3.6 1.0 2 1.0 2 0.8 3.6 0.8 2 0.8 1.4 0.6 2 0.6 1.4 0.6 0.9 Input Capacitor Selection The function of the input capacitor is to provide a low impedance shunt path for the current drawn by the A8670 when the highside switch is on. This minimizes the amount of ripple current reflected back into the source supply. This reduces the potential for higher conducted electromagnetic interference (EMI). In a correctly designed system, with a quality capacitor positioned adjacent to the VIN pin and the PGND pin, this capacitor should supply the high-side switch current minus the average input current. During the high-side switch off-cycle, the capacitor is charged by the average input current. Output Capacitor Selection The output capacitor has two main functions: influence the control loop response (see the Control Loop section), and determine the magnitude of the output voltage ripple. The output voltage ripple can be approximated to: Vripp = where: Iripp 8 (9) fSW COUT Iripp is the peak-to-peak current in the inductor (see the Inductor Selection section), and COUT is the output capacitance. It is recommended that ceramic capacitors be used, taking into account: size, cost, reliability, and performance. It is imperative that ceramic type X5R or X7R are used. On no account should Y5V, Y5U, Z5U, or similar be used, because the capacitance tolerance and the temperature stability is very poor. There is generally no need to consider the effects of heating caused by the ripple current flowing into the output capacitor. This is because the equivalent series resistance (ESR) of ceramic capacitors is extremely low. The effective rms current that flows in the input filter capacitor is: 1/ 2 VOUT IOUT VIN (10) Irms = –1 VOUT VIN The amount of ripple voltage (Vripp ) that appears across the input terminals (VIN with respect to GND) is determined by the amount of charge removed from the input capacitor during the high-side switch conduction time. If a capacitor technology such as an electrolytic is used, then the effects of the ESR should also be taken into account. The amount of input capacitance (CIN) required for a given ripple voltage can be found: CIN = Irms ton Vripp (11) where: ton is the on-time of the high-side switch (see the Switch OnTime and Switching Frequency section; note that maximum ton occurs at minimum input voltage), and CIN is the input filter capacitance. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 As mentioned in the Output Capacitor Selection section, the effects of voltage biasing should be taken into account when choosing the capacitor voltage rating. If ceramic capacitors are being used, then there is generally no need to consider the effects of ESR heating. Soft-Start and Output Overloads The soft-start routine controls the rate of rise of the reference voltage, which in turn controls the FB pin, and thereby the output voltage (VOUT )(see figure 1). This function minimizes the amount of inrush current drawn from the input voltage (VIN ) and potential voltage overshoot on the output rail (VOUT ). drops below 85% (typical) of the target voltage, the POK flag goes low. If the overload occurs for shorter than the Hiccup Overload Duration (<50 μs; B in figure 1), the output will automatically recover to the target level. If the overload occurs for longer than the Hiccup Overload Duration (>50 μs; C in figure 1), the regulator will shut down, the soft-start capacitor will be discharged, and (assuming no other fault conditions exist and the enable pin is still high) the regulator will be delayed by the Hiccup Shutdown Duration (D in figure 1). The Hiccup Shutdown Duration ensures that prolonged overload conditions do not cause excessive junction temperatures to occur. After the Hiccup Shutdown Duration has elapsed, the output voltage is again brought up, controlled by the soft-start function. However, if the overload condition still exists and still remains after the Soft-Start Ramp Time has elapsed, the regulator will shut down and the process will repeat until the fault is removed. A soft-start routine is initiated when the enable pin (EN) is high, no overvoltage exists on the output, the thermal protection circuitry is not activated, and VIN is above the undervoltage threshold. Immediately after EN goes high, the soft-start capacitor is charged via an internal 10 μA source and PWM switching action occurs. During the Soft-Start Ramp Time (see A in figure 1), the reference is ramped from 0 up to 0.6 V, and the output voltage ( VOUT ) tracks the reference voltage. The POK flag is held low until the output voltage reaches 90% (typical) of the target voltage and a delay of 90 μs (typical) occurs. The Soft-Start Ramp Time, tss , can be found from the following formula: C 0.6 (12) tSS = SS 10 ×10 –6 where CSS is C5 in the Typical Applications section circuit diagrams. When an output overcurrent event occurs, the regulator immediately limits the valley current at a constant level on a pulse-by pulse basis. The output voltage will tend to fold back, depending on how low the output impedance is. When the output voltage Although the A8670 is optimized for ceramic output capacitors, large value electrolytic capacitors can be used where either special hold-up, or power sequencing is required. Note the guidelines for selecting large value capacitors in the Control Loop section. Enable (EN) 0V Soft-Start (SS) 0V A A Soft-Start Ramp Time Soft-Start Ramp Time Target output voltage 90% of Target Output Voltage Target output voltage 90% of Target 85% of Target 0V Valley Current Limit Maximum load Load Current 0A 90 μs POK Delay power OK (POK) B Maximum load C <50 μs Hiccup Overload Duration >50 μs Hiccup Overload Duration 90 μs POK Delay D > 200 μs Hiccup Shutdown Duration 90 μs POK Delay 0V Figure 1. Operation of the soft-start function Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 When selecting larger-value output capacitors, it is important that the soft-start period is appropriately scaled to take into account the charging of these capacitors. For example, if the soft-start is optimized for a 22 μF ceramic output capacitor and a 2000 μF capacitor is added to the output, there is every possibility that the converter will remain in an overload condition after the soft-start and the Hiccup Overload Duration have elapsed. This mode of operation could prevent the output ever reaching the target output voltage. To demonstrate the above, consider the following example: a regulator programmed for a 5 V output, 20 μF output capacitor, and a soft-start time-off of 1 ms. Assume there is no load current draw until 5 V is reached. At start-up, the regulator has to charge the output capacitor. From C×V = I×t , the charging current into the capacitor is: I = 20 μF × 5 / 1 ms = 100 mA Now if a 2000 μF capacitor is added to the output, the capacitor would require a charge current of: I = 2000 μF × 5 / 1 ms = 10 A In this condition, the A8670 would run into the pulse-by-pulse current limit, limiting the average charge current to 2.9 A (typ). An average current of 2.9 A, assumes a valley current limit of 2.7 A and a half ripple current of 0.2 A. This means that after the soft-start delay of 1 ms, the output voltage would only be charged to: V = 2.9 A × 1 ms / 2000 μF = 1.45 V After the soft-start period is completed, the output capacitor would be charged for a short duration, defined by the Hiccup Overload Duration. Then the converter would shut down and, after the Hiccup Shutdown Duration had elapsed, would enter the start-up process again. This mode is highly undesirable and a more appropriate soft-start capacitor should be selected. The effects of adding an output capacitor with too-large value would be a condition similar to starting-up into a short-circuit across the output; where the regulator enters a hiccup mode of operation. If the output of the A8670 is pre-biased at start-up, the switcher will remain in a high impedance state until the soft-start has reached the feedback voltage ( VFB ) amplitude. This avoids the output voltage being discharged. After the soft-start threshold exceeds the FB pin voltage, PWM switching action occurs and the output voltage is brought up under the control of the soft-start circuit (see figure 2). Note that when the regulator is turned off, it enters a high impedance mode (all switches off) and if the output voltage is discharged it is done so by the load (at A in figure 2). If the load does not discharge the output, the output voltage remains in a pre-biased condition. Fault Handling and Reporting Table 3 describes the action taken for particular faults including ¯T̄ ¯ and POK flags. the status of the F̄¯Ā¯Ū¯L̄ Enable (EN) 0V Soft-Start/ Hiccup (SS) 0V Soft-Start Ramp Time Target output voltage 90% of Target Pre-biased output voltage Output Voltage 0V Soft-start voltage less than feedback voltage (VFB) No PWM switching Feedback voltage (VFB) brought-up under soft-start control 90 μs PWM switching POK Delay A Load pulls the output voltage low Power OK (POK) 0V Figure 2. Operation of the soft-start function with pre-biasing Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Table 3. Fault Handling and Reporting POK Flag ¯¯Ā¯¯Ū¯L̄ ¯T̄ ¯ F̄ Flag Normal operation High High – During start-up, the feedback voltage (VFB) is brought-up under control of the soft-start circuit Low High – After start-up, if an overload occurs for less than the Hiccup Overload Duration (50 μs), the regulator will maintain switching operation Low High Auto-recovery After start-up, if an overload occurs for greater than the Hiccup Overload Duration (50 μs), the regulator will turn off and initiate a soft-start cycle Low High Auto-restart under control of soft-start VFB > 115% No current sourced from load into regulator output Regulator immediately turns off; when VFB is reduced to within regulation range, normal operation will resume Low High Auto-recovery VFB > 115% Current sourced from load into regulator output Regulator continues to operate, controlling to the Negative Valley Current Limit (INLIM), –600 mA (typ); if the source current from the load increases beyond the current limit level, although the current limit level still holds, current will flow from the load to the input, perhaps resulting in an increase in input voltage Low High Auto-recovery VIN < 6 V (typ) Regulator immediately turns off Low High Auto-restart under control of soft-start, when VIN > 6.4 V (typ) TJ > 140°C (typ) Regulator keeps operating; if TJ < 120°C (typ), ¯ĀŪ¯L̄¯T̄ ¯ goes high F̄ High Low – TJ > 160°C (typ) Regulator immediately turns off Low Low Auto-restart under control of soft-start, when TJ < 145°C LX pin shorted to GND The voltage across the series switch is monitored; if the voltage exceeds 2 V (typ), the regulator is latched off Low Low Either the Enable pin (EN) or input voltage (VIN) must go low then high to restart under control of soft-start ton > 4 μs (typ) Regulator immediately turns off Low Low Either the Enable pin (EN) or input voltage (VIN) must go low then high to restart under control of soft-start Internal bias or bootstrap supply below the undervoltage threshold Regulator immediately turns off Low High Auto-restart under control of soft-start when above BIAS and BOOT UVLO thresholds A8670 Condition 90% < VFB < 115% VFB < 85% Comments Action After Fault Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Control Loop To a first order, the small-signal loop can be modeled as shown in figure 3. The control loop can be broken into two sections: power stage and error amplifier. Power Stage The power stage includes the output filter capacitor (COUT), the equivalent load (RLOAD), and: the inner current loop, PWM modulator, and power inductor, which together are modeled as a transconductance amplifier with a gain of 1.3 A / V. The signal Vc , supplied to the power stage, is effectively the load current demand signal. This signal effectively controls the valley current through the inductor; the higher the load the larger the Vc signal. To simplify matters, we will assume this signal controls the average current through the inductor as opposed to the valley current. The effective DC gain of the power stage, without the output capacitor and load resistor, is 1.3 A / V, where the signal Vc is limited to the range 0.36 to 2.75 V. The DC current is converted into VOUT as the current flows into the load resistor. The overall DC gain of the power stage is given as VOUT / Vc (see figure 4). At full load, the Vc signal would be 2 /1.3 = 1.54 V. Power Stage Amplifier gm = 1.3 A / V Vc Il From a small-signal point of view, the power inductor behaves like a current source; the inductor can be ignored as far as the bandwidth of the loop is concerned. The output capacitor integrates the ripple current through the inductor, effectively forming a single pole with the output load. The power stage pole can be found: 1 fp(PS) = 2 × × COUT × RLOAD (13) It can be seen that as the load changes, the position of the power pole changes in the frequency domain. This may seem like an issue in terms of where to optimize the loop, however, the change in load also changes the gain in the power stage, thus compensating for this effect. Figure 4 illustrates how the loop response of the power stage changes with a varying load. The position of fp1 and G1 is one solution, fp2 and G2 is another solution, and so forth. As the value of RLOAD increases (reducing load), the power pole moves down in frequency and the DC gain increases. Generally speaking this is not a problem, because even if the pole approaches the low frequency pole produced by the error amplifier, there is still plenty of gain in the system. In this case, while the phase margin may be greatly reduced, even to a value approaching 0°, because there is sufficient DC gain in the loop it can be shown from Nyquist theory that the system is conditionally stable. The phase margin must be considered only at the 0 dB crossover frequency. VOUT RLOAD COUT G1 FB Pin COMP Pin C8 gm = 800 μA / V R4 Ro R5 R6 VOUT Vc G2 Gain (dB) G3 RLOAD increasing Ref C7 Error Amplifier Figure 3. 1st order model of the small-signal control loop (see Typical Applications section circuit diagrams for component references) f p2 f p1 Frequency f p3 Figure 4. Power stage DC gain characteristic Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 It is recommended that X5R/ X7R ceramic capacitors be used, however, large-value capacitors such as electrolytic types can be used. Care should be taken when selecting the value of an electrolytic capacitor. As this capacitance is increased, the power pole is pushed to such a low frequency that the gain can fall off sufficiently to cause a loop instability. If using an electrolytic capacitor, consideration should also be given to the equivalent series resistance (ESR) value, because this introduces a zero with the capacitance itself. It is important to use a low-ESR type capacitor. It should be noted that capacitor manufacturers usually quote an ESR which is a maximum at a particular frequency (such as 100 kHz) and temperature (20°C). The ESR does vary with frequency and temperature, plus there are tolerance effects as well. If the zero produced by the ESR of the output capacitor features in the control loop, it is strongly recommended that a large tolerance be allowed. If necessary, the high frequency pole in the error amplifier can be used to negate the effects of this pole (see the Error Amplifier section). Error Amplifier The error amplifier is a transconductance amplifier. The DC gain of the amplifier is 61dB (1122) and, with a gm value of 800 μA / V, the effective output impedance of the amplifier can be modeled as: RO = 1122 = 1.4 MΩ 800 ×10–6 (14) The transconductance amplifier has a high DC gain to ensure good regulation. The gain is rolled off with a single pole positioned at a low frequency. A zero is positioned at higher frequencies to cancel the effects of the main power stage pole. A second pole can be introduced which should have minimal effect on the loop response, but is useful for reducing the effects of switching noise. The low frequency pole occurs at: fp1(EA) = 1 2 × × RO × C7 (15) The zero occurs at: 1 2 × × R4 × C7 fz(EA) = (16) The high frequency pole occurs at: fp2(EA) = 1 2 × × R4 × C8 (17) The potential divider formed by R5 and R6 in figure 3 effectively introduces a DC offset to the loop. This can be found from: VFB / VOUT . Control Loop Design Approach There are many different approaches to designing the feedback loop. The optimum solution is to select a target phase margin and bandwidth for optimum transient response. This typically requires either simulation software or detailed Bode plot analysis to generate a solution. The particular approach described here derives a solution through a series of basic calculations. This approach aims for a simple –20 dB/decade roll off, from the low frequency error amplifier pole (fp1(EA) ) to the 0 dB crossover point (fcross ). The 0 dB crossover point is aimed at a thirteenth of the switching frequency (fSW). This factor is chosen as a compromise between good bandwidth and minimizing the phase lag introduced by the second power pole, which occurs between 1/3 and 1/6 of the switching frequency. In theory, this should introduce a phase margin of 90°, however, in practice it will be slightly less than this, perhaps by about 5°, due to the effects of the second power pole. It is recommended that the error amplifier high frequency pole should be positioned one octave below the switching frequency. This provides some attenuation of the switching ripple whilst having minimum impact on the closed loop response. To achieve a –20 dB/decade roll off, the error amplifier zero is positioned to coincide with the power pole at maximum load. Figure 5 illustrates the power stage gain, the error amplifier gain, and then the combined overall loop response (power stage and error amplifier). Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Design Example Assuming: output voltage (VOUT) = 1.5 V, maximum load (IOUT) = 2 A, switching frequency (fSW ) = 700 kHz, and output capacitance (COUT) = 20 μF. Analyze the response at full load. 1. Crossover frequency: 700 ×103 fcross = = 53.8 kHz 13 2. Overall DC gain (refer to figure 5): VOUT DC gain (PS) = 20 Log10 Vc DC gain (EA) = 61 dB+ 20 Log10 (18) = 20 Log10 VFB VOUT + 61 dB+ 20 Log10 Vc VOUT = 20 Log10 1.5 + 61 dB + 20 Log10 1.54 0.6 1.5 = 52.8 dB (19) VFB (21) DC gain (All) = DC gain (PS) + DC gain (EA) (20) VOUT Note: With a power stage gain of 1.3 A / V and a load of 2 A, the corresponding Vc = 2 / 1.3 = 1.54 V. 3. With a 53.8 kHz crossover and a 20 dB /decade increase in gain, at what frequency does the gain reach 52.8 dB? The –20 dB / decade roll off can be described as a single pole with this transfer function for magnitude (G): 1 (22) G= 2 × × f × RC Gain (dB) DC gain (PS) Power Stage Frequency fp(PS) Gain (dB) DC gain (EA) Error Amplifier fp1(EA) fp2(EA) Frequency fz(EA) Gain (dB) –2 Overall Loop 0d B DC gain (All) /d ec ad e f cross Frequency Figure 5. Power stage, error amplifier, and combined overall control loop response Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 3a. We know that at 53.8 kHz the gain is 0 dB (1). Therefore the constant RC can be worked out: 1 (23) RC = 2 × × 53.8 ×103 × 1 = 2.96 ×10 – 6 3b. A magnitude of 52.8 dB = 436.5. The frequency at which a gain of 436.5 is reached is: 1 f = (24) 2 × × 2.96 ×10 – 6 × 436.5 = 123 Hz So the overall loop response objective is shown in figure 6. (26) 2 × × RLOAD × COUT 1 = 2 × × 0.75 × 20 ×10 –6 = 10 610 Hz 4c. The error amplifier zero (fz(EA) ) also occurs at 10.610 kHz to cancel the effects of the power pole. Therefore, as C7 is known, R4 can be found: 1 2 × × C7 × fp(PS) 1 = 2 × × 1 ×10 –9 × 10610 = 15 kΩ R4 = 4. Select the RC components. 4a. The error amplifier pole (fp1(EA) ) occurs at 123 Hz. Therefore, C7 can be found: 1 C7 = (25) 2 × × RO × fp1(EA) 1 = 2 × × 1.4 ×10 6 × 123 = 1 nF 4b. The power pole (fp(PS) ) can be found, because the output capacitor (COUT) and maximum load (RLOAD) are known: 1 fp(PS) = (27) 4d. The error amplifier high frequency pole (fp2(EA) ) is set an octave below the switching frequency. Therefore, C8 can be found: 1 2 × × R4 × ( fSW /2) 1 = 3 2 × × 15 ×10 × (700 ×10 3 / 2) = 30 pF C8 = (28) 4e. Using the above compensation component selection technique, table 4 provides preferred component values for a given Overall Loop Response, Gain (dB) output voltage, 2 A output, at target switching frequencies of 52.8 500 kHz, 700 kHz, and 1 MHz. fp1(EA) Table 4. Recommended R4 and C7 Values Switching Frequency, fSW fp(PS), fz(EA) 500 kHz –2 0d B/ de VOUT (V) ca de fcross 0.123 Frequency (kHz) 53.8 Figure 6. Design example objective: overall control loop response (power stage and error amplifier) 700 kHz R4 (kΩ) C7 (nF) VOUT (V) 5.0 33 1.5 3.3 22 1.5 2.5 18 1.8 12 1.5 10 1 MHz R4 (kΩ) C7 (nF) VOUT (V) R4 (kΩ) C7 (nF) 5.0 51 1.0 5.0 68 0.68 3.3 33 1.0 3.3 51 0.68 1.5 2.5 24 1.0 2.5 39 0.68 1.5 1.8 18 1.0 1.8 27 0.68 1.5 1.5 15 1.0 1.5 22 0.68 1.2 8.2 1.5 1.2 12 1.0 1.2 18 0.68 1.0 6.8 1.5 1.0 10 1.0 1.0 15 0.68 0.8 4.7 1.5 0.8 8.2 1.0 0.8 12 0.68 0.6 3.9 1.5 0.6 5.6 1.0 0.6 8.2 0.68 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Thermal Considerations For a given set of conditions, the junction temperature of the A8670 can be estimated by carrying out a few calculations. This is important to ensure an adequate safety margin with respect to the maximum junction temperature (150°C) to enhance reliability. This exercise also helps to understand the overall efficiency of the regulator. The general approach is to work out what thermal impedance (RθJ-A) is required to maintain the junction temperature at a given level, for a particular power dissipation. It should be noted that this process is usually iterative to achieve the optimum solution. The following steps can be used as a guideline for determining a suitable thermal solution. First, estimate the maximum ambient temperature (TA ) of the application. Second, define the maximum junction temperature (TJ ). Note that the absolute maximum is 150°C. Third, determine the worst case power dissipation. This will typically occur at maximum load and minimum VIN. Design Example Assuming: input voltage (VIN ) = 12 V, output voltage (VOUT) = 1.2 V, maximum load (IOUT) = 2 A, switching frequency (fSW ) = 500 kHz, target junction temperature (TJ) ≤ 125ºC, maximum ambient temperature (TA ) = 105°C, and inductive resistance (DCRL) = 20 mΩ. 1. The main power loss contributors are calculated separately: • Switch static losses = 45 × 10 –3 1+ TJ – 25 200 (30) 125 – 25 200 = 0.0675 Ω where RDS(on)LS(25C) is the RDS(on)LS value that can be found from the Electrical Characteristics table in this datasheet. c. Estimate the duty cycle (D) by applying equation 3 (ton ): D = ton × fSW VOUT + (RDS(on)LS + DCRL ) IOUT = VIN + (RDS(on)LS – RDS(on)HS ) IOUT = 1.2 + (0.068 + 0.02 ) 12 + (0.068 – 0.3 ) = 0.12 2 2 (31) 1 fSW 1 500 103 fSW 500 103 d. The high side static loss can be determined: PstaticHI = I 2OUT × D × RDS(on)HS(TJ) (32) = 22 × 0.12 × 0.3 = 0.144 W e. The low side static loss can be determined: a. Estimate the RDS(on) of the high-side switch at the maximum target junction temperature: RDS(on)HS(TJ) = RDS(on)HS(25C) 1 + = 200 × 10 –3 RDS(on)LS(TJ) = RDS(on)LS(25C) 1 + 1+ TJ – 25 200 PstaticLO = I 2OUT × 1 – D × RDS(on)LS(TJ) (29) 125 – 25 200 = 0.3 Ω where RDS(on)HS(25C) is the RDS(on)HS value that can be found from the Electrical Characteristics table in this datasheet. b. Estimate the RDS(on) of the low side switch at the given junction temperature: (33) = 22 × (1 – 0.12) × 0.068 = 0.239 W • Switching losses The combined turn on and turn off losses for both switches are calculated as: VIN × I OUT × 6 ×10 –9 × fSW × 2 2 12 = × 2 × 6 ×10 –9 × 500 ×103 × 2 2 = 0.072 W Pswitch = Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com (34) 17 A8670 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK • Recirculation diode losses The recirculation diode losses (low-side switch) are calculated as: Precirc = 0.8 × I OUT × 6 ×10 –9 × fSW (35) = 0.8 × 2 × 6 ×10 –9 × 500 ×103 = 0.005 W • Diode transit losses The recirculation diode losses (low-side switch) are calculated as: Ptransit = VIN × I OUT × 3 ×10 –9 × fSW (36) = 12 × 2 × 3 ×10 –9 × 500 ×103 = 0.036 W • BIAS losses The supply bias losses are calculated as: (37) Pbias = VIN × 7.2 × 10 –3 = 0.086 W 2. The total losses in the A8670 can be estimated: Ptotal = PstaticHI + PstaticLO + Pswitch + Precirc + Ptransit + Pbias (38) = 0.144 + 0.239 + 0.072 + 0.005 + 0.036 + 0.086 = 0.582 W 3. The thermal impedance required for the solution can be found: T – TA RθJA = J (39) Ptotal 125 – 105 = 0.582 = 34 °C/W For this particular solution, a high thermal efficiency board is required to ensure the junction temperature is kept below 125°C. It is recommended to use a PCB with four layers. The A8670 should be mounted onto a thermal pad. A number of vias should connect the thermal pad to at least one of the internal layers and the bottom side of the PCB. Both of these layers should be a ground plane. See the Layout section for more information. Regulator Efficiency The overall regulator efficiency can be determined by including the inductor loss. In the above thermal characteristics example, the inductor resistance, DCRL = 20 mΩ. Therefore the inductor power loss can be found:: PL = DCRL × I 2OUT (40) = 0.02 × 22 = 0.08 W The overall regulator efficiency can be found: η = VOUT × IOUT (VOUT × IOUT ) + Ptotal+ PL 1.2 × 2 = (1.2 × 2) + 0.582 + 0.08 (41) = 78. 4 % Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Layout Although the power dissipation in the A8670 is very low, it is recommended that the thermal pad of the device is soldered to an appropriate pad on the printed circuit board to help minimize the junction temperature and enhance the efficiency. The PCB pad should in turn be connected to the ground plane via a number of thermal vias. As a suggestion, the following could be used: sixteen vias, arranged in 4 rows of 4, with diameter 0.25 mm and spaced (pitch) 0.6 mm apart. The PCB pad as well as acting as a thermal connection, also forms the star connection for the grounding system. The ground return connection for the feedback resistor should be Kelvin-connected directly back to the star ground. Note: To avoid voltage offset errors in the output voltage, the feedback resistor should not be connected to the filter capacitor or load grounds returns. Figure 7 illustrates the key objectives in the grounding system. The filtering capacitors: C1, C3, C4, and C6 should be connected as close as possible to their respective pins. The ground connections for each of the capacitors should be returned directly to the star connection (PCB pad). Again, these connections should be as short as possible. Both the PGND and AGND connections should connect directly to the PCB pad to form the star connection. Due to the high impedance nature of the COMP node, it is important to ensure the compensation components are connected as close as possible. The feedback trace from R5 and R6 to the FB pin is also a high impedance input and should be as short as possible and be placed well away from noisy connections such as LX. It is recommended to keep any ground planes well away from the LX node to avoid any potential noise coupling effects. The support components (C5, C7, and C8) that are ground referenced should be connected together locally and then a common trace used to return directly to the star connection. Again, this ground should not pick-up any of the filter capacitors or load ground returns. A8670 Support Components SS C5 R4 C7 COMP C8 A8670 L1 VIN Local ‘quiet’ Ground Trace C6 Ground Plane LX BIAS R5 C3/C4 C1 PGND AGND Thermal Pad Thermal Vias R6 Ground Plane (internal or bottom side of PCB) Figure 7. Layout considerations for mounting the A8760 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Typical Applications Application circuit 1 C2 10 nF L1 4.7 μH VIN 12 V BOOT VIN C1 10 μF R1 91 kΩ VOUT 1.2 V LX A8670 C3 10 μF TON ILIM Vpull-up C4 10 μF R5 10 kΩ EN R2 20 kΩ R3 20 kΩ FB POK FAULT POK SS BIAS AGND PGND C6 100 nF C5 10 nF R6 10 kΩ COMP FAULT R4 12 k Ω C7 1 nF C8 39 pF Operating Characteristics: VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz Inductor used: Taiyo Yuden NR8040 4.7 μH Further improvements can be made to the efficiency of this circuit by: • Adding a 1 A Schottky diode between the LX node and ground. • Using an inductor with a lower DCR. Measured efficiency for this circuit 87.0 Efficiency, η (%) 85.0 TA = 25°C 83.0 81.0 TA = 75°C 79.0 77.0 75.0 0 0.5 1.0 1.5 2.0 2.5 Output Current, IOUT (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Application circuit 2 C2 10 nF L1 4.7 μH VIN 12 V BOOT VIN C1 10 μF R1 113 k Ω VOUT 1.5 V LX A8670 C3 10 μF TON ILIM Vpull-up C4 10 μF R5 15 kΩ EN R2 20 kΩ R3 20 kΩ FB POK FAULT POK SS BIAS AGND PGND C6 100 nF C5 10 nF R6 10 kΩ COMP FAULT R4 15 k Ω C7 1 nF C8 33 pF Operating Characteristics: VIN = 12 V, VOUT = 1.5 V, fSW = 500 kHz Inductor used: Taiyo Yuden NR8040 4.7 μH Further improvements can be made to the efficiency of this circuit by: • Adding a 1 A Schottky diode between the LX node and ground. • Using an inductor with a lower DCR. Measured efficiency for this circuit 89.0 TA = 25°C Efficiency, η (%) 87.0 85.0 83.0 TA = 75°C 81.0 79.0 77.0 0 0.5 1.0 1.5 2.0 2.5 Output Current, IOUT (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Application circuit 3 C2 10 nF L1 6.8 μH VIN 12 V BOOT VIN C1 10 μF R1 137 kΩ VOUT 1.8 V LX A8670 C3 10 μF TON ILIM Vpull-up C4 10 μF R5 20 kΩ EN R2 20 kΩ R3 20 kΩ FB POK FAULT POK FAULT SS BIAS AGND PGND C6 100 nF C5 10 nF R6 10 kΩ COMP R4 18 k Ω C7 1 nF C8 27 pF Operating Characteristics: VIN = 12 V, VOUT = 1.8 V, fSW = 500 kHz Inductor used: Taiyo Yuden NR8040 6.8 μH Further improvements can be made to the efficiency of this circuit by: • Adding a 1 A Schottky diode between the LX node and ground. • Using an inductor with a lower DCR. Measured efficiency for this circuit 90.0 TA = 25°C Efficiency, η (%) 88.0 86.0 84.0 TA = 75°C 82.0 80.0 78.0 0 0.5 1.0 1.5 2.0 2.5 Output Current, IOUT (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Application circuit 4 C2 10 nF L1 10 μH VIN 12 V BOOT VIN C1 10 μF R1 187 kΩ VOUT 2.5 V LX A8670 C3 10 μF TON ILIM Vpull-up C4 10 μF R5 31.6 k Ω EN R2 20 kΩ R3 20 kΩ FB POK FAULT POK SS BIAS AGND PGND C6 100 nF C5 10 nF R6 10 kΩ COMP FAULT R4 24 k Ω C7 1 nF C8 18 pF Operating Characteristics: VIN = 12 V, VOUT = 2.5 V, fSW = 500 kHz Inductor used: Taiyo Yuden NR8040 10 μH Further improvements can be made to the efficiency of this circuit by: • Adding a 1 A Schottky diode between the LX node and ground. • Using an inductor with a lower DCR. Measured efficiency for this circuit 92.0 TA = 25°C Efficiency, η (%) 90.0 88.0 TA = 75°C 86.0 84.0 82.0 80.0 0 0.5 1.0 1.5 2.0 2.5 Output Current, IOUT (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Application circuit 5 C2 10 nF L1 10 μH VIN 12 V BOOT VIN C1 10 μF R1 243 k Ω VOUT 3.3 V LX A8670 C3 10 μF TON ILIM Vpull-up C4 10 μF R5 45 kΩ EN R2 20 kΩ R3 20 kΩ FB POK FAULT POK SS BIAS AGND PGND C6 100 nF C5 10 nF R6 10 kΩ COMP FAULT R4 33 k Ω C7 1 nF C8 15 pF Operating Characteristics: VIN = 12 V, VOUT = 3.3 V, fSW = 500 kHz Inductor used: Taiyo Yuden NR8040 10 μH Further improvements can be made to the efficiency of this circuit by: • Adding a 1 A Schottky diode between the LX node and ground. • Using an inductor with a lower DCR. Measured efficiency for this circuit 96.0 Efficiency, η (%) 94.0 TA = 25°C 92.0 90.0 TA = 75°C 88.0 86.0 84.0 0 0.5 1.0 1.5 2.0 2.5 Output Current, IOUT (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Application circuit 6 C2 10 nF L1 10 μH VIN 12 V BOOT VIN C1 10 μF R1 374 k Ω VOUT 5.0 V LX A8670 C3 10 μF TON ILIM Vpull-up C4 10 μF R5 73.2 k Ω EN R2 20 kΩ R3 20 kΩ FB POK FAULT POK SS BIAS AGND PGND C6 100 nF C5 10 nF R6 10 kΩ COMP FAULT R4 51 k Ω C7 1 nF C8 10 pF Operating Characteristics: VIN = 12 V, VOUT = 5.0 V, fSW = 500 kHz Inductor used: Taiyo Yuden NR8040 10 μH Further improvements can be made to the efficiency of this circuit by: • Adding a 1 A Schottky diode between the LX node and ground. • Using an inductor with a lower DCR. Measured efficiency for this circuit 96.0 TA = 25°C Efficiency, η (%) 94.0 92.0 TA = 75°C 90.0 88.0 86.0 84.0 0 0.5 1.0 1.5 2.0 2.5 Output Current, IOUT (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Package ES, 20-Contact QFN 0.30 4.00 ±0.10 1 2 0.50 20 20 0.95 A 1 2 4.00 ±0.10 2.6 4.10 2.6 4.10 21X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 0.75 ±0.05 0.50 BSC C C PCB Layout Reference View For Reference Only, not for tooling use (reference DWG-2864, excluding pad) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) 0.40 ±0.10 B 2.6 2 1 C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 20 2.6 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 Fixed Frequency, 2 A Synchronous Buck Regulator With Fault Warnings and Power OK A8670 Revision History Revision Revision Date Rev. 2 March 29, 2012 Description of Revision Update ton(max) and various minor changes Copyright ©2011-2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27