ON MC100E116 Quint differential line receiver Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MC10E/100E116 is a quint differential line receiver with
emitter-follower outputs. An internally generated reference supply (VBB)
is available for single-ended reception.
•
•
•
•
•
500ps Max. Propagation Delay
QUINT DIFFERENTIAL
LINE RECEIVER
VBB Supply Output
Dedicated VCCO Pin for Each Receiver
Extended 100E VEE Range of – 4.2V to – 5.46V
75kΩ Input Pulldown Resistors
Active current sources plus a deep collector feature of the MOSAIC III
process provide the receivers with excellent common-mode noise
rejection. Each receiver has a dedicated VCCO supply lead, providing
optimum symmetry and stability.
The receiver design features clamp circuitry to cause a defined state if
both the inverting and non-inverting inputs are left open; in this case the Q
output goes LOW, while the Q output goes HIGH. This feature makes the
FN SUFFIX
device ideal for twisted pair applications.
PLASTIC PACKAGE
If both inverting and non-inverting inputs are at an equal potential of
CASE 776-02
> –2.5V, the receiver does not go to a defined state, but rather
current-shares in normal differential amplifier fashion, producing output
voltage levels midway between HIGH and LOW, or the device may even
oscillate.
The device VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only.
When using for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor. Please refer to the interface
section of the design guide for information on using the E116 in specialized applications.
The E116 features input pull-down resistors, as does the rest of the ECLinPS family. For applications which require
bandwidths greater than that of the E116, the E416 device may be of interest.
Pinout: 28-Lead PLCC (Top View)
PIN NAMES
Pin
D0, D0 – D4, D4
Q0, Q0 – Q4, Q4
VBB
D3
D4
D4
VCCO
Q4
Q4
VCCO
25
24
23
22
21
20
19
D3
26
18
Q3
D2
27
17
Q3
D2
28
16
VCC
VEE
1
15
Q2
VBB
2
14
Q2
D0
3
13
VCCO
D0
4
12
Q1
Function
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output.
5
6
7
8
9
10
11
D1
D1
VCCO
Q0
Q0
VCCO
Q1
* All VCC and VCCO pins are tied together on the die.
5/95
 Motorola, Inc. 1996
2–1
REV 3
MC10E116 MC100E116
LOGIC DIAGRAM
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D4
Q4
VBB
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
–40°C
Symbol
VBB
Characteristic
Output Reference
Voltage
10E
100E
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VPP(DC)
VCMR
Min
Typ
0°C
Max
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Cond
V
–1.43
–1.38
–1.30
–1.26
–1.38
–1.38
–1.27
–1.26
200
–1.35
–1.38
–1.25
–1.26
200
–1.31
–1.38
–1.19
–1.26
200
200
µA
mA
29
29
Input Sensitivity
150
Commom Mode
Range
–2.0
35
35
29
29
35
35
150
–0.6
–2.0
29
29
35
35
29
29
150
–0.6
35
40
150
–2.0
–0.6
–2.0
–0.6
mV
1
V
2
1. Differential input voltage required to obtain a full ECL swing on the outputs.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
–40°C
Symbol
0°C to 85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
tPLH
tPHL
Propagation Delay to Output
D (Differential)
D (Single-Ended)
150
150
300
300
500
550
200
150
300
300
450
500
tskew
tskew
Within-Device Skew
VPP(AC)
tr/tf
Minimum Input Swing
150
Rise/Fall Time
250
Duty Cycle Skew
Unit
Condition
ps
50
50
±10
tPLH – tPHL
±10
150
375
625
275
375
575
ps
1
ps
2
mV
3
ps
20–80%
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
3. Minimum input swing for which AC parameters are guaranteed.
MOTOROLA
2–2
ECLinPS and ECLinPS Lite
DL140 — Rev 4
MC10E116 MC100E116
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
Y BRK
-N-
T L –M
M
U
0.007 (0.180)
X
G1
M
S
N
T L –M
S
S
N
S
D
Z
-L-
-M-
D
W
28
V
1
C
A
0.007 (0.180)
M
R
0.007 (0.180)
M
T L –M
S
T L –M
S
N
S
N
S
H
S
N
S
0.007 (0.180)
M
T L –M
N
S
S
0.004 (0.100)
G
J
-T-
K
SEATING
PLANE
F
VIEW S
G1
T L –M
S
N
0.007 (0.180)
M
T L –M
S
N
S
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
ECLinPS and ECLinPS Lite
DL140 — Rev 4
T L –M
K1
E
S
S
VIEW D-D
Z
0.010 (0.250)
0.010 (0.250)
2–3
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
—
0.025
—
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
—
0.020
2°
10°
0.410 0.430
0.040
—
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
10.42 10.92
1.02
—
MOTOROLA
MC10E116 MC100E116
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MOTOROLA
2–4
*MC10E116/D*
MC10E116/D
ECLinPS and ECLinPS Lite
DL140 — Rev 4
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