Am49LV6408M Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 30918 Revision A Amendment 0 Issue Date November 5, 2003 THIS PAGE LEFT INTENTIONALLY BLANK. ADVANCE INFORMATION Am49LV6408M Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 2.7 to 3.3 volt ■ High Performance — Access time as fast as 100ns initial 5 ns page Flash 55 ns pSRAM ■ Package — 69-Ball FBGA — Look ahead pinout for simple migration — 8 x 10 x 1.2 mm ■ Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Single power supply operation — 3 V for read, erase, and program operations ■ Manufactured on 0.23 µm MirrorBit process technology ■ SecSi™ (Secured Silicon) Sector region — 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer ■ Flexible sector architecture — One hundred twenty seven 32 Kword sectors — Eight 4 Kword boot sectors ■ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ■ Minimum 100,000 erase cycle guarantee per sector ■ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS ■ High performance — 100 ns access time — 35 ns page read times — 0.5 s typical sector erase time — 22 µs typical write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word updates — 4-word page read buffer — 16-word write buffer ■ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical initial Page read current; 10 mA typical intra-Page read current — 50 mA typical erase/program current — 1 µA typical standby mode current SOFTWARE & HARDWARE FEATURES ■ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices ■ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: VID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects top or bottom two sectors regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device pSRAM Features ■ As fast as 55ns access time ■ Power dissipation — Operating: 23 mA maximum — Standby: 60 µA maximum at 3.0 V ■ CE1ps# and CE2ps Chip Select ■ Power down features using CE1ps# and CE2ps ■ Data retention supply voltage: 1.5 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 30918 Rev: A Amendment/0 Issue Date: November 5, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION Am29LV640MH/L Features The Am29LV640MH/L is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words. The device has an 16-bit bus and can be programmed either in the host system or in standard EPROM programmers. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the 2 DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Requirements for Reading Array Data ................................... 11 Page Mode Read ................................................................ 11 Writing Commands/Command Sequences ............................ 11 Write Buffer ......................................................................... 11 Accelerated Program Operation .......................................... 11 Autoselect Functions ........................................................... 11 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12 Table 2. Am29LV640MT Top Boot Sector Architecture ..................12 Table 3. Am29LV640MB Bottom Boot Sector Architecture .............15 Sector Group Protection and Unprotection ............................. 18 Table 4. Am29LV640MT Top Boot Sector Protection .....................18 Table 5. Am29LV640MB Bottom Boot Sector Protection ................18 Write Protect (WP#) ................................................................ 19 Temporary Sector Group Unprotect ....................................... 19 Figure 1. Temporary Sector Group Unprotect Operation................ 19 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20 SecSi (Secured Silicon) Sector Flash Memory Region .......... 21 Table 6. SecSi Sector Contents ......................................................21 Figure 3. SecSi Sector Protect Verify.............................................. 22 Hardware Data Protection ...................................................... 22 Low VCC Write Inhibit ......................................................... 22 Write Pulse “Glitch” Protection ............................................ 22 Logical Inhibit ...................................................................... 22 Power-Up Write Inhibit ......................................................... 22 Common Flash Memory Interface (CFI) . . . . . . . 22 Command Definitions . . . . . . . . . . . . . . . . . . . . . 25 Reading Array Data ................................................................ 25 Reset Command ..................................................................... 26 Autoselect Command Sequence ............................................ 26 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 26 Word Program Command Sequence ..................................... 26 Unlock Bypass Command Sequence .................................. 27 Write Buffer Programming ................................................... 27 Accelerated Program ........................................................... 28 Figure 4. Write Buffer Programming Operation............................... 29 Figure 5. Program Operation .......................................................... 30 Program Suspend/Program Resume Command Sequence ... 30 Figure 6. Program Suspend/Program Resume............................... 31 Chip Erase Command Sequence ........................................... 31 Sector Erase Command Sequence ........................................ 31 Figure 7. Erase Operation............................................................... 32 Erase Suspend/Erase Resume Commands ........................... 32 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 34 DQ7: Data# Polling ................................................................. 34 Figure 8. Data# Polling Algorithm ................................................... 34 Figure 9. Toggle Bit Algorithm........................................................ 36 DQ2: Toggle Bit II ................................................................... 36 Reading Toggle Bits DQ6/DQ2 ............................................... 36 DQ5: Exceeded Timing Limits ................................................ 37 DQ3: Sector Erase Timer ....................................................... 37 DQ1: Write-to-Buffer Abort ..................................................... 37 Table 12. Write Operation Status ................................................... 37 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38 Figure 10. Maximum Negative Overshoot Waveform ................... 38 Figure 11. Maximum Positive Overshoot Waveform..................... 38 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Pseudo SRAM DC and Operating Characteristics . . . . . . . . . . . . . . . . . . Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38 39 40 41 Figure 12. Test Setup.................................................................... 41 Table 13. Test Specifications ......................................................... 41 Key to Switching Waveforms. . . . . . . . . . . . . . . . 41 Figure 13. Input Waveforms and Measurement Levels ................. 41 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 Flash Read-Only Operations ................................................. 42 Figure 14. Read Operation Timings ............................................... 42 Figure 15. Page Read Timings ...................................................... 43 Hardware Reset (RESET#) .................................................... 44 Figure 16. Reset Timings ............................................................... 44 Erase and Program Operations .............................................. 45 Figure 17. Program Operation Timings.......................................... Figure 18. Accelerated Program Timing Diagram.......................... Figure 19. Chip/Sector Erase Operation Timings .......................... Figure 20. Data# Polling Timings (During Embedded Algorithms)...................................................... Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... Figure 22. DQ2 vs. DQ6................................................................. 46 46 47 48 49 49 Temporary Sector Unprotect .................................................. 50 Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 50 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 51 Alternate CE# Controlled Erase and Program Operations ..... 52 Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 53 Pseudo SRAM AC Characteristics . . . . . . . . . . . 54 Power Up Time ....................................................................... 54 Read Cycle ............................................................................. 54 Figure 26. Pseudo SRAM Read Cycle—Address Controlled......... 54 Figure 27. Pseudo SRAM Read Cycle........................................... 55 Write Cycle ............................................................................. 56 Figure 28. Pseudo SRAM Write Cycle—WE# Control ................... 56 Figure 29. Pseudo SRAM Write Cycle—CE1#s Control ................ 57 Flash Erase And Programming Performance . . 58 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 58 BGA Package Capacitance . . . . . . . . . . . . . . . . . 58 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60 TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA) 8 x 10 mm Package ................................................................ 60 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61 DQ6: Toggle Bit I .................................................................... 35 November 5, 2003 Am49LV6408M 3 A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE Am49LV6408M Family Part Number Flash Memory Standard Voltage Range: VCC = 2.7–3.3 V pSRAM 10, 15 11 15 10, 11 Max Access Time (ns) 100 110 55 70 Max. CE# Access (ns) 100 110 55 70 Max. Page Access Time (tPACC) 35 40 N/A N/A OE# Access (ns) 35 40 30 35 Speed Option Note: See “AC Characteristics” for full specifications. MCP BLOCK DIAGRAM VCCf VSS A21 to A0 RY/BY# A21 to A0 WP#/ACC RESET# CE#f 64 M Bit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs/VCCQ VSS/VSSQ A0 toto A19 A18 A0 LB#ps UB#ps WE# OE# CE1#ps CE2ps 4 8 M Bit pseudo Static RAM DQ15 to DQ0 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N FLASH MEMORY BLOCK DIAGRAM DQ15–DQ0 VCC Sector Switches VSS Erase Voltage Generator Input/Output Buffers RESET#f WE# WP#/ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE#f OE# VCC Detector Timer A21–A0 November 5, 2003 Am49LV6408M Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 5 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAMS 69-ball Fine-pitch BGA Top View, Balls Facing Down Flash only A1 A5 A6 A10 NC NC NC NC B5 B6 B7 B8 LB# WP#/ACC WE# A8 A11 C3 C4 C7 C8 C9 A3 A6 UB# A19 A12 A15 D2 D3 D4 D5 D6 D7 D8 D9 A2 A5 A18 RY/BY# A20 A9 A13 A21 E1 E2 E3 E4 E7 E8 E9 E10 NC A1 A4 A17 A10 A14 NC NC F1 F2 F3 F4 F7 F8 F9 F10 NC A0 VSS DQ1 DQ6 NC A16 NC G2 G3 G4 G5 G6 G7 G8 G9 CE#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 NC H2 H3 H4 H5 H6 H7 H8 H9 CE1#ps DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS J3 J4 J5 J6 J7 J8 DQ8 DQ2 DQ11 NC DQ5 DQ14 K1 K5 K6 K10 NC NC NC NC B1 B3 B4 NC A7 C2 C5 C6 RESET# CE2ps SPECIAL PACKAGE HANDLING INSTRUCTIONS FOR FBGA PACKAGES Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data 6 pSRAM only Shared integrity may be compromised if the package body is exposed to temperatures about 150°C for prolonged periods of time. Am49LV6408M November 5, 2003 A D V A N C E PIN DESCRIPTION A21–A0 I N F O R M A T I O N LOGIC SYMBOL = 22 Address inputs 22 DQ15–DQ0 = 16 Data inputs/outputs CE#f A21–A0 = Chip Enable input (Flash) CE1#ps 16 DQ15–DQ0 CE1#ps, CE2ps= Chip Enable (pSRAM) CE2ps OE# = Output Enable input (Flash) WE# = Write Enable input (Flash) WP#/ACC = Hardware Write Protect input/Programming Acceleration input (Flash) WP#/ACC RESET#f = Hardware Reset Pin input (Flash) RESET#f VCCf = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) UB#ps VCCps = pSRAM Power Supply VSS = Device Ground NC = Pin Not Connected Internally UB#ps = Upper Byte Control (pSRAM) LB#ps = Lower Byte Control (pSRAM) November 5, 2003 OE# WE# Am49LV6408M LB#ps RY/BY# 7 A D V A N C E I N F O R M A T I O N ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49LV640 8 M T 10 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector PROCESS TECHNOLOGY M = 0.23 µm MirrorBit pSRAM DEVICE DENSITY 8 = 8 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49LV6408M Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM Am29LV640M 64 Megabit (4 M x 16-Bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM Valid Combinations Valid Combinations Order Number Package Marking Am49LV6408MT15I M49000003Z Am49LV6408MB15I M49000004A Am49LV6408MT10I Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations M49000002T T 8 Am49LV6408MB10I M49000002U Am49LV6408MT11I M49000002V Am49LV6408MB11I M49000002X Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the November 5, 2003 register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am49LV6408M 9 A D V A N C E Table 1. Operation (Notes 1, 2) H X X L H X X L VCC ± 0.3 V H X X L Output Disable L L H Flash Hardware Reset X H X X L H X X L H X X L H X X L L Write to Flash L Sector Protect (Note 5) L Sector Unprotect (Note 5) L Temporary Sector Unprotect X Read from pSRAM Write to pSRAM Device Bus Operations CE#f CE1#ps CE2ps OE# WE# Read from Flash Standby I N F O R M A T I O N H H L L H H Addr. LB#s UB#s RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 L H AIN X X H L/H DOUT DOUT H L AIN X X H (Note 4) DIN DIN X X X X X VCC ± 0.3 V H High-Z High-Z H H X L X H H X X L H L/H High-Z High-Z X X X X X L L/H High-Z High-Z L SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X H L SADD, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X X X X X VID (Note 6) DIN High-Z L L DOUT DOUT H L X H L AIN AIN H L High-Z DOUT L H DOUT High-Z L L DIN DIN H L High-Z DIN L H DIN High-Z H H X X Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#ps = VIL and CE2ps = VIH at the same time. 3. Don’t care or open LB#ps or UB#ps. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector Group Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. 10 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Flash Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. November 5, 2003 An erase operation can erase one sector, multiple sectors, or the entire device. Tables 3 and 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector Group Protection and Unprotection and Autoselect Command Sequence sections for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within Am49LV6408M 11 A D V A N C E I N F O R M A T I O N VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RETable 2. 12 SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29LV640MT Top Boot Sector Architecture Sector Sector Address A21–A12 Sector Size (Kwords) SA0 0000000xxx 32 00000h–07FFFh SA1 0000001xxx 32 08000h–0FFFFh SA2 0000010xxx 32 10000h–17FFFh SA3 0000011xxx 32 18000h–1FFFFh SA4 0000100xxx 32 20000h–27FFFh SA5 0000101xxx 32 28000h–2FFFFh SA6 0000110xxx 32 30000h–37FFFh SA7 0000111xxx 32 38000h–3FFFFh SA8 0001000xxx 32 40000h–47FFFh SA9 0001001xxx 32 48000h–4FFFFh SA10 0001010xxx 32 50000h–57FFFh SA11 0001011xxx 32 58000h–5FFFFh SA12 0001100xxx 32 60000h–67FFFh SA13 0001101xxx 32 68000h–6FFFFh SA14 0001101xxx 32 70000h–77FFFh SA15 0001111xxx 32 78000h–7FFFFh SA16 0010000xxx 32 80000h–87FFFh SA17 0010001xxx 32 88000h–8FFFFh SA18 0010010xxx 32 90000h–97FFFh SA19 0010011xxx 32 98000h–9FFFFh SA20 0010100xxx 32 A0000h–A7FFFh SA21 0010101xxx 32 A8000h–AFFFFh SA22 0010110xxx 32 B0000h–B7FFFh SA23 0010111xxx 32 B8000h–BFFFFh SA24 0011000xxx 32 C0000h–C7FFFh Am49LV6408M (x16) Address Range November 5, 2003 A D V A N C E Table 2. I N F O R M A T I O N Am29LV640MT Top Boot Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA25 0011001xxx 32 C8000h–CFFFFh SA26 0011010xxx 32 D0000h–D7FFFh SA27 0011011xxx 32 D8000h–DFFFFh SA28 0011000xxx 32 E0000h–E7FFFh SA29 0011101xxx 32 E8000h–EFFFFh SA30 0011110xxx 32 F0000h–F7FFFh SA31 0011111xxx 32 F8000h–FFFFFh SA32 0100000xxx 32 F9000h–107FFFh SA33 0100001xxx 32 108000h–10FFFFh SA34 0100010xxx 32 110000h–117FFFh SA35 0101011xxx 32 118000h–11FFFFh SA36 0100100xxx 32 120000h–127FFFh SA37 0100101xxx 32 128000h–12FFFFh SA38 0100110xxx 32 130000h–137FFFh SA39 0100111xxx 32 138000h–13FFFFh SA40 0101000xxx 32 140000h–147FFFh SA41 0101001xxx 32 148000h–14FFFFh SA42 0101010xxx 32 150000h–157FFFh SA43 0101011xxx 32 158000h–15FFFFh SA44 0101100xxx 32 160000h–167FFFh SA45 0101101xxx 32 168000h–16FFFFh SA46 0101110xxx 32 170000h–177FFFh SA47 0101111xxx 32 178000h–17FFFFh SA48 0110000xxx 32 180000h–187FFFh SA49 0110001xxx 32 188000h–18FFFFh SA50 0110010xxx 32 190000h–197FFFh SA51 0110011xxx 32 198000h–19FFFFh SA52 0100100xxx 32 1A0000h–1A7FFFh SA53 0110101xxx 32 1A8000h–1AFFFFh SA54 0110110xxx 32 1B0000h–1B7FFFh SA55 0110111xxx 32 1B8000h–1BFFFFh SA56 0111000xxx 32 1C0000h–1C7FFFh SA57 0111001xxx 32 1C8000h–1CFFFFh SA58 0111010xxx 32 1D0000h–1D7FFFh SA59 0111011xxx 32 1D8000h–1DFFFFh SA60 0111100xxx 32 1E0000h–1E7FFFh SA61 0111101xxx 32 1E8000h–1EFFFFh SA62 0111110xxx 32 1F0000h–1F7FFFh SA63 0111111xxx 32 1F8000h–1FFFFFh SA64 1000000xxx 32 200000h–207FFFh SA65 1000001xxx 32 208000h–20FFFFh SA66 1000010xxx 32 210000h–217FFFh SA67 1000011xxx 32 218000h–21FFFFh SA68 1000100xxx 32 220000h–227FFFh SA69 1000101xxx 32 228000h–22FFFFh SA70 1000110xxx 32 230000h–237FFFh SA71 1000111xxx 32 238000h–23FFFFh SA72 1001000xxx 32 240000h–247FFFh SA73 1001001xxx 32 248000h–24FFFFh SA74 1001010xxx 32 250000h–257FFFh SA75 1001011xxx 32 258000h–25FFFFh SA76 1001100xxx 32 260000h–267FFFh SA77 1001101xxx 32 268000h–26FFFFh SA78 1001110xxx 32 270000h–277FFFh SA79 1001111xxx 32 278000h–27FFFFh November 5, 2003 Am49LV6408M 13 A D V A N C E Table 2. 14 I N F O R M A T I O N Am29LV640MT Top Boot Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA80 1010000xxx 32 280000h–28FFFFh SA81 1010001xxx 32 288000h–28FFFFh SA82 1010010xxx 32 290000h–297FFFh SA83 1010011xxx 32 298000h–29FFFFh SA84 1010100xxx 32 2A0000h–2A7FFFh SA85 1010101xxx 32 2A8000h–2AFFFFh SA86 1010110xxx 32 2B0000h–2B7FFFh SA87 1010111xxx 32 2B8000h–2BFFFFh SA88 1011000xxx 32 2C0000h–2C7FFFh SA89 1011001xxx 32 2C8000h–2CFFFFh SA90 1011010xxx 32 2D0000h–2D7FFFh SA91 1011011xxx 32 2D8000h–2DFFFFh SA92 1011100xxx 32 2E0000h–2E7FFFh SA93 1011101xxx 32 2E8000h–2EFFFFh SA94 1011110xxx 32 2F0000h–2FFFFFh SA95 1011111xxx 32 2F8000h–2FFFFFh SA96 1100000xxx 32 300000h–307FFFh SA97 1100001xxx 32 308000h–30FFFFh SA98 1100010xxx 32 310000h–317FFFh SA99 1100011xxx 32 318000h–31FFFFh SA100 1100100xxx 32 320000h–327FFFh SA101 1100101xxx 32 328000h–32FFFFh SA102 1100110xxx 32 330000h–337FFFh SA103 1100111xxx 32 338000h–33FFFFh SA104 1101000xxx 32 340000h–347FFFh SA105 1101001xxx 32 348000h–34FFFFh SA106 1101010xxx 32 350000h–357FFFh SA107 1101011xxx 32 358000h–35FFFFh SA108 1101100xxx 32 360000h–367FFFh SA109 1101101xxx 32 368000h–36FFFFh SA110 1101110xxx 32 370000h–377FFFh SA111 1101111xxx 32 378000h–37FFFFh SA112 1110000xxx 32 380000h–387FFFh SA113 1110001xxx 32 388000h–38FFFFh SA114 1110010xxx 32 390000h–397FFFh SA115 1110011xxx 32 398000h–39FFFFh SA116 1110100xxx 32 3A0000h–3A7FFFh SA117 1110101xxx 32 3A8000h–3AFFFFh SA118 1110110xxx 32 3B0000h–3B7FFFh SA119 1110111xxx 32 3B8000h–3BFFFFh SA120 1111000xxx 32 3C0000h–3C7FFFh SA121 1111001xxx 32 3C8000h–3CFFFFh SA122 1111010xxx 32 3D0000h–3D7FFFh SA123 1111011xxx 32 3D8000h–3DFFFFh SA124 1111100xxx 32 3E0000h–3E7FFFh SA125 1111101xxx 32 3E8000h–3EFFFFh SA126 1111110xxx 32 3F0000h–3F7FFFh SA127 1111111000 4 3F8000h–3F8FFFh SA128 1111111001 4 3F9000h–3F9FFFh SA129 1111111010 4 3FA000h–3FAFFFh SA130 1111111011 4 3FB000h–3FBFFFh SA131 1111111100 4 3FC000h–3FCFFFh SA132 1111111101 4 3FD000h–3FDFFFh SA133 1111111110 4 3FE000h–3FEFFFh SA134 1111111111 4 3FF000h–3FFFFFh Am49LV6408M November 5, 2003 A D V A N C E Table 3. I N F O R M A T I O N Am29LV640MB Bottom Boot Sector Architecture Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA0 0000000000 4 00000h–00FFFh SA1 0000000001 4 01000h–01FFFh SA2 0000000010 4 02000h–02FFFh SA3 0000000011 4 03000h–03FFFh SA4 0000000100 4 04000h–04FFFh SA5 0000000101 4 05000h–05FFFh SA6 0000000110 4 06000h–06FFFh SA7 0000000111 4 07000h–07FFFh SA8 0000001xxx 32 08000h–0FFFFh SA9 0000010xxx 32 10000h–17FFFh SA10 0000011xxx 32 18000h–1FFFFh SA11 0000100xxx 32 20000h–27FFFh SA12 0000101xxx 32 28000h–2FFFFh SA13 0000110xxx 32 30000h–37FFFh SA14 0000111xxx 32 38000h–3FFFFh SA15 0001000xxx 32 40000h–47FFFh SA16 0001001xxx 32 48000h–4FFFFh SA17 0001010xxx 32 50000h–57FFFh SA18 0001011xxx 32 58000h–5FFFFh SA19 0001100xxx 32 60000h–67FFFh SA20 0001101xxx 32 68000h–6FFFFh SA21 0001101xxx 32 70000h–77FFFh SA22 0001111xxx 32 78000h–7FFFFh SA23 0010000xxx 32 80000h–87FFFh SA24 0010001xxx 32 88000h–8FFFFh SA25 0010010xxx 32 90000h–97FFFh SA26 0010011xxx 32 98000h–9FFFFh SA27 0010100xxx 32 A0000h–A7FFFh SA28 0010101xxx 32 A8000h–AFFFFh SA29 0010110xxx 32 B0000h–B7FFFh SA30 0010111xxx 32 B8000h–BFFFFh SA31 0011000xxx 32 C0000h–C7FFFh SA32 0011001xxx 32 C8000h–CFFFFh SA33 0011010xxx 32 D0000h–D7FFFh SA34 0011011xxx 32 D8000h–DFFFFh SA35 0011000xxx 32 E0000h–E7FFFh SA36 0011101xxx 32 E8000h–EFFFFh SA37 0011110xxx 32 F0000h–F7FFFh SA38 0011111xxx 32 F8000h–FFFFFh SA39 0100000xxx 32 F9000h–107FFFh SA40 0100001xxx 32 108000h–10FFFFh SA41 0100010xxx 32 110000h–117FFFh SA42 0101011xxx 32 118000h–11FFFFh SA43 0100100xxx 32 120000h–127FFFh SA44 0100101xxx 32 128000h–12FFFFh SA45 0100110xxx 32 130000h–137FFFh SA46 0100111xxx 32 138000h–13FFFFh SA47 0101000xxx 32 140000h–147FFFh SA48 0101001xxx 32 148000h–14FFFFh SA49 0101010xxx 32 150000h–157FFFh SA50 0101011xxx 32 158000h–15FFFFh SA51 0101100xxx 32 160000h–167FFFh SA52 0101101xxx 32 168000h–16FFFFh SA53 0101110xxx 32 170000h–177FFFh SA54 0101111xxx 32 178000h–17FFFFh November 5, 2003 Am49LV6408M 15 A D V A N C E Table 3. 16 I N F O R M A T I O N Am29LV640MB Bottom Boot Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA55 0110000xxx 32 180000h–187FFFh SA56 0110001xxx 32 188000h–18FFFFh SA57 0110010xxx 32 190000h–197FFFh SA58 0110011xxx 32 198000h–19FFFFh SA59 0100100xxx 32 1A0000h–1A7FFFh SA60 0110101xxx 32 1A8000h–1AFFFFh SA61 0110110xxx 32 1B0000h–1B7FFFh SA62 0110111xxx 32 1B8000h–1BFFFFh SA63 0111000xxx 32 1C0000h–1C7FFFh SA64 0111001xxx 32 1C8000h–1CFFFFh SA65 0111010xxx 32 1D0000h–1D7FFFh SA66 0111011xxx 32 1D8000h–1DFFFFh SA67 0111100xxx 32 1E0000h–1E7FFFh SA68 0111101xxx 32 1E8000h–1EFFFFh SA69 0111110xxx 32 1F0000h–1F7FFFh SA70 0111111xxx 32 1F8000h–1FFFFFh SA71 1000000xxx 32 200000h–207FFFh SA72 1000001xxx 32 208000h–20FFFFh SA73 1000010xxx 32 210000h–217FFFh SA74 1000011xxx 32 218000h–21FFFFh SA75 1000100xxx 32 220000h–227FFFh SA76 1000101xxx 32 228000h–22FFFFh SA77 1000110xxx 32 230000h–237FFFh SA78 1000111xxx 32 238000h–23FFFFh SA79 1001000xxx 32 240000h–247FFFh SA80 1001001xxx 32 248000h–24FFFFh SA81 1001010xxx 32 250000h–257FFFh SA82 1001011xxx 32 258000h–25FFFFh SA83 1001100xxx 32 260000h–267FFFh SA84 1001101xxx 32 268000h–26FFFFh SA85 1001110xxx 32 270000h–277FFFh SA86 1001111xxx 32 278000h–27FFFFh SA87 1010000xxx 32 280000h–28FFFFh SA88 1010001xxx 32 288000h–28FFFFh SA89 1010010xxx 32 290000h–297FFFh SA90 1010011xxx 32 298000h–29FFFFh SA91 1010100xxx 32 2A0000h–2A7FFFh SA92 1010101xxx 32 2A8000h–2AFFFFh SA93 1010110xxx 32 2B0000h–2B7FFFh SA94 1010111xxx 32 2B8000h–2BFFFFh SA95 1011000xxx 32 2C0000h–2C7FFFh SA96 1011001xxx 32 2C8000h–2CFFFFh SA97 1011010xxx 32 2D0000h–2D7FFFh SA98 1011011xxx 32 2D8000h–2DFFFFh SA99 1011100xxx 32 2E0000h–2E7FFFh SA100 1011101xxx 32 2E8000h–2EFFFFh SA101 1011110xxx 32 2F0000h–2FFFFFh SA102 1011111xxx 32 2F8000h–2FFFFFh SA103 1100000xxx 32 300000h–307FFFh SA104 1100001xxx 32 308000h–30FFFFh SA105 1100010xxx 32 310000h–317FFFh SA106 1100011xxx 32 318000h–31FFFFh SA107 1100100xxx 32 320000h–327FFFh SA108 1100101xxx 32 328000h–32FFFFh SA109 1100110xxx 32 330000h–337FFFh Am49LV6408M November 5, 2003 A D V A N C E Table 3. I N F O R M A T I O N Am29LV640MB Bottom Boot Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA110 1100111xxx 32 338000h–33FFFFh SA111 1101000xxx 32 340000h–347FFFh SA112 1101001xxx 32 348000h–34FFFFh SA113 1101010xxx 32 350000h–357FFFh SA114 1101011xxx 32 358000h–35FFFFh SA115 1101100xxx 32 360000h–367FFFh SA116 1101101xxx 32 368000h–36FFFFh SA117 1101110xxx 32 370000h–377FFFh SA118 1101111xxx 32 378000h–37FFFFh SA119 1110000xxx 32 380000h–387FFFh SA120 1110001xxx 32 388000h–38FFFFh SA121 1110010xxx 32 390000h–397FFFh SA122 1110011xxx 32 398000h–39FFFFh SA123 1110100xxx 32 3A0000h–3A7FFFh SA124 1110101xxx 32 3A8000h–3AFFFFh SA125 1110110xxx 32 3B0000h–3B7FFFh SA126 1110111xxx 32 3B8000h–3BFFFFh SA127 1111000xxx 32 3C0000h–3C7FFFh SA128 1111001xxx 32 3C8000h–3CFFFFh SA129 1111010xxx 32 3D0000h–3D7FFFh SA130 1111011xxx 32 3D8000h–3DFFFFh SA131 1111100xxx 32 3E0000h–3E7FFFh SA132 1111101xxx 32 3E8000h–3EFFFFh SA133 1111110xxx 32 3F0000h–3F7FFFh SA134 1111111000 32 3F8000h–3FFFFFh November 5, 2003 Am49LV6408M 17 A D V A N C E I N F O R M A T I O N Sector Group Protection and Unprotection Sector A21–A12 Sector/ Sector Block Size SA80-SA83 10100XXXXX 256 (4x64) Kbytes SA84-SA87 10101XXXXX 256 (4x64) Kbytes SA88-SA91 10110XXXXX 256 (4x64) Kbytes SA92-SA95 10111XXXXX 256 (4x64) Kbytes SA96-SA99 11000XXXXX 256 (4x64) Kbytes SA100-SA103 11001XXXXX 256 (4x64) Kbytes SA104-SA107 11010XXXXX 256 (4x64) Kbytes SA108-SA111 11011XXXXX 256 (4x64) Kbytes SA112-SA115 11100XXXXX 256 (4x64) Kbytes SA116-SA119 11101XXXXX 256 (4x64) Kbytes SA120-SA123 11110XXXXX 256 (4x64) Kbytes SA124-SA126 1111100XXX 1111101XXX 1111110XXX 192 (3x64) Kbytes SA127 1111111000 8 Kbytes SA128 1111111001 8 Kbytes The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. SA129 1111111010 8 Kbytes SA130 1111111011 8 Kbytes SA131 1111111100 8 Kbytes SA132 1111111101 8 Kbytes SA133 1111111110 8 Kbytes It is possible to determine whether a sector group is protected or unprotected. See the Sector Group Protection and Unprotection section for details. SA134 1111111111 8 Kbytes The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Tables 4 and 5). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. Table 4. 18 Table 5. Am29LV640MT Top Boot Sector Protection Am29LV640MB Bottom Boot Sector Protection Sector A21–A12 Sector/ Sector Block Size SA0 0000000000 8 Kbytes Sector A21–A12 Sector/ Sector Block Size SA0-SA3 00000XXXXX 256 (4x64) Kbytes SA1 0000000001 8 Kbytes SA4-SA7 00001XXXXX 256 (4x64) Kbytes SA2 0000000010 8 Kbytes SA8-SA11 00010XXXXX 256 (4x64) Kbytes SA3 0000000011 8 Kbytes SA12-SA15 00011XXXXX 256 (4x64) Kbytes SA4 0000000100 8 Kbytes SA16-SA19 00100XXXXX 256 (4x64) Kbytes SA5 0000000101 8 Kbytes SA20-SA23 00101XXXXX 256 (4x64) Kbytes SA6 0000000110 8 Kbytes SA24-SA27 00110XXXXX 256 (4x64) Kbytes SA7 0000000111 8 Kbytes SA28-SA31 00111XXXXX 256 (4x64) Kbytes SA32-SA35 01000XXXXX 256 (4x64) Kbytes SA8–SA10 0000001XXX, 0000010XXX, 0000011XXX, 192 (3x64) Kbytes SA36-SA39 01001XXXXX 256 (4x64) Kbytes SA11–SA14 00001XXXXX 256 (4x64) Kbytes SA40-SA43 01010XXXXX 256 (4x64) Kbytes SA15–SA18 00010XXXXX 256 (4x64) Kbytes SA44-SA47 01011XXXXX 256 (4x64) Kbytes SA19–SA22 00011XXXXX 256 (4x64) Kbytes SA48-SA51 01100XXXXX 256 (4x64) Kbytes SA52-SA55 01101XXXXX 256 (4x64) Kbytes SA56-SA59 01110XXXXX 256 (4x64) Kbytes SA60-SA63 01111XXXXX 256 (4x64) Kbytes SA64-SA67 10000XXXXX 256 (4x64) Kbytes SA68-SA71 10001XXXXX 256 (4x64) Kbytes SA72-SA75 10010XXXXX 256 (4x64) Kbytes SA76-SA79 10011XXXXX 256 (4x64) Kbytes SA23–SA26 00100XXXXX 256 (4x64) Kbytes SA27-SA30 00101XXXXX 256 (4x64) Kbytes SA31-SA34 00110XXXXX 256 (4x64) Kbytes SA35-SA38 00111XXXXX 256 (4x64) Kbytes SA39-SA42 01000XXXXX 256 (4x64) Kbytes SA43-SA46 01001XXXXX 256 (4x64) Kbytes SA47-SA50 01010XXXXX 256 (4x64) Kbytes SA51-SA54 01011XXXXX 256 (4x64) Kbytes Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N Temporary Sector Group Unprotect Table 5. Am29LV640MB Bottom Boot Sector Protection (Continued) Sector A21–A12 Sector/ Sector Block Size SA55–SA58 01100XXXXX 256 (4x64) Kbytes SA59–SA62 01101XXXXX 256 (4x64) Kbytes SA63–SA66 01110XXXXX 256 (4x64) Kbytes SA67–SA70 01111XXXXX 256 (4x64) Kbytes SA71–SA74 10000XXXXX 256 (4x64) Kbytes SA75–SA78 10001XXXXX 256 (4x64) Kbytes SA79–SA82 10010XXXXX 256 (4x64) Kbytes SA83–SA86 10011XXXXX 256 (4x64) Kbytes SA87–SA90 10100XXXXX 256 (4x64) Kbytes SA91–SA94 10101XXXXX 256 (4x64) Kbytes SA95–SA98 10110XXXXX 256 (4x64) Kbytes SA99–SA102 10111XXXXX 256 (4x64) Kbytes SA103–SA106 11000XXXXX 256 (4x64) Kbytes SA107–SA110 11001XXXXX 256 (4x64) Kbytes SA111–SA114 11010XXXXX 256 (4x64) Kbytes SA115–SA118 11011XXXXX 256 (4x64) Kbytes SA119–SA122 11100XXXXX 256 (4x64) Kbytes SA123–SA126 11101XXXXX 256 (4x64) Kbytes SA127–SA130 11110XXXXX 256 (4x64) Kbytes SA131–SA134 11111XXXXX 256 (4x64) Kbytes (Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 5). This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Write Protect (WP#) The Write Protect function provides a hardware method of protecting the top two or bottom two sectors without using V ID. WP# is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in “DC Characteristics”. Temporary Sector Group Unprotect Completed (Note 2) Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the top or bottom two sectors were previously set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note: No external pullup is necessary since the WP#/ACC pin has internal pullup to VCC November 5, 2003 Am49LV6408M Figure 1. Temporary Sector Group Unprotect Operation 19 A D V A N C E I N F O R M A T I O N START START PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Group Unprotect Mode No PLSCNT = 1 Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address RESET# = VID Wait 1 µs First Write Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector group address No All sector groups protected? Yes Sector Group Protect: Write 60h to sector group address with A6–A0 = 0xx0010 Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6–A0 = 1xx0010 Wait 150 µs Verify Sector Group Protect: Write 40h to sector group address with A6–A0 = 0xx0010 Increment PLSCNT Temporary Sector Group Unprotect Mode No Reset PLSCNT = 1 Read from sector group address with A6–A0 = 0xx0010 Wait 15 ms Verify Sector Group Unprotect: Write 40h to sector group address with A6–A0 = 1xx0010 Increment PLSCNT No No PLSCNT = 25? Read from sector group address with A6–A0 = 1xx0010 Data = 01h? Yes No Yes Device failed Protect another sector group? Yes PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Group Protect Algorithm Set up next sector group address No Data = 00h? Yes Last sector group verified? No Yes Sector Group Protect complete Sector Group Unprotect Algorithm Remove VID from RESET# Write reset command Sector Group Unprotect complete Figure 2. 20 In-System Sector Group Protect/Unprotect Algorithms Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N SecSi (Secured Silicon) Sector Flash Memory Region Factory Locked: SecSi Sector Programmed and Protected At the Factory The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. See Table 6 for SecSi Sector addressing. AMD offers the device with the SecSi Sector either fac t or y l ocke d or c u s t om e r l o ckabl e. T he fac tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The SecSi sector address space in this device is allocated as follows: Table 6. SecSi Sector Address Range x16 000000h– 000007h 000008h– 00007Fh SecSi Sector Contents Standard Factory Locked ExpressFlash Factory Locked ESN ESN or determined by customer Unavailable Determined by customer Customer Lockable Determined by customer The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. November 5, 2003 Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word/256 bytes SecSi sector. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. Am49LV6408M 21 A D V A N C E I N F O R M A T I O N hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. START RESET# = VIH or VID Wait 1 µs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Remove VIH or VID from RESET# Write reset command Write Pulse “Glitch” Protection SecSi Sector Protect Verify complete Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Figure 3. Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. SecSi Sector Protect Verify Power-Up Write Inhibit Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 11 and 12 for command definitions). In addition, the following If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 7–10. To terminate reading CFI data, the system must write the reset command. 22 The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7–10. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Am49LV6408M November 5, 2003 A D V A N C E Table 7. I N F O R M A T I O N CFI Query Identification String Addresses (x16) Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 8. System Interface String Addresses (x16) Data 1Bh 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0007h Typical timeout per single byte/word write 2N µs 20h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0001h Max. timeout for byte/word write 2N times typical 24h 0005h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) November 5, 2003 Description Am49LV6408M 23 A D V A N C E Table 9. Addresses (x16) 24 I N F O R M A T I O N Device Geometry Definition Data Description N 27h 0017h Device Size = 2 byte 28h 29h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0005h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0002h Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) 2Dh 2Eh 2Fh 30h 007Fh 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 007Eh 0000h 0000h 0001h Erase Block Region 2 Information (refer to CFI publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to CFI publication 100) Am49LV6408M November 5, 2003 A D V A N C E Table 10. I N F O R M A T I O N Primary Vendor-Specific Extended Query Addresses (x16) Data 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII 45h 0008h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Description Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 0000h Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0001h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00B5h 4Eh 00C5h 4Fh 0002h/ 0003h 50h 0001h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Tables 11 and 12 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens November 5, 2003 first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any Am49LV6408M 25 A D V A N C E I N F O R M A T I O N non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. 26 Identifier Code A7:A0 (x16) Manufacturer ID 00h Device ID, Cycle 1 01h Device ID, Cycle 2 0Eh Device ID, Cycle 3 0Fh SecSi Sector Factory Protect 03h Sector Protect Verify (SA)02h Note: The device ID is read over three cycles. SA = Sector Address Tables 11 and 12 show the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 11 and 12 show the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N internally generated program pulses and verifies the programmed cell margin. Tables 11 and 12 show the address and data requirements for the word program command sequence. Note that the autoselect and CFI functions are unavailable when a program operation is in progress. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 11 and 12 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. November 5, 2003 Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A MAX–A 4 . All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host s y s t e m m u s t t h e r e fo r e a c c o u n t fo r l o a d i n g a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. Am49LV6408M 27 A D V A N C E I N F O R M A T I O N The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. The Write Buffer Programming Sequence can be aborted in the following ways: Accelerated Program ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset 28 The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N Write “Write to Buffer” command and Sector Address Part of “Write to Buffer” Command Sequence Write number of addresses to program minus 1(WC) and Sector Address Write first address/data Yes WC = 0 ? No Write to a different sector address Abort Write to Buffer Operation? Yes Write to buffer ABORTED. Must write “Write-to-buffer Abort Reset” command sequence to return to read mode. No (Note 1) Write next address/data pair WC = WC - 1 Write program buffer to flash sector address Notes: 1. Read DQ7 - DQ0 at Last Loaded Address No 2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. 3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. Yes DQ7 = Data? No No DQ1 = 1? DQ5 = 1? Yes Yes When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 4. See Table 12 for command sequences required for write buffer programming. Read DQ7 - DQ0 with address = Last Loaded Address (Note 2) DQ7 = Data? Yes No (Note 3) FAIL or ABORT Figure 4. November 5, 2003 PASS Write Buffer Programming Operation Am49LV6408M 29 A D V A N C E I N F O R M A T I O N Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 µs maximum (5 µs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 12 for program command sequence. Figure 5. Program Operation No After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. 30 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on these status bits. Program Operation or Write-to-Buffer Sequence in Progress Write address/data XXXh/B0h Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Wait 15 µs Read data as required No Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors Done reading? Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend Figure 6. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Sector Erase Command Sequence Yes Write address/data XXXh/30h Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 11 and 12 shows the address and data requirements for the chip erase command sequence. Note that the autoselect and CFI functions are unavailable when an erase operation is in progress. Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Tables 11 and 12 shows the address and data requirements for the sector erase command sequence. Note that the autoselect and CFI functions are unavailable when an erase operation is in progress. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e ct o r E ra se o r E ra s e S u s p en d d u r i n g th e time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- November 5, 2003 Am49LV6408M 31 A D V A N C E I N F O R M A T I O N ing edge of the final WE# pulse in the command sequence. Erase Suspend/Erase Resume Commands When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Sector Group Protection and Unprotection and Autoselect Command Sequence sections for details. Yes Erasure Completed Notes: 1. See Table 12 and Table 12 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. 32 After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. Data = FFh? Figure 7. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Erase Operation Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N Command Definitions Table 11. Read (Note 5) Autoselect (Note 7) Reset (Note 6) Bus Cycles (Notes 1–4) Cycles Command Sequence (Notes) Command Definitions Addr Data 1 RA RD First Second Third Fourth Fifth Addr Data Addr Data Addr Data 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E SecSi™ Sector Factory Protect (Note 9) 4 555 AA 2AA 55 555 90 X03 (Note 9) Sector Group Protect Verify (Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 00/01 Sixth Addr Data Addr Data X0E 2210 X0F 2200/ 2201 PA PD WBL PD Enter SecSi Sector Region 3 555 AA 2AA 55 555 88 Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 11) 6 555 AA 2AA 55 SA 25 SA WC Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (Note 12) 3 555 AA 2AA 55 555 F0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (Note 15) 1 BA B0 Program/Erase Resume (Note 16) 1 BA 30 CFI Query (Note 17) 1 55 98 Legend: X = Don’t care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address . Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. bottom two address sectors, the data is 88h for factory locked and 08h for not factor locked. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 10. The data is 00h for an unprotected sector group and 01h for a protected sector group. 4. During unlock cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 21. 5. No unlock or command cycles required when device is in read mode. 12. Command sequence resets device for next command after aborted write-to-buffer operation. 6. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high while the device is providing status information. 13. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 14. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 7. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. Except RD, PD and WC. See the Autoselect Command Sequence section for more information. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 8. The device ID must be read in three cycles. The data is 2201h for top boot and 2200h for bottom boot. 16. The Erase Resume command is valid only during the Erase Suspend mode. 9. If WP# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the 17. Command is valid when device is ready to read array data or when device is in autoselect mode. November 5, 2003 Am49LV6408M 33 A D V A N C E I N F O R M A T I O N WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 20 in the AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling START The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Read DQ7–DQ0 Addr = VA During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has 34 Yes DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am49LV6408M Figure 8. Data# Polling Algorithm November 5, 2003 A D V A N C E I N F O R M A T I O N RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. November 5, 2003 After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. Am49LV6408M 35 A D V A N C E I N F O R M A T I O N DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. START Read DQ7–DQ0 DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ6. Read DQ7–DQ0 Toggle Bit = Toggle? No Yes No Figure 9 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? Reading Toggle Bits DQ6/DQ2 No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 9. Toggle Bit Algorithm Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform 36 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9). DQ5: Exceeded Timing Limits DQ5 indic ates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- Table 12. Standard Mode Program Suspend Mode Erase Suspend Mode Write-toBuffer Status Embedded Program Algorithm Embedded Erase Algorithm Program-Suspended Program- Sector Suspend Non-Program Read Suspended Sector Erase-Suspended EraseSector Suspend Non-Erase Suspended Read Sector Erase-Suspend-Program (Embedded Program) Busy (Note 3) Abort (Note 4) mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 relative to the other status bits. DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Write Operation Status DQ7 (Note 2) DQ7# 0 1 DQ6 Toggle Toggle No toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/BY# 0 0 Invalid (not allowed) 1 Data 1 0 N/A Toggle N/A Data 1 1 DQ7# Toggle 0 N/A N/A N/A 0 DQ7# DQ7# Toggle Toggle 0 0 N/A N/A N/A N/A 0 1 0 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to ‘1’ when tthe device has aborted the write-to-buffer operation. November 5, 2003 Am49LV6408M 37 A D V A N C E I N F O R M A T I O N ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V 20 ns 20 ns +0.8 V –0.5 V –2.0 V RESET#f (Note 2) . . . . . . . . . . . . –0.5 V to +12.5 V 20 ns WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V Figure 10. Maximum Negative Overshoot Waveform All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 10. During voltage transitions, input or I/O pins may overshoot to V CC +2.0 V for periods up to 20 ns. See Figure 11. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to –2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 11. Maximum Positive Overshoot Waveform 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Supply Voltages VCCf/VCCs for full voltage range . . . . . . . . . . 2.7–3.3 V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. 38 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N DC Characteristics CMOS Compatible Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ±1.0 µA ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH, ICC2 VCC Initial Page Read Current (2, 3) ICC3 ICC4 5 MHz 15 20 1 MHz 15 20 CE# = VIL, OE# = VIH 30 50 mA VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH 10 20 mA VCC Active Write Current (3, 4) CE# = VIL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 1 5 µA ICC6 VCC Reset Current (3) RESET# = VSS ± 0.3 V, WP# = VIH 1 5 µA ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 1 5 µA mA VIL1 Input Low Voltage 1(6, 7) –0.5 0.8 V VIH1 Input High Voltage 1 (6, 7) 1.9 VCC + 0.5 V VIL2 Input Low Voltage 2 (6, 8) –0.5 0.3 x VIO V VIH2 Input High Voltage 2 (6, 8) 1.9 VIO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage (9) IOL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage VOH2 VLKO IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V Low VCC Lock-Out Voltage (10) 2.3 Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum ICC specifications are tested with VCC = VCCmax. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. November 5, 2003 2.5 V 6. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V. 7. VCC voltage requirements. 8. VIO voltage requirements. 9. Includes RY/BY# 10. Not 100% tested. Am49LV6408M 39 A D V A N C E I N F O R M A T I O N PSEUDO SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 3 5 mA ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 12 25 mA VIL Input Low Voltage –0.2 (Note 3) 0.4 V VIH Input High Voltage 2.2 VCC+0.2 (Note 2) V VOL Output Low Voltage IOL = 2.0 mA 0.4 V VOH Output High Voltage IOH = –1.0 mA ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL 0.3 mA ISB1 Standby Current (CMOS) CE1#s=VIH, CE2= VIL: Other inputs = VIH or VIL: tA = 85°C, VCC = 3.0 V 60 µA ISB2 Standby Current (CMOS) CE1#s=VIH, CE2= VIL: Other inputs = VIH or VIL: tA = 85°C, VCC = 3.3 V 85 µA 2.2 V Notes: 1. TA= –40° to 85°C, otherwise specified. 2. 3. 4. 5. 40 Overshoot: VCC+1.0V if pulse width ≤ 20 ns. Undershoot: –1.0V if pulse width ≤ 20 ns. Overshoot and undershoot are sampled, not 100% tested. Stable power supply required 200 µs before device operation. Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N TEST CONDITIONS Table 13. 3.3 V Test Condition 2.7 kΩ Device Under Test CL Test Specifications 6.2 kΩ All Speeds Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 12. Unit Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 1.5 V Output 0.0 V Figure 13. November 5, 2003 Input Waveforms and Measurement Levels Am49LV6408M 41 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Speed Std. Description Test Setup tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay 10, 15 11 Unit Min 100 110 ns CE#, OE# = VIL Max 100 110 ns OE# = VIL Max 100 110 ns Max 35 40 ns 35 40 ns tPACC Page Access Time tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns Read Min 0 ns tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling Min 10 ns Notes: 1. Not 100% tested. 2. See Figure 12 and Table 12 for test specifications. tRC Addresses Stable Addresses tACC CE#f tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET#f RY/BY# 0V Figure 14. 42 Read Operation Timings Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Same Page A21-A2 A1-A0 Aa Ab tPACC tACC Data Bus Qa Ad Ac tPACC Qb tPACC Qc Qd CE#f OE# Figure 15. November 5, 2003 Page Read Timings Am49LV6408M 43 A D V A N C E I N F O R M A T I O N AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std. Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 ms tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Input Low to Standby Mode Min 20 µs tRB RY/BY# Output High to CE#, OE# pin Low Min 0 ns Notes: 1. Not 100% tested. 2. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ¼ VCC. CE#f, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CE#f, OE# RESET# tRP Figure 16. 44 Reset Timings Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N AC Characteristics Erase and Program Operations Parameter Speed Options JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 352 µs tWLAX tWHWH1 tWHWH2 tWHWH1 10, 15 11 Unit 100 110 ns Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2, 5) Word Typ 100 Single Word/Byte Accelerated Programming Operation (Note 2, 5) Word Typ 90 µs tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY WE# High to RY/BY# Low Min 100 110 ns Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 5. Word programming specification is based upon a single word programming operation not utilizing the write buffer. November 5, 2003 Am49LV6408M 45 A D V A N C E I N F O R M A T I O N AC Characteristics Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE#f tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status DOUT VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. Illustration shows device in word mode. Figure 17. Program Operation Timings VHH ACC VIL or VIH VIL or VIH tVHH Figure 18. 46 tVHH Accelerated Program Timing Diagram Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N AC Characteristics Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE#f tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h 30h In Progress Complete 10 for Chip Erase tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”. 2. Illustration shows device in word mode. Figure 19. November 5, 2003 Chip/Sector Erase Operation Timings Am49LV6408M 47 A D V A N C E I N F O R M A T I O N AC Characteristics tRC Addresses VA VA VA tACC tCE CE#f tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data True Valid Data High Z True Valid Data Notes:Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Data# Polling Timings (During Embedded Algorithms) 48 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N AC Characteristics tAHT tAS Addresses tAHT tASO CE#f tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Data Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 22. November 5, 2003 DQ2 vs. DQ6 Am49LV6408M 49 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: Not 100% tested. VID RESET# VID VSS, VIL, or VIH VSS, VIL, or VIH tVIDR tVIDR Program or Erase Command Sequence CE#f WE# tRSP Figure 23. 50 Temporary Sector Group Unprotect Timing Diagram Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N AC Characteristics VID VIH RESET# SA, A6, A3, A2, A1, A0 Valid* Valid* Sector Group Protect or Unprotect Data 60h 60h Valid* Verify 40h Status Sector Group Protect: 150 µs, Sector Group Unprotect: 15 ms 1 µs CE# WE# OE# Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010. Figure 24. November 5, 2003 Sector Group Protect and Unprotect Timing Diagram Am49LV6408M 51 A D V A N C E I N F O R M A T I O N AC Characteristics Alternate CE# Controlled Erase and Program Operations Parameter Speed Options JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 352 µs tWHWH1 tWHWH2 tWHWH1 10, 15 11 Unit 100 110 ns Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2, 5) Word Typ 100 Single Word/Byte Accelerated Programming Operation (Note 2, 5) Word Typ 90 µs tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tRH RESET# High Time Before Write Min 50 ns Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 5. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 52 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE#f tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. Figure 25. November 5, 2003 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am49LV6408M 53 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS Power Up Time When powering up the pSRAM, maintain VCCs for 100 µs minimum with CE#1ps at VIH. Read Cycle Parameter Symbol Speed Description Unit 15 10, 11 tRC Read Cycle Time Min 55 70 ns tAA Address Access Time Max 55 70 ns tCO1, tCO2 Chip Enable to Output Max 55 70 ns tOE Output Enable Access Time Max 30 35 ns tBA LB#ps, UB#ps to Access Time Max 55 70 ns Chip Enable (CE1#ps Low and CE2ps High) to Low-Z Output Min 5 tBLZ UB#ps, LB#ps Enable to Low-Z Output Min 5 ns tOLZ Output Enable to Low-Z Output Min 5 ns tHZ1, tHZ2 Chip Disable to High-Z Output Max 20 25 ns tBHZ UB#ps, LB#ps Disable to High-Z Output Max 20 25 ns tOHZ Output Disable to High-Z Output Max 20 25 ns tOH Output Data Hold from Address Change Min tLZ1, tLZ2 ns 10 ns tRC Address tOH Data Out tAA Data Valid Previous Data Valid Notes: 1. CE1#ps = OE# = VIL, CE2ps = WE# = VIH, UB#ps and/or LB#ps = VIL 2. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs. Figure 26. 54 Pseudo SRAM Read Cycle—Address Controlled Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS Read Cycle tRC Address tAA tCO1 CE#1s CE2s tOH tCO2 tHZ tBA UB#s, LB#s tBHZ tOE OE# Data Out High-Z tOLZ tBLZ tLZ tOHZ Data Valid Notes: 1. WE# = VIH. 2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. 4. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs. Figure 27. November 5, 2003 Pseudo SRAM Read Cycle Am49LV6408M 55 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS Write Cycle Parameter Symbol Speed Description Unit 55 70 tWC Write Cycle Time Min 55 70 ns tCw Chip Enable to End of Write Min 45 55 ns tAS Address Setup Time Min tAW Address Valid to End of Write Min 45 55 ns tBW UB#s, LB#s to End of Write Min 45 55 ns tWP Write Pulse Time Min 45 55 ns tWR Write Recovery Time Min 0 Min 0 tWHZ Write to Output High-Z Max 25 tDW Data to Write Time Overlap Min 40 ns tDH Data Hold from Write Time Min 0 ns tOW End Write to Output Low-Z Min 5 ns 0 ns ns ns tWC Address tWR tCW (See Note 1) CE1#s tAW CE2s tCW (See Note 1) tWP (See Note 4) WE# Data In tAS (See Note 3) tDW High-Z High-Z Data Valid tWHZ Data Out tDH tOW Data Undefined Notes: 1. WE# controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 28. 56 Pseudo SRAM Write Cycle—WE# Control Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS tWC Address tAS (See Note 2 ) tCW (See Note 3) tWR (See Note 4) CE1#s tAW CE2s tBW UB#s, LB#s tWP (See Note 5) WE# tDW tDH Data Valid Data In Data Out High-Z High-Z Notes: 1. CE1#s controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 29. November 5, 2003 Pseudo SRAM Write Cycle—CE1#s Control Am49LV6408M 57 A D V A N C E I N F O R M A T I O N FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Max (Note 2) Typ (Note 1) Unit Sector Erase Time 0.5 15 sec Chip Erase Time 32 128 sec Single Word Program Time (Note 3) Word 100 µs Accelerated Single Word Program Time (Note 3) Word 90 µs 352 µs 22 µs Total Accelerated Effective Write Buffer Program Time (Note 4) 282 µs Effective Accelerated Write Buffer PRogram Word Time (Note 4) 17.6 µs Chip Program Time 92 sec Total Write Buffer Program Time (Note 4) Effective Write Buffer Program Time (Note 5) Per Word Comments Notes: 1. Typical program and erase times assume the following conditions: 25×C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 4. For 1-16 words programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 12 and 11 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA PACKAGE CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 Fine-pitch BGA 4.2 5.0 pF COUT Output Capacitance VOUT = 0 Fine-pitch BGA 5.4 6.5 pF CIN2 Control Pin Capacitance VIN = 0 Fine-pitch BGA 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. 58 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time November 5, 2003 Am49LV6408M 59 A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA) 8 x 10 mm Package D1 A D eD 0.15 C 10 (2X) 9 8 SE 7 7 6 E E1 5 4 eE 3 2 1 K INDEX MARK PIN A1 CORNER J H B 10 TOP VIEW G F E D C B A 7 SD 0.15 C PIN A1 CORNER (2X) BOTTOM VIEW 0.20 C A A2 A1 C 69X 0.15 0.08 0.08 C SIDE VIEW 6 b M C A B M C NOTES: PACKAGE TLB 069 JEDEC 10.00 mm X 8.00 mm PACKAGE SYMBOL A MIN. --- A1 0.20 A2 0.81 NOM. --- NOTE MAX. 1.20 --- --- --- 0.97 PROFILE BALL HEIGHT 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX IN THE "D" DIRECTION. BODY SIZE E 8.00 BSC BODY SIZE D1 7.20 BSC MATRIX FOOTPRINT MATRIX FOOTPRINT E1 7.20 BSC MD 10 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 69 0.33 --- SYMBOL "ME" IS THE BALL MATRIX IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 10.00 BSC eE DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BODY THICKNESS D Ob 1. N/A 6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL COUNT 0.43 0.80 BSC BALL DIAMETER WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = E/2 BALL PITCH eD 0.80 BSC BALL PITCH SD/SE 0.40 BSC SOLDER BALL PLACEMENT A2,A3,A4,A7,A8,A9,B2,B9,B10 C1,C10,D1,D10,E5,E6,F5,F6 G1,G10,H1,H10 J1,J2,J9,J10,K2,K3,K4,K7,K8,K9 DEPOPULATED SOLDER BALLS 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. NOT USED. 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. w052903-163814C 60 Am49LV6408M November 5, 2003 A D V A N C E I N F O R M A T I O N REVISION SUMMARY Revision A (November 5, 2003) Initial release. Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 5, 2003 Am49LV6408M 61