Microchip MCP6024T-E/ST Rail-to-rail input/output, 10 mhz op amp Datasheet

M
MCP6021/2/3/4
Rail-to-Rail Input/Output, 10 MHz Op Amps
Features
Description
•
•
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The MCP6021, MCP6022, MCP6023 and MCP6024
from Microchip Technology Inc. are rail-to-rail input and
output op amps with high performance. Key
specifications include: wide bandwidth (10 MHz), low
noise (8.7 nV/√Hz), low input offset voltage and low
distortion (0.00053% THD+N). These features make
these op amps well suited for applications requiring
high performance and bandwidth. The MCP6023 also
offers a chip select pin (CS) that gives power savings
when the part is not in use.
•
•
•
•
•
•
Rail-to-Rail Input/Output
Wide Bandwidth: 10 MHz (typ.)
Low Noise: 8.7 nV/√Hz, at 10 kHz (typ.)
Low Offset Voltage:
- Industrial Temperature: ±500 µV (max.)
- Extended Temperature: ±250 µV (max.)
Mid-Supply V REF: MCP6021 and MCP6023
Low Supply Current: 1 mA (typ.)
Total Harmonic Distortion: 0.00053% (typ., G = 1)
Unity Gain Stable
Power Supply Range: 2.5V to 5.5V
Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
The single MCP6021, single MCP6023 and dual
MCP6022 are available in standard 8-lead PDIP, SOIC
and TSSOP. The quad MCP6024 is offered in 14-lead
PDIP, SOIC and TSSOP packages.
The MCP6021/2/3/4 family is available in the Industrial
and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
Typical Applications
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•
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Automotive
Driving A/D Converters
Multi-Pole Active Filters
Barcode Scanners
Audio Processing
Communications
DAC Buffer
Test Equipment
Medical Instrumentation
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® software (at www.microchip.com)
PACKAGE TYPES
MCP6021
PDIP SOIC, TSSOP
NC 1
VIN– 2
VIN+ 3
VSS 4
MCP6022
PDIP SOIC, TSSOP
8 NC VOUTA 1
7 VDD VINA– 2
6 VOUT VINA+ 3
5 VREF
 2003 Microchip Technology Inc.
VSS 4
MCP6023
PDIP SOIC, TSSOP
NC 1
8 VDD
V
IN– 2
7 VOUTB
6 VINB– VIN+ 3
5 V + VSS 4
INB
MCP6024
PDIP SOIC, TSSOP
8 CS
7 VDD
VOUTA 1
VINA– 2
14 VOUTD
13 VIND–
6 VOUT
VINA+ 3
VDD 4
12 VIND+
11 VSS
VINB+ 5
VINB– 6
VOUTB 7
10 VINC+
9 VINC–
5 VREF
8 VOUTC
DS21685B-page 1
MCP6021/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
Pin Function Table
Name
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All Inputs and Outputs ..................... VSS - 0.3V to V DD + 0.3V
Difference Input Voltage ....................................... |VDD - VSS|
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Junction Temperature.................................................. +150°C
ESD Protection on all pins (HBM/MM) ................ ≥ 2 kV / 200V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Function
VIN +, VINA+, VINB+, VINC+, VIND+
Non-inverting Inputs
VIN –, VINA–, VINB–, VINC–, VIND–
Inverting Inputs
VDD
Positive Power Supply
VSS
Negative Power Supply
CS
Chip Select
VREF
Reference Voltage
VOUT, VOUTA, VOUTB, VOUTC ,
VOUTD
Outputs
NC
No Internal Connection
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2 and R L = 10 kΩ to VDD/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Industrial Temperature Parts
VOS
-500
—
+500
µV
VCM = 0V
Extended Temperature Parts
VOS
-250
—
+250
µV
VCM = 0V, VDD = 5.0V
Extended Temperature Parts
VOS
-2.5
—
+2.5
mV
VCM = 0V, VDD = 5.0V
TA = -40°C to +125°C
Input Offset Voltage Temperature Drift
∆VOS/∆TA
—
±3.5
—
PSRR
74
90
—
IB
—
1
—
pA
IB
—
30
150
pA
TA = +85°C
TA = +125°C
Input Offset
Input Offset Voltage:
Power Supply Rejection Ratio
µV/°C TA = -40°C to +125°C
dB
VCM = 0V
Input Current and Impedance
Input Bias Current
Industrial Temperature Parts
IB
—
640
5,000
pA
Input Offset Current
IOS
—
±1
—
pA
Common-Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||3
—
Ω||pF
Common-Mode Input Range
VCMR
VSS-0.3
—
VDD +0.3
V
Common-Mode Rejection Ratio
CMRR
74
90
—
dB
VDD = 5V, VCM = -0.3V to 5.3V
CMRR
70
85
—
dB
VDD = 5V, VCM = 3.0V to 5.3V
CMRR
74
90
—
dB
VDD = 5V, VCM = -0.3V to 3.0V
Extended Temperature Parts
Common-Mode
Voltage Reference (MCP6021 and MCP6023 only)
VREF Accuracy (VREF - VDD /2)
VREF Temperature Drift
∆VREF
-50
—
+50
∆VREF /∆T
—
±100
—
90
110
—
mV
µV/°C TA = -40°C to +125°C
A
Open Loop Gain
DC Open Loop Gain (Large Signal)
DS21685B-page 2
AOL
dB
VCM = 0V,
VOUT = VSS+0.3V to VDD -0.3V
 2003 Microchip Technology Inc.
MCP6021/2/3/4
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2 and R L = 10 kΩ to VDD/2.
Parameters
Sym
Min
Typ
Max
Units
V OL, VOH
ISC
VSS+15
—
VDD -20
mV
—
±30
—
mA
Supply Voltage
VS
2.5
—
5.5
V
Quiescent Current per Amplifier
IQ
0.5
1.0
1.35
mA
Conditions
Output
Maximum Output Voltage Swing
Output Short Circuit Current
0.5V output overdrive
Power Supply
IO = 0
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, V CM = VDD/2, VOUT ≈ VDD /2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
GBWP
—
10
—
MHz
PM
—
65
—
°
tSETTLE
—
250
—
ns
SR
—
7.0
—
V/µs
Conditions
AC Response
Gain Bandwidth Product
Phase Margin at Unity-Gain
Settling Time, 0.2%
Slew Rate
G=1
G = 1, VOUT = 100 mVp-p
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = 1
THD+N
—
0.00053
—
%
VOUT = 0.25V + 3.25V, BW = 22 kHz
f = 1 kHz, G = 1, RL = 600Ω@1 KHz
THD+N
—
0.00064
—
%
VOUT = 0.25V + 3.25V, BW = 22 kHz
f = 1 kHz, G = +1 V/V
THD+N
—
0.0014
—
%
VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +10 V/V
THD+N
—
0.0009
—
%
VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +100 V/V
THD+N
—
0.005
—
%
VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
Input Voltage Noise
Eni
—
2.9
—
µVp-p
f = 0.1 Hz to 10 Hz
Input Voltage Noise Density
eni
—
8.7
—
nV/√Hz
f = 10 kHz
Input Current Noise Density
ini
—
3
—
fA/√Hz
f = 1 kHz
Noise
MCP6023 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
CS Logic Threshold, Low
VIL
0
—
0.2VDD
V
CS Input Current, Low
ICSL
-1.0
0.01
—
µA
CS Logic Threshold, High
VIH
0.8VDD
—
VDD
V
CS Input Current, High
Conditions
DC Characteristics
CS = VSS
ICSH
—
0.01
2.0
µA
CS = VDD
CS Input High, GND Current
ISS
—
0.05
2.0
µA
CS = VDD
Amplifier Output Leakage
—
—
0.01
—
µA
CS = VDD
CS Low to Amplifier Output
Turn-on Time
tON
—
2
10
µs
G = 1, VIN = VSS,
CS = 0.2VDD to VOUT = 0.45VDD time
CS High to Amplifier Output
High-Z Turn-off Time
tOFF
—
0.01
—
µs
G = 1, VIN = VSS,
CS = 0.8VDD to VOUT = 0.05VDD time
VHYST
—
0.6
—
V
Internal Switch
Timing
Hysteresis
 2003 Microchip Technology Inc.
DS21685B-page 3
MCP6021/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, V DD = +2.5V to +5.5V and V SS = GND.
Parameters
Symbol
Min
Typ
Max
Units
TA
-40
—
+85
°C
Extended Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Industrial Temperature Range
Note 1
Thermal Package Resistances
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
124
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note 1:
The industrial temperature devices operate over this extended temperature range, but with reduced
performance. In any case, the internal junction temperature (TJ) must not exceed the absolute maximum
specification of 150°C.
CS
tON
VOUT
Hi-Z
ISS 50 nA (typ.)
ICS
10 nA (typ.)
tOFF
Amplifier On
Hi-Z
1 mA (typ.)
50 nA (typ.)
10 nA (typ.)
10 nA (typ.)
FIGURE 1-1:
Timing diagram for the CS
pin on the MCP6023.
DS21685B-page 4
 2003 Microchip Technology Inc.
MCP6021/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Input Offset Voltage (µV)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.5V.
12
8
10
6
20
16
12
8
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
-40°C
+25°C
+85°C
+125°C
1.5
1.0
0.5
VDD = 5.5V
0.0
Input Offset Voltage (µV)
Input Offset Voltage (µV)
3.0
500
400
300
200
100
0
-100
-200
-300
-400
-500
-0.5
2.5
Common Mode Input Voltage (V)
 2003 Microchip Technology Inc.
-4
FIGURE 2-5:
Input Offset Voltage Drift,
(Extended Temperature Parts).
-40°C
+25°C
+85°C
+125°C
2.0
-8
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage,
(Extended Temperature Parts).
1.5
-12
-16
Input Offset Voltage (µV)
1.0
438 Samples
VCM = 0V
TA = -40°C to +125°C
E-Temp
Parts
4
26%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-20
200
160
120
80
40
0
-40
Percentage of Occurances
FIGURE 2-4:
Input Offset Voltage Drift,
(Industrial Temperature Parts).
E-Temp
Parts
-80
-120
-160
-200
Percentage of Occurances
438 Samples
VDD = 5.0V
VCM = 0V
TA = +25°C
500
400 VDD = 2.5V
300
200
100
0
-100
-200
-300
-400
-500
-0.5
0.0
0.5
4
Input Offset Voltage Drift (µV/°C)
FIGURE 2-1:
Input Offset Voltage,
(Industrial Temperature Parts).
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
2
500
400
300
200
100
0
-100
-200
-300
-400
0%
0
2%
-2
4%
I-Temp
Parts
-4
6%
-6
8%
1192 Samples
TA = -40°C to +85°C
-8
10%
12%
11%
10%
9%
8%
7%
6%
5%
4%
3%
2%
1%
0%
-10
12%
I-Temp
Parts
-12
14%
1192 Samples
TA = +25°C
Percentage of Occurances
16%
-500
Percentage of Occurances
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
DS21685B-page 5
MCP6021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
200
Input Offset Voltage (µV)
50
0
-50
-100
-150
-200
VDD = 5.0V
VCM = 0V
-250
VDD = 5.5V
50
0
VDD = 2.5V
-50
-100
-150
Output Voltage (V)
FIGURE 2-10:
Output Voltage.
1.E+00
1.E+01
1
10
FIGURE 2-8:
vs. Frequency.
1.E+02
1.E+03
1.E+04
100
1k
10k
Frequency (Hz)
1.E+05
8
6
4
2
1.E+06
100k 1M
0
5.0
1.E-01
0.1
10
4.5
1
12
4.0
10
f = 1 kHz
VDD = 5.0V
14
3.5
100
16
0.0
Input Noise Voltage Density
(nV/—Hz)
1,000
Input Offset Voltage vs.
3.0
Input Offset Voltage vs.
2.5
FIGURE 2-7:
Temperature.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
125
2.0
0
25
50
75
100
Ambient Temperature (°C)
1.5
-25
1.0
-50
Input Noise Voltage Density
(nV/—Hz)
100
-200
-300
Common Mode Input Voltage (V)
Input Noise Voltage Density
FIGURE 2-11:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
100
110
PSRR+
PSRR-
105
PSRR, CMRR (dB)
90
CMRR, PSRR (dB)
VCM = VDD/2
150
0.5
Input Offset Voltage (µV)
100
80
70
60
CMRR
50
40
CMRR
100
95
90
PSRR (VCM = 0V)
85
80
75
30
20
100
1.E+02
70
1.E+03
1k
1.E+04
10k
1.E+05
100k
Frequency (Hz)
FIGURE 2-9:
Common Mode, Power
Supply Rejection Ratios vs. Frequency.
DS21685B-page 6
1.E+06
1M
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-12:
Common Mode, Power
Supply Rejection Ratios vs. Temperature.
 2003 Microchip Technology Inc.
MCP6021/2/3/4
IB, TA = +125°C
VDD = 5.5V
1,000
IOS, TA = +125°C
IB, TA = +85°C
100
10
IOS, TA = +85°C
1
10,000
VCM = VDD
VDD = 5.5V
1,000
IB
100
IOS
10
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
25 35 45 55 65 75 85 95 105 115 125
Common Mode Input Voltage (V)
Ambient Temperature (°C)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
+125°C
+85°C
+25°C
-40°C
FIGURE 2-16:
vs. Temperature.
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD = 5.5V
VDD = 2.5V
VCM = VDD - 0.5V
-50
-25
FIGURE 2-17:
Temperature.
35
30
25
20
15
10
5
+125°C
+85°C
+25°C
-40°C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Open-Loop Gain (dB)
Output Short Circuit Current
(mA)
Quiescent Current vs.
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
1.E+00
1
 2003 Microchip Technology Inc.
25
50
75
100
125
1.E+01
Quiescent Current vs.
1.E+02
1.E+03
10 100 1k
0
-15
-30
-45
-60
-75
Phase
-90
-105
-120
-135
-150
Gain
-165
-180
-195
-210
10k 100k 1M 10M 100M
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Supply Voltage (V)
FIGURE 2-15:
Output Short-Circuit Current
vs. Supply Voltage.
0
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-14:
Supply Voltage.
Input Bias, Offset Currents
Open-Loop Phase (°)
FIGURE 2-13:
Input Bias, Offset Currents
vs. Common Mode Input Voltage.
Quiescent Current
(mA/amplifier)
Input Bias, Offset Currents (pA)
10,000
Quiescent Current
(mA/amplifier)
Input Bias, Offset Currents (pA)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
FIGURE 2-18:
Frequency.
Open-Loop Gain, Phase vs.
DS21685B-page 7
MCP6021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
120
VDD = 5.5V
DC Open-Loop Gain (dB)
120
110
VDD = 2.5V
100
90
115
VDD = 5.5V
110
105
VDD = 2.5V
100
95
90
1.E+02
1.E+03
1.E+04
1k
10k
1.E+05
-50
100k
-25
Load Resistance (:)
DC Open-Loop Gain vs.
FIGURE 2-22:
Temperature.
VCM = VDD/2
110
VDD = 5.5V
100
90
VDD = 2.5V
80
70
0.00
0.05
0.10
0.15
0.20
0.25
50
75
100
-50
-25
0
25
50
75
75
8
60
Phase Margin, G = +1
6
4
45
30
2
15
VDD = 5.0V
0
FIGURE 2-23:
Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-21:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
Gain Bandwidth Product
(MHz)
14
Ambient Temperature (°C)
DS21685B-page 8
10
90
Common Mode Input Voltage (V)
Phase Margin, G = +1 (°)
GBWP, VDD = 5.5V
GBWP, VDD = 2.5V
PM,
VDD = 2.5V
PM,
VDD = 5.5V
100
90
80
70
60
50
40
30
20
10
0
100 125
105
Gain Bandwidth Product
12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FIGURE 2-20:
Small Signal DC Open-Loop
Gain vs. Output Voltage Headroom.
10
9
8
7
6
5
4
3
2
1
0
125
DC Open-Loop Gain vs.
0
0.30
Output Voltage Headroom (V);
VDD - VOH or VOL - VSS
Gain Bandwidth Product
(MHz)
25
14
120
Gain Bandwidth Product
(MHz)
DC Open-Loop Gain (dB)
FIGURE 2-19:
Load Resistance.
0
Ambient Temperature (°C)
Phase Margin, G = +1 (°)
80
100
12
105
Gain Bandwidth Product
10
75
8
Phase Margin, G = +1
6
60
45
4
2
90
30
VDD = 5.0V
VCM = VDD/2
15
0
Phase Margin, G = +1 (°)
DC Open-Loop Gain (dB)
130
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
FIGURE 2-24:
Gain Bandwidth Product,
Phase Margin vs. Output Voltage.
 2003 Microchip Technology Inc.
MCP6021/2/3/4
11
10
9
8
7
6
5
4
3
2
1
0
10
Falling, VDD = 5.5V
Rising, VDD = 5.5V
Maximum Output Voltage
Swing (VP-P)
Slew Rate (V/µs)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
Falling, VDD = 2.5V
Rising, VDD = 2.5V
VDD = 5.5V
VDD = 2.5V
1
0.1
10k
1.E+04
-50
-25
0
25
50
75
100
125
1.E+05
Ambient Temperature (°C)
FIGURE 2-25:
Slew Rate vs. Temperature.
0.1000%
f = 1 kHz
BWMeas = 22 kHz
VDD = 5.0V
G = +100 V/V
G = +100 V/V
0.0100%
1.E+07
10M
FIGURE 2-28:
Maximum Output Voltage
Swing vs. Frequency.
THD+N (%)
THD+N (%)
0.1000%
1.E+06
100k
1M
Frequency (Hz)
G = +10 V/V
0.0010%
0.0100%
G = +10 V/V
0.0010%
G = +1 V/V
f = 20 kHz
BWMeas = 80 kHz
VDD = 5.0V
G = +1 V/V
0.0001%
0.0001%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FIGURE 2-26:
Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz.
FIGURE 2-29:
Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 20 kHz.
Channel to Channel Separation
(dB)
6
Input, Output Voltage (V)
VIN
VDD = 5V
G = +1 V/V
5
VOUT
4
3
2
1
0
-1
0.0E+00
1.0E-05
2.0E-05
3.0E-05
4.0E-05
5.0E-05
6.0E-05
7.0E-05
8.0E-05
9.0E-05
1.0E-04
Time (10 µs/div)
FIGURE 2-27:
The MCP6021/2/3/4 family
shows no phase reversal under overdrive.
 2003 Microchip Technology Inc.
Output Voltage (VP-P)
135
130
125
120
115
110
G = +1 V/V
105
1.E+03
1k
1.E+04
1.E+05
10k
100k
Frequency (Hz)
1.E+06
1M
FIGURE 2-30:
Channel-to-Channel
Separation vs. Frequency (MCP6022 and
MCP6024 only).
DS21685B-page 9
MCP6021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
Output Voltage Headroom
VDD-VOH or VOL-VSS (mV)
Output Voltage Headroom;
VDD-VOH or VOL-VSS (mV)
1,000
100
VOL - VSS
10
VDD - VOH
1
0.01
0.1
1
10
9
8
7
6
5
4
3
2
1
0
10
VOL - VSS
VDD - VOH
-50
-25
Output Current Magnitude (mA)
FIGURE 2-31:
Output Voltage Headroom
vs. Output Current.
FIGURE 2-34:
vs. Temperature.
6.E-02
50
75
100
125
Output Voltage Headroom
G = -1 V/V
RF = 1 k:
5.E-02
Output Voltage (10 mV/div)
Output Voltage (10 mV/div)
25
6.E-02
G = +1 V/V
5.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
-5.E-02
-5.E-02
-6.E-02
-6.E-02
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
0.E+00
2.E-06
2.E-07
4.E-07
6.E-07
FIGURE 2-32:
Pulse Response.
Small-Signal Non-inverting
FIGURE 2-35:
Response.
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
Small-Signal Inverting Pulse
5.0
5.0
G = +1 V/V
4.5
G = -1 V/V
RF = 1 k:
4.5
Output Voltage (V)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0.0
8.E-07
Time (200 ns/div)
Time (200 ns/div)
Output Voltage (V)
0
Ambient Temperature (°C)
0.E+00
5.E-07
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
0.0
0.E+00
5.E-07
FIGURE 2-33:
Pulse Response.
DS21685B-page 10
Large-Signal Non-inverting
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-36:
Response.
Large-Signal Inverting Pulse
 2003 Microchip Technology Inc.
MCP6021/2/3/4
50
40
30
20
10
0
-10
-20
-30
-40
-50
VREF Accuracy; VREF-VDD/2 (mV)
VREF Accuracy; VREF-VDD/2 (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 kΩ to V DD/2,
VOUT ≈ VDD/2 and C L = 60 pF.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
50
40
30
20
10
0
-10
-20
-30
-40
-50
Representative Part
VDD = 5.5V
VDD = 2.5V
-50
FIGURE 2-37:
VREF Accuracy vs. Supply
Voltage (MCP6021 and MCP6023 only).
25
50
75
100
125
FIGURE 2-40:
VREF Accuracy vs.
Temperature (MCP6021 and MCP6023 only).
Op Amp
shuts off here
1.4
Quiescent Current
(mA/amplifier)
Op Amp
turns on here
1.4
Quiescent Current
(mA/amplifier)
0
1.6
1.6
1.2
1.0
Hysteresis
CS swept
high to low
0.8
0.6
VDD = 2.5V
G = +1 V/V
VIN = 1.25V
0.4
0.2
CS swept
low to high
Op Amp
turns on here
Op Amp
shuts off here
1.2
Hysteresis
1.0
0.8
CS swept
high to low
0.6
0.4
0.2
VDD = 5.5V
G = +1 V/V
VIN = 2.75V
CS swept
low to high
0.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
FIGURE 2-38:
Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Chip Select Voltage (V)
Chip Select Voltage,
Output Voltage (V)
-25
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-41:
Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 5.5V.
VDD = 5.0V
G = +1 V/V
VIN = VSS
CS Voltage
VOUT
Output
on
0.0E+00
5.0E-06
Output
on
Output High-Z
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
3.5E-05
Time (5 µs/div)
FIGURE 2-39:
Chip Select (CS) to
Amplifier Output Response Time (MCP6023
only).
 2003 Microchip Technology Inc.
DS21685B-page 11
MCP6021/2/3/4
3.0
APPLICATIONS INFORMATION
The MCP6021/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity-gain stable and suitable for a
wide range of general-purpose applications.
3.1
Rail-to-Rail Input
The MCP6021/2/3/4 amplifier family is designed to not
exhibit phase inversion when the input pins exceed the
supply voltages. Figure 2-27 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
The input stage of the MCP6021/2/3/4 family of devices
uses two differential input stages in parallel; one
operates at low common-mode input voltage (VCM),
while the other operates at high VCM. With this topology,
the device operates with VCM up to 0.3V past either
supply rail (VSS - 0.3V to VDD + 0.3V) at 25°C. The
amplifier input behaves linearly as long as VCM is kept
within the specified VCMR limits. The input offset voltage
is measured at both VCM = VSS - 0.3V and VDD + 0.3V
to ensure proper operation.
3.3
MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS). When CS is high, the supply current is less than
10 nA (typ) and travels from the CS pin to VSS, with the
amplifier output being put into a high-impedance state.
When CS is low, the amplifier is enabled. If CS is left
floating, the amplifier will not operate properly.
Figure 1-1 and Figure 2-39 show the output voltage
and supply current response to a CS pulse.
3.4
MCP6021 and MCP6023 Reference
Voltage
The single op amps (MCP6021 and MCP6023) have
an internal mid-supply reference voltage connected to
the VREF pin (see Figure 3-2). The MCP6021 has CS
internally tied to VSS, which always keeps the op amp
on and always provides a mid-supply reference. With
the MCP6023, taking the CS pin high conserves power
by shutting down both the op amp and the V REF
circuitry. Taking the CS pin low turns on the op amp and
VREF circuitry.
VDD
Input voltages that exceed the input voltage range
(VCMR) can cause excessive current to flow in or out of
the input pins. Current beyond ±2 mA introduces
possible reliability problems. Thus, applications that
exceed this rating must externally limit the input current
with an input resistor (RIN), as shown in Figure 3-1.
50 kΩ
VREF
50 kΩ
CS
RIN
MCP602X
VOUT
VIN
(CS tied internally to VSS for MCP6021)
R IN ≥
R IN ≥
(Maximum expected VIN) - VDD
2 mA
VSS - (Minimum expected VIN)
FIGURE 3-1:
into an input pin.
3.2
VSS
2 mA
R IN limits the current flow
FIGURE 3-2:
Simplified internal VREF
circuit (MCP6021 and MCP6023 only).
See Figure 3-3 for a non-inverting gain circuit using the
internal mid-supply reference. The DC-blocking
capacitor (CB) also reduces noise by coupling the op
amp input to the source.
Rail-to-Rail Output
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load.
According to the specification table, the output can
reach within 20 mV of either supply rail when
RL = 10 kΩ. See Figure 2-31 and Figure 2-34 for more
information concerning typical performance.
DS21685B-page 12
RG
RF
CB
VREF
VOUT
VIN
FIGURE 3-3:
Non-inverting gain circuit
using VREF (MCP6021 and MCP6023 only).
 2003 Microchip Technology Inc.
MCP6021/2/3/4
To use the internal mid-supply reference for an
inverting gain circuit, connect the V REF pin to the noninverting input, as shown in Figure 3-4. The capacitor
CB helps reduce power supply noise on the output.
Recommended RISO (:)
RG
1,000
RF
VIN
VOUT
GN t +1
100
10
VREF
10
100
1,000
10,000
Normalized Capacitance; CL/GN (pF)
CB
FIGURE 3-6:
Recommended RISO values
for capacitive loads.
FIGURE 3-4:
Inverting gain circuit using
VREF (MCP6021 and MCP6023 only).
If you don’t need the mid-supply reference, leave the
VREF pin open.
3.5
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 3-5) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
VIN
RISO
VOUT
MCP602X
CL
FIGURE 3-5:
Output resistor RISO
stabilizes large capacitive loads.
Figure 3-6 gives recommended RISO values for
different capacitive laods and gains. The x-axis is the
normalized load capacitance (C L/G N), where G N is the
circuit’s noise gain. For non-inverting gains, G N and the
gain are equal. For inverting gains, G N is 1+|Gain| (e.g.,
-1 V/V gives GN = +2 V/V).
After selecting R ISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6021/2/3/4 Spice macro
model are very helpful. Modify RISO’s value until the
response is reasonable.
3.6
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other parts.
3.7
PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6021/2/3/4 family’s bias current at 25°C (1 pA,
typ).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 3-7.
Guard Ring
FIGURE 3-7:
 2003 Microchip Technology Inc.
VIN– VIN+
Example guard ring layout.
DS21685B-page 13
MCP6021/2/3/4
1.
Inverting (Figure 3-7) and Transimpedance
Gain Amplifiers (convert current to voltage, such
as photo detectors).
a.
b.
2.
3.8
Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp’s input (e.g., VDD/2 or ground).
Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
3.9
Typical Applications
3.9.1
A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
Figure 3-8 shows a third-order Butterworth filter that
can be used as an A/D converter driver. It has a bandwidth of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 dB attenuation at 60 kHz).
Non-inverting Gain and Unity-Gain Buffer
a.
Connect the guard ring to the inverting input
pin (VIN–); this biases the guard ring to the
common mode input voltage.
b.
Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
High-Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a
significant difference in the performance of these op
amps. Good PC board layout techniques will help you
achieve the performance shown in the Electrical
Characteristics and Typical Performance Curves, while
also helping you minimize EMC (Electro-Magnetic
Compatibility) issues.
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low-speed from highspeed and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separating
them from interfering components and traces. This is
especially important for high-frequency (low rise-time)
signals.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect the guard
trace to ground plane at both ends, and in the middle
for long traces.
Use coax cables (or low inductance wiring) to route
signal and power to and from the PCB.
DS21685B-page 14
1.0 nF
8.45 kΩ 14.7 kΩ
33.2 kΩ
1.2 nF
100 pF
MCP602X
FIGURE 3-8:
A/D converter driver and
anti-aliasing filter with a 20 kHz cutoff frequency.
This filter can easily be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
3.9.2
OPTICAL DETECTOR AMPLIFIER
Figure 3-9 shows the MCP6021 op amp used as a
transimpedance amplifier in a photo detector circuit.
The photo detector looks like a capacitive current
source, so the 100 kΩ resistor gains the input signal to
a reasonable level. The 5.6 pF capacitor stabilizes this
circuit and produces a flat frequency response with a
bandwidth of 370 kHz.
5.6 pF
Photo
Detector
100 kΩ
100 pF
MCP6021
VDD/2
FIGURE 3-9:
Transimpedance amplifier
for an optical detector.
 2003 Microchip Technology Inc.
MCP6021/2/3/4
4.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6021/2/3/4 family of op amps.
4.1
SPICE Macro Model
The latest SPICE macro model for the MCP6021/2/3/4
op amps is available on our web site
(www.microchip.com). This model is intended as an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specs and plots.
4.2
FilterLab® Software
The FilterLab® software is an innovative tool that
simplifies analog active filter (using op amps) design.
Available at no cost from our web site (at www.microchip.com), the FilterLab software active filter design
tool provides full schematic diagrams of the filter circuit
with component values. It also outputs the filter circuit
in SPICE format, which can be used with the Macro
Model to simulate actual filter performance.
 2003 Microchip Technology Inc.
DS21685B-page 15
MCP6021/2/3/4
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
YYWW
MCP6021
I/P256
0331
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
MCP6021
I/SN0331
NNN
256
Example:
8-Lead TSSOP
XXXX
6021
YWW
E331
NNN
256
Legend: XX...X
Y
YY
WW
NNN
Note:
*
Example:
Customer specific information*
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard device marking consists of Microchip part number, year code, week code, and traceability
code.
DS21685B-page 16
 2003 Microchip Technology Inc.
MCP6021/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6024)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC (150 mil) (MCP6024)
Example:
MCP6024-I/P
XXXXXXXXXXXXXX
0331256
Example:
MCP6024ISL
XXXXXXXXXX
0331256
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6024)
Example:
XXXXXX
YYWW
6024E
0331
NNN
256
 2003 Microchip Technology Inc.
DS21685B-page 17
MCP6021/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21685B-page 18
 2003 Microchip Technology Inc.
MCP6021/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
 2003 Microchip Technology Inc.
DS21685B-page 19
MCP6021/2/3/4
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
INCHES
NOM
MAX
8
.026
.033
.002
.246
.169
.114
.020
0
.004
.007
0
0
.035
.004
.251
.173
.118
.024
4
.006
.010
5
5
.043
.037
.006
.256
.177
.122
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
8
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
2.90
3.00
3.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
DS21685B-page 20
 2003 Microchip Technology Inc.
MCP6021/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
eB
B1
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
 2003 Microchip Technology Inc.
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
DS21685B-page 21
MCP6021/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21685B-page 22
 2003 Microchip Technology Inc.
MCP6021/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
 2003 Microchip Technology Inc.
DS21685B-page 23
MCP6021/2/3/4
NOTES:
DS21685B-page 24
 2003 Microchip Technology Inc.
MCP6021/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
c)
Device:
MCP6021
MCP6021T
MCP6022
MCP6022T
MCP6023
MCP6023T
MCP6024
MCP6024T
CMOS Single Op Amp
CMOS Single Op Amp
(Tape and Reel for SOIC, TSSOP)
CMOS Dual Op Amp
CMOS Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
CMOS Single Op Amp w/ CS Function
CMOS Single Op Amp w/ CS Function
(Tape and Reel for SOIC and TSSOP)
CMOS Quad Op Amp
CMOS Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature Range:
I
E
= -40°C to +85°C
= -40×C to +125×C
Package:
P
SN
SL
ST
=
=
=
=
a)
b)
c)
a)
b)
c)
a)
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP, 8-lead, 14-lead
b)
c)
MCP6021-I/P:
Industrial temperature,
PDIP package.
MCP6021-E/P:
Extended temperature,
PDIP package.
MCP6021-E/SN: Extended temperature,
SOIC package.
MCP6022-I/P:
Industrial temperature,
PDIP package.
MCP6022-E/P:
Extended temperature,
PDIP package.
MCP6022T-E/ST: Tape and Reel,
Extended temperature,
TSSOP package.
MCP6023-I/P:
Industrial temperature,
PDIP package.
MCP6023-E/P:
Extended temperature,
PDIP package.
MCP6023-E/SN: Extended temperature,
SOIC package.
MCP6024-I/SL:
Industrial temperature,
SOIC package.
MCP6024-E/SL: Extended temperature,
SOIC package.
MCP6024T-E/ST: Tape and Reel,
Extended temperature,
TSSOP package.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2003 Microchip Technology Inc.
DS21685B-page 25
MCP6021/2/3/4
NOTES:
DS21685B-page 26
 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
 2003 Microchip Technology Inc.
DS21685B-page 27
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Suite 22, 41 Rawson Street
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Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
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Tel: 770-640-0034
Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
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Tel: 978-692-3848
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Chicago
333 Pierce Road, Suite 180
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Tel: 630-285-0071
Fax: 630-285-0075
Dallas
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Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
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Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
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Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
China - Beijing
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
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Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
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China - Shenzhen
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Irvine, CA 92612
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Fax: 949-263-1338
Rm. 1812, 18/F, Building A, United Plaza
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Tel: 86-755-82901380
Fax: 86-755-8295-1393
Phoenix
China - Shunde
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Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
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Tel: 86-765-8395507 Fax: 86-765-8395571
San Jose
China - Qingdao
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Toronto
India
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
Divyasree Chambers
1 Floor, Wing A (A3/A4)
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Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
DS21685B-page 28
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
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Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
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Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
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91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
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Tel: 49-89-627-144-0
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Italy
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Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
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Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
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Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
 2003 Microchip Technology Inc.