LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 LM10524 Triple Buck Power Management Unit Check for Samples: LM10524 FEATURES DESCRIPTION • LM10524 is an advanced PMU containing three configurable, high-efficiency buck regulators for supplying variable voltages. The device is ideal for supporting ASIC and SOC designs for SSD and Flash drives. 1 2 • • • • • • • Three Highly Efficient Programmable Buck Regulators – Integrated FETs with Low RDSON – Bucks Operate with Their Phases Shifted to Reduce the Input Current Ripple and Capacitor Size – Programmable Output Voltage via the SPI Interface – Over and Under-Voltage-Lockout – Automatic Internal Soft Start with PowerOn-Reset – Current Overload and Thermal Shutdown Protection – PFM Mode for High Efficiency at Light Load Conditions Power-Down Data Protection Enhances Data Integrity Bypass Mode Available on Buck 1 Sleep Mode to Save Power During Idle Times – DEVSLP Function SPI-Programmable Interrupt Comparator (2.0V to 4.0V) Factory Programmable Startup Sequencing for Varied Controllers Fast Startup for all Voltage Rails in about 3.5ms to PWR_OK Fast Turn-off / Active Discharge on Regulator Outputs The LM10524 can operate cooperatively with an ASIC to optimize the supply voltage for low-power conditions and to control power saving modes via the SPI interface. KEY SPECIFICATIONS • • • • • • Single input rail with wide range: 3.3 to 5.5V Programmable Buck Regulator Outputs: – Buck 1: 1.1V to 3.6V; 1.6A – Buck 2: 1.1V to 3.6V; 1A – Buck 3: 0.7V to 1.95V; 2.5A ±3% feedback voltage accuracy Up to 95% efficient buck regulators 2MHz switching frequency for smaller inductor size 2.815mm, 3.215mm, 0.4mm pitch, 46 bump micro SMD package APPLICATION • Solid-State Drives 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Typical Application Diagram LM10524 DEVSLP_OVR1 DEVSLP_OVR2 IO Input Supply Power Supply 3.3 / 5.5V CONTROL LOGIC and REGISTERS C8 2.2uF VIN VIN_B1 C5 4.7uF VIN_B2 C6 4.7uF IRQ SW_B1 BUCK1 2.2uH 1.1 to 3.6V, 1.6A C1 47uF L2 SW_B2 BUCK2 2.2uH 1.1 to 3.6V, 1.0A C2 47uF FB_B2 L3 SW_B3 1.0uH Host 1 Flash Vcc 2.85V Host 2 Domain Vccq 1.8V 0.7 to 1.95V, 2.5A C3 47uF Host 3 Domain Vcore 1.0V GND VIN_B3 GND L1 FB_B1 BUCK3 GND System Control Vcomp COMP FB_B3 C7 4.7uF ASIC / SoC SPI_CS SPI_DI SPI SPI_DO SPI_CLK VIN_IO C4 2.2uF SLEEP_EN DEVSLP_ CTRL POWERUP_MODE DEVSLP PWR_OK 2 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Overview The LM10524 contains three buck converters. Supply Specification below lists the output characteristics of the power regulators. Supply Specification (1) Regulator Default VOUT at Start-Up VOUT if DEVSLP=High (DEVSLP mode) Output Voltage Range Max Output Current BUCK1 (1) 2.85 V OFF 1.1V to 3.6V; 50 mV steps 1.6A BUCK2 (1) 1.8 V OFF 1.1V to 3.6V; 50 mV steps 1.0A BUCK3 (1) 1.0V OFF 0.7V to 1.95V; 10mV steps 2.5A Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode.. 3 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Connection Diagram And Package Marking TOP VIEW LOOKING THROUGH THE PACKAGE 1 2 3 4 5 6 7 A VIN_IO PWR_OK VIN DEVSLP VIN_B1 SW_B1 GND_B1 B GND GND VCOMP FB_B1 VIN_B1 SW_B1 GND_B1 C SPI_ CLK GND IRQ FB_B1 FB_B1 FREE DEVSLP _OVR1 D SPI_DI DEVSLP _OVR2 E SPI_DO DEVSLP _CTRL F SPI_CS SW_B2 FB_B2 FREE FB_B3 SW_B3 SLEEP _EN G GND_B2 SW_B2 VIN_B2 FREE VIN_B3 SW_B3 GND_B3 H GND_B2 SW_B2 VIN_B2 POWER UP_MODE VIN_B3 SW_B3 GND_B3 Figure 1. 46 Bump Micro SMD with 0.4mm Pitch 4 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Table 1. 9.0 LM10524 Pin Description (1) Pin # Pin Name I/O A4 DEVSLP I D E7 DEVSLP_CTRL O D Indicates DevSLP signal is active but drives low when device is in SLEEP mode. C7 DEVSLP_OVR1 I D Used to gate activation of device sleep. D7 DEVSLP_OVR2 I D C5 FB_B1 I/O A Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power. B4 FB_B1 I/O A Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power. C4 FB_B1 I/O A Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power. F3 FB_B2 I A Buck Switcher Regulator 2 - Voltage output feedback. F5 FB_B3 I A Buck Switcher Regulator 3 - Voltage output feedback. C6 FREE Not Used. F4 FREE Not Used. G4 FREE Not Used. B1 GND G G Ground. Connect to system Ground. B2 GND G G Ground. Connect to system Ground. C2 GND G G Ground. Connect to system Ground. A7 GND_B1 G P Buck Switcher Regulator 1 - Power ground for Buck Regulator. (1) (2) Type (2) Functional Description Digital Input Control Signal for entering Device Sleep Mode. Input activates the device sleep function in conjunction with DEVSLP_OVR1, DEVSLP_OVR2, and PowerUp_mode. This is an active High pin with an option for an internal pullup resistor. Turns off all outputs and internal oscillator. Used to gate activation of device sleep. B7 GND_B1 G P Buck Switcher Regulator 1 - Power ground for Buck Regulator. G1 GND_B2 G P Buck Switcher Regulator 2 - Power ground for Buck Regulator. H1 GND_B2 G P Buck Switcher Regulator 2 - Power ground for Buck Regulator. G7 GND_B3 G P Buck Switcher Regulator 3 - Power ground for Buck Regulator. H7 GND_B3 G P Buck Switcher Regulator 3 - Power ground for Buck Regulator. C3 IRQ O D Interrupt. Digital Output of Comparator to signal interrupt condition. A2 PWR_OK O D PWR_OK Signal, Push Pull output. H4 POWERUP _MODE I/O D Used to indicate SSD initialization is complete. Once initialization is complete, this pin should be externally pulled low to allow Sleep mode activation via DEVSLP F7 SLEEP_EN O D Active high output indicates device is in Sleep Mode. C1 SPI_CLK I D SPI Interface - serial clock input. F1 SPI_CS I D SPI Interface - chip select. D1 SPI_DI I D SPI Interface - serial data input. E1 SPI_DO O D SPI Interface - serial data output. A6 SW_B1 I/O P Buck Switcher Regulator 1 - Power Switching node, connect to inductor. B6 SW_B1 I/O P Buck Switcher Regulator 1 - Power Switching node, connect to inductor. F2 SW_B2 I/O P Buck Switcher Regulator 2 - Power Switching node, connect to inductor. G2 SW_B2 I/O P Buck Switcher Regulator 2 - Power Switching node, connect to inductor. H2 SW_B2 I/O P Buck Switcher Regulator 2 - Power Switching node, connect to inductor. F6 SW_B3 I/O P Buck Switcher Regulator 3 - Power Switching node, connect to inductor. G6 SW_B3 I/O P Buck Switcher Regulator 3 - Power Switching node, connect to inductor. H6 SW_B3 I/O P Buck Switcher Regulator 3 - Power Switching node, connect to inductor. B3 VCOMP I A Analog Input for Comparator. A3 VIN I P Power supply Input Voltage — must be present for device to work; decouple closely to D7. A5 VIN_B1 I P Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if Buck 1 is not used, tie to ground to reduce leakage. B5 VIN_B1 I P Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if Buck 1 is not used, tie to ground to reduce leakage. I: Input Pin, O: Output Pin A: Analog Pin, D: Digital Pin, G: Ground, P: Power Connection 5 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Table 1. 9.0 LM10524 Pin Description (continued) (1) Type (2) Functional Description Pin # Pin Name I/O G3 VIN_B2 I P Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET, if Buck 2 is not used, tie to ground to reduce leakage. H3 VIN_B2 I P Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET, if Buck 2 is not used, tie to ground to reduce leakage. G5 VIN_B3 I P Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET. H5 VIN_B3 I P Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET.. A1 VIN_IO I A Supply Voltage for Digital Interface. Table 2. Device Information Part Number Buck 1 Bypass FPWM Default Package Type Product Identification LM10524TME Disabled All Bucks micro SMD V088 Supplied as 250 Tape & Reel LM10524TMX LM10524TME-A 1000 Tape & Reel Disabled Bucks 2 + 3 micro SMD V089 250 Tape & Reel LM10524TMX-A 1000 Tape & Reel These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Pins Min Max Units VIN, VCOMP -0.3 6 V VIN_IO, VIN_B1, VIN_B2, VIN_B3, SPI_CS, SPI_DI, SPI_CLK, SPI_DO, DEVSLP, DEVSLP_CTRL, SLEEP_EN, POWERUP MODE, SW_1, SW_2, SW_3, FB_1, FB_2, FB_3, PWR_OK, IRQ, DEVSLP_OVR1, DEVSLP_OVR2 -0.3 VVIN Junction Temperature, TJ-MAX 150 Storage Temperature -65 ESD Rating, HBM – Human Body Model (1) (2) °C 150 1 kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Operating Ratings (1) (2) (3) Pins Min Max Units 3 5.5 V 1.72 VVIN 0 VVIN Junction Temperature, TJ -30 125 Ambient Temperature, TA -30 85 VIN_B1, VIN_B2, VIN_B3, VIN VIN_IO All other Input Pins °C Junction-to-Ambient Thermal resistance, θJA 40 °C/W Maximum Continuous Power Dissipation, PDMAX 1 W (1) (2) (3) Internal thermal shutdown protects device from permanent damage. Thermal shutdown engages at TJ = +140°C and disengages at TJ = +120°C (typ.). Thermal shutdown is ensured by design. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junvction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics). 6 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 General Electrical Characteristics (1) (2) Unless otherwise noted, VVIN = 5.0V where: VVIN=VVIN_B1 = VVIN_B2 = VVIN_B3. VVIN_I0 = 3.0V. The application circuit used is the one shown in “Typical Application Circuit". Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range of -30°C ≤ TA=TJ ≤ +85°C. Symbol Parameter Conditions Min IQ(DEVSLP) Quiescent supply current. DevSLP=High No load. Typ Max Units 50 200 µA V UNDER/OVER VOLTAGE LOCK OUT VUVLO_RISING 2.7 2.9 3.135 VUVLO_FALLING 2.45 2.6 2.75 VOVLO_RISING 6.05 VOVLO_FALLING 5.75 DIGITAL INTERFACE VIL Logic Input Low VIH Logic Input High VIL Logic Input Low VIH Logic Input High VIL Logic Input Low VIH Logic Input High VOL Logic output Low VOH Logic output High IIL Input Current, pin driven low SPI_CS, SPI_DI, SPI_CLK -2 DEVSLP -5 IIH Input Current, pin driven high SPI_CS, SPI_DI, SPI_CLK,DEVSLP fSPI_MAX SPI max frequency (1) (2) (3) SPI_CS, SPI_DI, SPI_CLK, POWERUP_MODE (3) 0.3*VVIN_IO V 0.7*VVIN_IO DEVSLP_OVR1, DEVSLP_OVR2 0.3*VVIN (3) 0.7*VVIN DEVSLP (3) 0.3V 1.2V IRQ (at 2mA load), SPI_DO, DEVSLP_CTRL (3), SLEEP_EN (3),PWR_OK 0.2*VVIN_IO 0.8*VVIN_IO µA 2 10 MHz All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. Specification ensured by design. Not tested during production. 7 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Buck 1 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VVIN = 5.0V where: VVIN=VVIN_B1 = VVIN_B2 = VVIN_B3. The application circuit used is the one shown in “Typical Application Circuit". Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range of -30°C ≤ TA=TJ ≤ +85°C. Symbol Parameter Conditions Min IQ DC Bias Current in VIN No Load, PFM Mode IOUT-MAX Continuous maximum load current (4) (5) (6) Buck 1 enabled, switching in PWM 1.6 IPEAK Peak switching current limit Buck 1 enabled, switching in PWM 1.9 η Efficiency peak, Buck 1 (4) IOUT = 0.3 A, VVIN = 3.3V FSW Switching Frequency CIN Input Capacitor (4) COUT Output Filter Capacitor (4) Typ Max Units 15 50 µA A 2.2 1.75 0mA ≤ IOUT ≤ IOUT-MAX 2 47 ∆VOUT MHz µF 100 20 Output Filter Inductance (4) (4) % 2.3 4.7 22 Output Capacitor ESR (4) L 2.8 90 mΩ 2.2 µH 3.3V ≤ VVIN ≤ 5V, IOUT = IOUT-MAX 0.5 %/V DC Load regulation, PWM (4) VVIN=3.3V, 0.1 * IOUT-MAX ≤ IOUT ≤ IOUT-MAX 0.3 %/A IFB Feedback pin input bias current VFB = 2.85V 2.3 VFB Feedback Accuracy VFB = 2.85V RDS-ON-HS High Side Switch On Resistance RDS-ON-LS Low Side Switch On Resistance RDS-ON-BYPASS Bypass FET on resistance DC Line regulation -3 5 3 115 VVIN = 2.6V µA % mΩ 190 60 110 Used in parallel with the high side FET while in Bypass mode. Resistance (DCR) of inductor = 100 mΩ VIN = 3.1V 75 VIN = 2.6V 120 mΩ Startup Tstart_NoLoad Internal soft-start (turn on time) (4) Start up from shutdown, VOUT=0V, no load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.1 Tstart_FullLoad Internal soft-start (turn on time) (4) Start up from shutdown, VOUT =0V, Maximum Load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.5 (1) (2) (3) (4) (5) (6) ms All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. BUCK normal operation is ensured if VIN ≥ VOUT+1.0V. Specification ensured by design. Not tested during production. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) 8 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Buck 2 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VVIN = 5.0V where: VVIN=VVIN_B1 = VVIN_B2 = VVIN_B3. The application circuit used is the one shown in “Typical Application Circuit". Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range of -30°C ≤ TA=TJ ≤ +85°C. Symbol Parameter Conditions Min IQ DC Bias Current in VIN No Load, PFM Mode IOUT-MAX Continuous maximum load current (4) (5) (6) Buck 2 enabled, switching in PWM 1 IPEAK Peak switching current limit Buck 2 enabled, switching in PWM 1.35 η Efficiency peak, Buck2 (4) IOUT = 0.3 A, VVIN = 3.3V FSW Switching Frequency CIN Input Capacitor (4) COUT Output Filter Capacitor (4) Typ Max Units 15 50 µA A 1.55 1.75 0mA ≤ IOUT ≤ IOUT-MAX 2 47 ∆VOUT µF µH %/V 3.3V ≤ VVIN ≤ 5V, IOUT = IOUT-MAX 0.5 V VIN=3.3V, 100mA ≤ IOUT ≤ IOUT-MAX 0.3 IFB Feedback pin input bias current VFB = 1.8V 2.3 VFB Feedback Accuracy VFB = 1.8V RDS-ON-HS High Side Switch On Resistance RDS-ON-LS Low Side Switch On Resistance -3 %/A 5 3 125 VVIN = 2.6V mΩ 2.2 DC Load regulation, PWM (4) DC Line regulation MHz 100 20 Output Filter Inductance (4) (4) % 2.3 4.7 22 Output Capacitor ESR (4) L 1.90 90 µA % mΩ 200 60 110 Startup Tstart_NoLoad Internal soft-start (turn on time) (4) Start up from shutdown, VOUT=0V, no load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.1 Tstart_FullLoad Internal soft-start (turn on time) (4) Start up from shutdown, VOUT =0V, Maximum Load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.5 (1) (2) (3) (4) (5) (6) ms All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. BUCK normal operation is ensured if VIN ≥ VOUT+1.0V. Specification ensured by design. Not tested during production. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) 9 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Buck 3 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VVIN = 5.0V where: VVIN=VVIN_B1 = VVIN_B2 = VVIN_B3. The application circuit used is the one shown in “Typical Application Circuit". Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range of -30°C ≤ TA=TJ ≤ +85°C. Symbol Parameter Conditions Min IQ DC Bias Current in VIN No Load, PFM Mode IOUT-MAX Continuous Peak load current (4) (5) (6) Buck 3 enabled, switching in PWM 2.5 IPEAK Peak switching current limit Buck 3 enabled, switching in PWM 2.9 η Efficiency peak, Buck3 (4) IOUT = 0.3 A, VVIN = 3.3V FSW Switching Frequency CIN Input Capacitor (4) COUT Output Filter Capacitor (4) Typ Max Units 15 50 µA A 3.5 90 1.75 0mA ≤ IOUT ≤ IOUT-MAX 2 4.7 47 47 Output Capacitor ESR (4) ∆VOUT (4) %/V 0.5 VIN=5V, 100mA ≤ IOUT ≤ IOUT-MAX 0.3 IFB Feedback pin input bias current VFB = 1.0V 3.0 VFB Feedback Accuracy VFB = 1.0V RDS-ON-HS High Side Switch On Resistance -3 %/A 5 3 95 VVIN = 2.6V Low Side Switch On Resistance mΩ µH 3.3V ≤ VVIN ≤ 5V, IOUT = IOUT-MAX RDS-ON-LS µF 1 DC Load regulation, PWM (4) DC Line regulation MHz 100 20 Output Filter Inductance (4) L % 2.3 µA % mΩ 140 45 90 Startup Tstart_NoLoad Internal soft-start (turn on time) (4) Start up from shutdown, VOUT=0V, no load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.1 Tstart_FullLoad Internal soft-start (turn on time) (4) Start up from shutdown, VOUT=0V, Maximum Load, LC = recommended circuit, using software enable, to VOUT = 95% of final value 0.5 (1) (2) (3) (4) (5) (6) ms All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. BUCK normal operation is ensured if VIN ≥ VOUT+1.0V. Specification ensured by design. Not tested during production. In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.) 10 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Comparators Electrical Characteristics (1) (2) Unless otherwise noted, VVIN = 5.0V where: VVIN=VVIN_B1 = VVIN_B2 = VVIN_B3. The application circuit used is the one shown in “Typical Application Circuit". Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range of -30°C ≤ TA=TJ ≤ +85°C. Symbol Parameter Conditions IVCOMP VCOMP pin bias current Min Typ Max Units VCOMP = 0.0V 0.1 2 µA VCOMP = 5.0V 0.1 2 VCOMP_RISE Comparator rising edge trigger level 2.79 VCOMP_FALL Comparator falling edge trigger level 2.73 Hysteresis tCOMP_IRQ (1) (2) 30 Transition time of Interrupt output V 60 80 mV 6 15 µs All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. 11 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Typical Performance Characteristics (All plots are representative typical plots) Vin=5.0V Buck 2 Efficiency 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Buck 1 Efficiency 100 60 50 40 30 60 50 40 30 VIN=3.7V VIN=4.2V VIN=5.0V 20 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 0 1.6 Load Current (A) VIN=3.3V VIN=4.2V VIN=5.0V 20 0.0 0.1 0.2 0.3 Figure 2. Buck 3 Efficiency 90 3.5 Output Voltage (V) 80 Efficiency (%) 70 60 50 40 30 3.0 Output Voltage (V) 5 0.9 1.0 C005 Buck 1 Buck 2 Buck 3 POK 2.0 1.5 0.5 0.0 Time (2ms/DIV) C006 C001 Figure 4. Figure 5. POK at DEVSLP DEVSLP Timing 5ms Buck 1 Buck 2 Buck 3 POK Voltage (1V/DIV) 6 0.8 2.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 Load Current (A) 0.7 1.0 VIN=3.3V VIN=4.2V VIN=5.0V 0 0.6 Startup 4.0 10 0.5 Figure 3. 100 20 0.4 Load Current (A) C004 4 3 2 Buck 3 Buck 2 SLPEN DEVSLP 1 0 Time (2ms/DIV) Time (5ms/DIV) C003 C002 Figure 6. Figure 7. 12 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Typical Performance Characteristics (continued) Voltage (1V/DIV) DEVSLP Timing 10ms Buck 1 - 0 to 750mA Buck 3 Buck 2 SLPEN DEVSLP Time (5ms/DIV) C004 Figure 8. Figure 9. Buck 1 - 750mA to 1.6A Buck 2 - 0 to 500mA Figure 10. Figure 11. Buck 2 - 500 to 1A Buck 3 - 0 to 1.25A Figure 12. Figure 13. 13 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Typical Performance Characteristics (continued) Buck 3 - 1.25 to 2.5A Figure 14. 14 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 APPLICATION INFORMATION LM10524 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and processors. It operates cooperatively and communicates with processors over an SPI interface with output Voltage programmability. The device incorporates three high-efficiency synchronous buck regulators that deliver three output voltages from a single power source. GND GND GND SPI_CLK SPI_DI SPI_DO SPI_CS VIN_IO The device also includes a SPI programmable Comparator Block that provides an interrupt output signal. The device has a separate logic supply input. SPI VIN_B2 PowerUp_Mode DEVSLP SW_B2 CONTROL LOGIC BUCK 2 REGISTERS DEVSLP_CTRL DEVSLP_OVR1 GND_B2 FB_B2 DEVSLP_OVR2 EN PWR_OK SLEEP_EN LM10524 VIN_B1 BUCK 1 GND_B1 EN SEQUENCER SW_B1 TSD OVLO UVLO EN FB_B1 VIN_B3 SW_B3 VCOMP BUCK 3 COMPARATOR GND_B3 FB_B3 IRQ Figure 15. Internal Block Diagram of the LM10524 PMIC SPI Data Interface The device is programmable via 4-wire SPI Interface. The signals associated with this interface are CS, DI, DO and CLK. Through this interface, the user can enable/disable the device, program the output voltages of the individual Bucks and of course read the status of Flag registers. By accessing the registers in the device through this interface, the user can get access and control the operation of the buck controllers and program the reference voltage of the comparator in the device. 15 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Figure 16. SPI Interface Write • Data In (DI) – 1 to 0 Write Command – A4to A0 Register address to be written – D7 to D0 Data to be written • Data Out (DO) – All Os Figure 17. SPI Interface Read • Data In (DI) – 1 to 1 Read Command – A4to A0 Register address to be read – Don’t care after A0 • Data Out (DO) – D7 to D0 Data Read 16 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Registers Configurable Via The SPI Interface Ad dr 0x0 0 0x0 7 0x0 8 0x0 A 0x0 B Reg Name Buck 3 Voltage Buck 1 Voltage Buck 2 Voltage Buck Control Comparator Control Bit R/W Default Description 7 — - 6 R/W 0 Buck 3 Voltage Code[6] 5 R/W 0 Buck 3 Voltage Code[5] 4 R/W 1 Buck 3 Voltage Code[4] 3 R/W 1 Buck 3 Voltage Code[3] 2 R/W 1 Buck 3 Voltage Code[2] 1 R/W 1 Buck 3 Voltage Code[1] 0 R/W 0 Buck 3 Voltage Code[0] 7 — - Notes Reset default: 0x1E (1.0V) Range: 0.7V to 1.95V Reset default: 6 — - 5 R/W 1 Buck 1 Voltage Code[5] 0x23 (2.85V) 4 R/W 0 Buck 1 Voltage Code[4] 3 R/W 0 Buck 1 Voltage Code[3] 2 R/W 0 Buck 1 Voltage Code[2] 1 R/W 1 Buck 1 Voltage Code[1] 0 R/W 1 Buck 1 Voltage Code[0] 7 — - 6 — - 5 R/W 0 Buck 2 Voltage Code[5] 4 R/W 0 Buck 2 Voltage Code[4] 3 R/W 1 Buck 2 Voltage Code[3] 2 R/W 1 Buck 2 Voltage Code[2] 1 R/W 1 Buck 2 Voltage Code[1] 0 R/W 0 Buck 2 Voltage Code[0] 7 R 1 BK3EN Reads Buck 3 enable status 6 — - 5 — - 4 R/W (see notes) BK1FPWM Buck 1 forced PWM mode when high. Default = 1 (LM10524), Default = 0 (LM10524-A). 3 R/W 1 BK2FPWM Buck 2 forced PWM mode when high 2 R/W 1 BK3FPWM Buck 3 forced PWM mode when high 1 R/W 1 BK1EN Enables Buck 1 0-disabled, 1-enabled 0 R/W 1 BK2EN Enables Buck 2 0-disabled, 1-enabled 7 R/W 0 Comp_hyst[0] Doubles Comparator hysteresis 6 R/W 0 Comp_thres(5) Programmable range of 2.0V to 4.0V, step size = 31.75 mV 5 R/W 1 Comp_thres(4) 4 R/W 1 Comp_thres(3) 3 R/W 0 Comp_thres(2) Comp_hyst=1 → min 80 mV hysteresis 2 R/W 0 Comp_thres(1) Comp_hyst=0 → min 40 mV hysteresis 1 R/W 0 Comp_thres(0) 0 R/W 1 COMPEN Range: 1.1V to 2.85V Reset default: 0x0E (1.8V) Range: 1.1V to 3.6V Comparator Threshold reset default: 6h'18. Comparator enable 17 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Ad dr 0x0 C 0x0 D Reg Name Interrupt Enable Interrupt Status 0x0 MISC Control E www.ti.com Bit R/W Default 7 — 6 — 5 — 4 — 3 R/W 0 Buck 3 OK 2 R/W 0 Buck 2 OK 1 R/W 0 Buck 1 OK 0 R/W 1 Comparator Interrupt comp event 7 — 6 — 5 — 4 R 3 R Buck 3 OK Buck 3 is greater than 90% of target 2 R Buck 2 OK Buck 2 is greater than 90% of target 1 R Buck 1 OK Buck 1 is greater than 90% of target 0 R Comparator Comparator output is high 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 R/W Interrupt Polarity Interrupt_polarity=0→Active low Interrupt Interrupt_polarity=1→Active high Interrupt 0 Description 18 Notes Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 ADDR 0x07& 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping Voltage code Voltage Voltage code Voltage 0x00 1.10 0x20 2.70 0x01 1.15 0x21 2.75 0x02 1.20 0x22 2.80 0x03 1.25 0x23 2.85 0x04 1.30 0x24 2.90 0x05 1.35 0x25 2.95 0x06 1.40 0x26 3.00 0x07 1.45 0x27 3.05 0x08 1.50 0x28 3.10 0x09 1.55 0x29 3.15 0x0A 1.60 0x2A 3.20 0x0B 1.65 0x2B 3.25 0x0C 1.70 0x2C 3.30 0x0D 1.75 0x2D 3.35 0x0E 1.80 0x2E 3.40 0x0F 1.85 0x2F 3.45 0x10 1.90 0x30 3.50 0x11 1.95 0x31 3.55 0x12 2.00 0x32 3.60 0x13 2.05 0x33 3.60 0x14 2.10 0x34 3.60 0x15 2.15 0x35 3.60 0x16 2.20 0x36 3.60 0x17 2.25 0x37 3.60 0x18 2.30 0x38 3.60 0x19 2.35 0x39 3.60 0x1A 2.40 0x3A 3.60 0x1B 2.45 0x3B 3.60 0x1C 2.50 0x3C 3.60 0x1D 2.55 0x3D 3.60 0x1E 2.60 0x3E 3.60 0x1F 2.65 0x3F 3.60 19 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com ADDR 0x00 & 0x09: Buck 3 Voltage Code and VOUT Level Mapping Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage 0x00 0.70 0x20 1.02 0x40 1.34 0x60 1.66 0x01 0.71 0x21 1.03 0x41 1.35 0x61 1.67 0x02 0.72 0x22 1.04 0x42 1.36 0x62 1.68 0x03 0.73 0x23 1.05 0x43 1.37 0x63 1.69 0x04 0.74 0x24 1.06 0x44 1.38 0x64 1.70 0x05 0.75 0x25 1.07 0x45 1.39 0x65 1.71 0x06 0.76 0x26 1.08 0x46 1.40 0x66 1.72 0x07 0.77 0x27 1.09 0x47 1.41 0x67 1.73 0x08 0.78 0x28 1.10 0x48 1.42 0x68 1.74 0x09 0.79 0x29 1.11 0x49 1.43 0x69 1.75 0x0A 0.80 0x2A 1.12 0x4A 1.44 0x6A 1.76 0x0B 0.81 0x2B 1.13 0x4B 1.45 0x6B 1.77 0x0C 0.82 0x2C 1.14 0x4C 1.46 0x6C 1.78 0x0D 0.83 0x2D 1.15 0x4D 1.47 0x6D 1.79 0x0E 0.84 0x2E 1.16 0x4E 1.48 0x6E 1.80 0x0F 0.85 0x2F 1.17 0x4F 1.49 0x6F 1.81 0x10 0.86 0x30 1.18 0x50 1.50 0x70 1.82 0x11 0.87 0x31 1.19 0x51 1.51 0x71 1.83 0x12 0.88 0x32 1.20 0x52 1.52 0x72 1.84 0x13 0.89 0x33 1.21 0x53 1.53 0x73 1.85 0x14 0.90 0x34 1.22 0x54 1.54 0x74 1.86 0x15 0.91 0x35 1.23 0x55 1.55 0x75 1.87 0x16 0.92 0x36 1.24 0x56 1.56 0x76 1.88 0x17 0.93 0x37 1.25 0x57 1.57 0x77 1.89 0x18 0.94 0x38 1.26 0x58 1.58 0x78 1.90 0x19 0.95 0x39 1.27 0x59 1.59 0x79 1.91 0x1A 0.96 0x3A 1.28 0x5A 1.60 0x7A 1.92 0x1B 0.97 0x3B 1.29 0x5B 1.61 0x7B 1.93 0x1C 0.98 0x3C 1.30 0x5C 1.62 0x7C 1.94 0x1D 0.99 0x3D 1.31 0x5D 1.63 0x7D 1.95 0x1E 1.00 0x3E 1.32 0x5E 1.64 0x1F 1.01 0x3F 1.33 0x5F 1.65 20 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 ADDR 0x0B: Comparator Threshold Mapping Voltage code Voltage Voltage code Voltage 6h'00 2.000 6h'20 3.016 6h'01 2.032 6h'21 3.048 6h'02 2.064 6h'22 3.080 6h'03 2.095 6h'23 3.111 6h'04 2.127 6h'24 3.143 6h'05 2.159 6h'25 3.175 6h'06 2.191 6h'26 3.207 6h'07 2.222 6h'27 3.238 6h'08 2.254 6h'28 3.270 6h'09 2.286 6h'29 3.302 6h'0A 2.318 6h'2A 3.334 6h'0B 2.349 6h'2B 3.365 6h'0C 2.381 6h'2C 3.397 6h'0D 2.413 6h'2D 3.429 6h'0E 2.445 6h'2E 3.461 6h'0F 2.476 6h'2F 3.492 6h'10 2.508 6h'30 3.524 6h'11 2.540 6h'31 3.556 6h'12 2.572 6h'32 3.588 6h'13 2.603 6h'33 3.619 6h'14 2.635 6h'34 3.651 6h'15 2.667 6h'35 3.683 6h'16 2.699 6h'36 3.715 6h'17 2.730 6h'37 3.746 6h'18 2.762 6h'38 3.778 6h'19 2.794 6h'39 3.810 6h'1A 2.826 6h'3A 3.842 6h'1B 2.857 6h'3B 3.873 6h'1C 2.889 6h'3C 3.905 6h'1D 2.921 6h'3D 3.937 6h'1E 2.953 6h'3E 3.969 6h'1F 2.984 6h'3F 4.000 Buck Regulators Operation A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground and a feedback path. The figure below shows the block diagram of each of the three buck regulators integrated in the device. G FB CONTROL G CIN P SW D D N S L COUT PGND VOUT S VIN PVIN U1 LM10524 GND Figure 18. Buck Functional Diagram 21 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VVIN_Bx –VOUT)/L by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of (–VOUT)/L. The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. Buck Regulators Description The LM10524 incorporates three high efficiency synchronous switching buck regulators that deliver various voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage regulation, high efficiency and fast transient response time. The bucks feature voltage mode architecture with synchronous rectification. Each of the switching regulators is specially designed for high efficiency operation throughout the load range. With a 2MHz typical switching frequency, the external L-C filter can be small and still provide very low output voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage and high output currents. All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch on. Additional features include soft-start, under-voltage lock-out, and current and thermal overload protection. To reduce the input current ripple, the device employs a control circuit that operates the three bucks at 120° phase. These bucks are nearly identical in performance and mode of operation. They operate in FPWM (forced PWM) or automatic mode (PWM/PFM). PWM Operation During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, a feed forward voltage inversely proportional to the input voltage is introduced. In Forced PWM Mode the bucks always operate in PWM mode regardless of the output current. In Automatic Mode, if the output current is less than 70 mA (typ.), the bucks automatically transition into PFM (Pulse Frequency Modulation) operation to reduce the current consumption. At higher than 100 mA (typ.) they operate in PWM mode. This increases the efficiency at lower output currents. The 30 mA (typ.) hysteresis is designed in for stable Mode transition. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. In this case the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. 22 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 PWM Mode at Moderate to Heavy Loads Vout PFM Mode at Light Load Load current increases, draws Vout towards Low2 PFM Threshold High PFM Threshold ~1.016*Vout Low1 PFM Threshold ~1.008*Vout PFET on until LPFM limit reached NFET on drains inductor current until I inductor=0 High PFM Voltage Threshold reached, go into Idle mode Low PFM Threshold, turn on PFET Load current increases Low2 PFM Threshold, switch back to PWM mode Low2 PFM Threshold Vout Time Figure 19. PFM vs PWM Operation PFM Operation [BUCK 1, 2 & 3] At very light loads, Buck 1, 2 and Buck 3 enter PFM mode and operate with reduced switching frequency and supply current to maintain high efficiency. Buck 1, 2 and 3 will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: 1. The inductor current becomes discontinuous, or 2. The peak PMOS switch current drops below the IMODE level. During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the Ipfm level set for PFM mode. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 19), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘idle’ mode is less than 100uA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. Soft Start Each of the buck converters has an internal soft-start circuit that limits the in-rush current during start-up. This allows the converters to gradually reach the steady state operating point, thus reducing start-up stresses and surges. During start-up, the switch current limit is increased in steps. 23 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com For Buck 1, 2 and 3 the soft start is implemented by increasing the switch current limit in steps that are gradually goes higher. The start-up time depends on the output capacitor size, load current and output voltage. Typical startup time with the recommended output capacitor of 10uF is 0.1-0.5ms. It is expected that in the final application the load current condition will be more likely in the lower load current range during the start up. Current Limiting A current limit feature protects the device and any external components during overload conditions. In PWM mode the current limiting is implemented by using an internal comparator that trips at current levels according to the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. Internal Synchronous Rectification While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. Bypass-FET Operation on Buck 1 This is a factory programmable option, this is disabled on the LM10524 and the LM10524-A. There is an additional bypass FET used on Buck 1. The FET is connected in parallel to High Side FET and inductor. The bypass threshold will be 3.1V with an option of 3.5V (set by OTP). With standard setting if buck 1 input voltage is greater than 3.1V the bypass function is disabled. The determination of whether or not the Buck 1 is in bypass mode or standard switching regulation is constantly monitored while the regulator is enabled. If at any time the input voltage goes above 3.1V while in by-pass mode, the regulator will transition to normal operation. When the bypass mode is enabled, the output voltage of the buck that is in bypass mode is not regulated, but instead, the output voltage follows the input voltage minus the voltage drop seen across the FET and DCR of the inductor. The voltage drop is a direct result of the current flowing across those resistive elements. When Buck 1 transitions into bypass mode, there is an extra FET used in parallel along with the high side FET for transmission of the current to the load. This added FET will help reduce the resistance seen by the load and decrease the voltage drop. Equivalent Circuit of Bypass Operation of Buck 1 High Side FET VIN_B1 DCR 100m Max. Ideal Inductor, no resistance VOUT Buck 1 SW_B1 Model of Inductor FB_B1 Load Resistance Load Capacitance Bypass FET Figure 20. Bypass Operation - Equivalent Circuits Low Dropout Operation The device can operate nearly at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is: VIN_MIN=VOUT+ILOAD*(RDSON_PFET+RIND) Where: • ILOAD = Load Current 24 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com • • SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 RDSON_PFET = Drain to source resistance of PFET (high side) RIND = Inductor resistance (1) Device Operating Modes Startup Sequence The startup mode of the LM10524 will depend on the input voltage. Once VIN reaches the UVLO threshold, there is a 15 msec delay before the LM10524 determines how to set up the buck regulators. If bypass mode is enabled and if VIN is below 3.2V, then Buck 1 will be in bypass mode. See Bypass-FET Operation on Buck 1 for functionality description. If the VIN voltage is greater than 3.2V buck 1 will start up as the standard regulators. The 3 buck regulators are staggered during startup to avoid large inrush currents. There is a fixed delay of 2 msec between the startup of each regulator. The Startup Sequence will be: 1. 15 msec (±30%) delay after VIN UVLO threshold 2. 2 ms delay 3. Buck 3 Startup 4. 2 ms delay 5. Buck 1 Startup 6. 2 ms delay 7. Buck 2 Startup 6. 05V 5.7V 3.1V 2.9V VCOMP 2.6V 15ms VIN 2ms 2ms Buck3 2ms If Bypass is Enabled 2ms Buck1 2ms 2ms Buck2 2ms 2ms PWR_OK IRQ STARTUP Normal Operation OVLO STARTUP Bypass UVLO IRQ UVLO Figure 21. Normal Operating Modes Power-On The device is always enabled, unless outside of operating voltage range. There is no LM10524 Enable Pin. Once VIN reaches a minimum required input Voltage, the power-up sequence will be started automatically and the startup sequence will be initiated. Once the device is started, the output voltage of the Bucks 1 and 2 can be individually disabled by accessing their corresponding BKEN register bits (BUCK CONTROL). 25 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com Sleep Function The Device can be put into Sleep mode where all the outputs and the internal oscillator are switched off. Sleep mode is initiated by the DevSLP pin going high and the function is gated by the state of device pins DevSLP_OVR1, DevSLP_OVR2, and PowerUp_Enable. DevSLP_CTRL and SLEEP_EN pins are used to indicate the status of the device while DevSLP pin is high. Device Power Up During the device power up there is a 150ms period where all outputs will be low or tri-state. Following this the PowerUp_Mode output will be high and SLEEP_EN output will be low. The DEVSLP_CTRL output will mirror the state of the DEVSLP input. This initialization phase is complete when the PowerUp_Mode pin is externally pulled low and the device latches this low state on the pin. Normal Operation When Sleep mode is initiated by the DEVSLP pin being pulled high, this is mirrored to the DEVSLP_CTRL pin. The conditions for entry into Sleep mode are checked, DEVSLP_OVR1, DEVSLP_OVR2, and PowerUp_Mode pins must be low. If these conditions are met the Ouput shutdown is started and the DEVSLP_CTRL pin is driven low. The SLEEP_EN pin is driven high to indicate that Sleep mode is active. SLEEP_EN will remain high until all outputs have discharged to zero and DEVSLP goes low. In the case where the DEVSLP input goes low prior to full discharge, SLEEP_EN will remain high until all outputs have discharged. If any of the gating pins DEVSLP_OVR1, DEVSLP_OVR2, and PowerUp_Mode go high while in sleep mode SLEEP_EN will go low and DEVSLP_CTRL will go to the same state as DEVSLP pin. 19.2.3 DEVSLP Timing Initialization phase: VIN OUTPUTS FROM PMIC t150mst DEVSLP DEVSLP_CTRL DEVSLP_OVR1 DEVSLP_OVR2 POWERUP_MODE Sleep mode is available after this edge SLEEP_EN Start up period. All signals low or tri-state. Initialisation period for DevSLP circuit Figure 22. Initialization 26 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 After device power up the regulated outputs are on and at their specified outputs voltages indicated by the ‘Outputs from PMIC’ trace above. All DEVSLP signals are low or tri-state for a period of 150ms. Following this 150ms period the device will hold SLEEP_EN low and will allow the POWERUP_MODE pin to go high via a 1KΩ pullup resistor referenced to VIN supply. The DEVSLP function is ready when the POWERUP_MODE pin is pulled low externally, This negative edge on the POWERUP_MODE pin triggers the device to pulldown the POWERUP_MODE pin and this output remains low until a device reset. During this Initialization phase the DEVSLP_CTRL output mirrors the input at DEVSLP. The two signals DEVSLP_OVR1/2 are ignored by the device during this phase. Normal Operation, DEVSLP high period > Outputs discharge time: VIN t25mst OUTPUTS FROM PMIC 150ms DEVSLP DEVSLP_CTRL 2µs DEVSLP_OVR1 DEVSLP_OVR2 150ms POWERUP_MODE SLEEP_EN Figure 23. DEVSLP, Period Greater than Output Discharge Time In normal operation when DEVSLP goes high, DEVSLP_CNTL will go high. The device checks the status of DEVSLP_OVR1 and DEVSLP_OVR2 as well as POWERUP_MODE to ensure they are low to allow entry into SLEEP mode. If these conditions are met then the device will power down all outputs in their time sequence and the DEVSLP_CTRL pin is forced low. SLEEP_EN is forced high. Following the outputs discharging to zero DEVSLP goes low, SLEEP_EN is driven low and the regulated outputs switch on in their determined time sequence. Normal Operation, DEVSLP high period < Outputs discharge time 27 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com VIN t14mst OUTPUTS FROM PMIC 150ms DEVSLP t10mst DEVSLP_CTRL 2µs DEVSLP_OVR1 DEVSLP_OVR2 150ms POWERUP_MODE *4ms + 10ms min sleep slot time SLEEP_EN * Time set by OTP Figure 24. DEVSLP. Period less than Output Discharge Time As above; in normal operation when DEVSLP goes high DEVSLP_CNTL will go high. The device checks the status of DEVSLP_OVR1 and DEVSLP_OVR2 as well as POWERUP_MODE to ensure they are low to allow entry into SLEEP mode. If these conditions are met then the device will power down all outputs in their time sequence (4ms) and the DEVSLP_CTRL pin is forced low. SLEEP_EN is forced high. In this case DEVSLP goes high prior to full output discharge to zero. SLEEP_EN will be forced low after a set time, (programmable) with default set to10ms (+4ms) to ensure the device outputs discharge fully. This timing is important to ensure proper discharge of the output capacitance (up to 100µF in a 7.5ms period. The device outputs will also be switched on after this time period. To ensure all buck outputs are discharged a minimum sleep time exists, this time is configured to 12ms (programmable set by OTP).In the case where DEVSLP is active for, <12ms, the SLEEP_EN and sleep cycle will be held for a minimum of 12ms. 28 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 15 ms VIN 2ms Buck3 2ms Buck1 2ms Buck2 POK POWER UP_MODE DEVSLP DEVSLP_CTRL DEVSLP_OVR2 DEVSLP_OVR1 SLEEP_EN Normal Operation SLEEP STARTUP Figure 25. Sleep using DEVSLP_OVR1 or 2 Undervoltage Lockout (UVLO) The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device cannot be ensured. The part will automatically disable Buck 3. To prevent unstable operation, the undervoltage lockout (UVLO) has a hysteresis window of about 300 mV. A UVLO event will force the device into the reset state, all internal registers are reset. Once the supply voltage is above the UVLO hysteresis, the device will initiate a power-up sequence and then enter the active state. The Comparator will remain functional past the UVLO threshold until VIN reaches approximately 2.25V. Overvoltage Lockout (OVLO) The VIN voltage is monitored for a supply over voltage condition, for which the operation of the device cannot be ensured. The purpose of overvoltage lockout (OVLO) is to protect the part and all other consumers connected to the PMU outputs from any damage and malfunction. Once VIN rises over 6.05V all the Bucks will be disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100 mV. An OVLO event will force the device into the reset state; all internal registers are reset. Once the supply voltage is below the OVLO hysteresis, the device will initiate a power-up sequence, and then enter the active state. Operating maximum input voltage at which parameters are ensured is 5.5V. Absolute maximum of the device is 6.0V. Device Status, Interrupt Enable The LM10524 has 2 interrupt registers, INTERRUPT ENABLE and INTERRUPT STATUS. These registers can be read via the serial interface. The interrupts are not latched to the register and will always represent the current state and will not be cleared on a read. 29 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com If interrupt condition is detected, then corresponding bit in the INTERRUPT STATUS register (0x0D) is set to '1', and Interrupt output is asserted. There are 5 interrupt generating conditions: • Buck 3 output is over flag level (90% when rising, 85% when falling) • Buck 2 output is over flag level (90% when rising, 85% when falling) • Buck 1 output is over flag level (90% when rising, 85% when falling) • Comparator input voltage crosses over selected threshold Reading the interrupt register will not release Interrupt output. Interrupt generation conditions can be individually enabled or disabled by writing respective bits in INTERRUPT ENABLE register (0x0C) to '1' or '0'. Thermal Shutdown (TSD) The temperature of the silicon die is monitored for an over-temperature condition, for which the operation of the device can not be ensured. The part will automatically be disabled if the temperature is too high (>140°C). The thermal shutdown (TSD) will force the device into the reset state. In reset, all circuitry is disabled. To prevent unstable operation, the TSD has a hysteresis window of about 20°C. Once the temperature has decreased below the TSD hysteresis, the device will initiate a powerup sequence and then enter the active state. In the active state, the part will start up as if for the first time, all registers will be in their default state. Comparator The comparator on the LM10524 takes its inputs from the VCOMP pin and an internal threshold level which is programmed by the user. The threshold level is programmable between 2.0 and 4.0V with a step of 31 mV and a default comp code of 6h'18. The output of the comparator is the Interrupt pin. Its polarity can be changed using Register 0x0E bit 0. If Interrupt polarity = 0 → Active low (default) is selected, then the output is low if VCOMP value is greater than the threshold level. The output is high if the VCOMP value is less than the threshold level. If Interrupt polarity = 1 → Active high is selected then the output is high if VCOMP value is greater than the threshold level. The output is low if the VCOMP value is less than the threshold level. There is some hysteresis when VCOMP transitions from high to low, typically 60 mV. There is a control bit in register 0x0B, comparator control, that can double the hysteresis value. Figure 26. Comparator Thresholds Thermal Shutdown (TSD) The temperature of the silicon die is monitored for an over-temperature condition, for which the operation of the device cannot be ensured. The part will automatically be disabled if the temperature is too high. The thermal shutdown (TSD) will force the device into the reset state. In reset, all circuitry is disabled. To prevent unstable operation, the TSD has a hysteresis window of about 20°C. Once the temperature has decreased below the TSD hysteresis, the device will initiate a power-up sequence and then enter the active state. In the active state, the part will start up as if for the first time, all registers will be in their default state. External Components Selection All three switchers require an input capacitor and an output inductor-capacitor filter. These components are critical to the performance of the device. All three switchers are internally compensated and do not require external components to achieve stable operation. The output voltages of the bucks can be programmed through the SPI pins. 30 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 Output Inductors & Capacitors Selection There are several design considerations related to the selection of output inductors and capacitors: • Load transient response • Stability • Efficiency • Output ripple voltage • Over current ruggedness The device has been optimized for use with nominal LC values as shown in the Typical Application Circuit. Inductor Selection The recommended inductor values are shown in Typical Application Diagram. It is important to ensure the inductor core does not saturate during any foreseeable operational situation. The inductor should be rated to handle the peak load current plus the ripple current. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. IL(MAX) ILOAD(MAX) 'IRIPPLE ILOAD(MAX) | ILOAD(MAX) D VOUT , FS VIN D u (VIN VOUT ) 2 u L u FS D u (VIN VOUT ) (A typ.), 2 u 2.2 u 2.0 2 MHz, L 2.2 PH (2) There are two methods to choose the inductor saturation current rating: Recommended Method for Inductor Selection: The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating greater than the maximum device current limit, as specified in the Electrical Characteristics tables. In this case the device will prevent inductor saturation by going into current limit before the saturation level is reached. Alternate Method for Inductor Selection: If the recommended approach cannot be used care must be taken to ensure that the saturation current is greater than the peak inductor current: ISAT ! ILPEAK ILPEAK IRIPPLE D IRIPPLE 2 D u (VIN VOUT ) L u FS IOUTMAX VOUT VIN u EFF Where: • • • • • ISAT: Inductor saturation current at operating temperature ILPEAK: Peak inductor current during worst case conditions IOUTMAX: Maximum average inductor current IRIPPLE: Peak-to-Peak inductor current VOUT: Output voltage 31 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 • • • • • www.ti.com VIN: Input voltage L: Inductor value in Henries at IOUTMAX F: Switching frequency, Hertz D: Estimated duty factor EFF: Estimated power supply efficiency (3) ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst-case conditions, etc. Suggested Inductors and Their Suppliers The designer should choose the inductors that best match the system requirements. A very wide range of inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance loss limited), series resistance, maximum operating frequency, losses, etc. In general, smaller physical size inductors will have higher series resistance (DCR) and implicitly lower overall efficiency is achieved. Very lowprofile inductors may have even higher series resistance. The designer should try to find the best compromise between system performance and cost. Value Manufacturer Part Number DCR Current Package 1.0 µH Murata LQH44PN1R0NP0 30 mΩ 2.95A 1616 1.0 µH Murata LQH32PN1R0NNC 45mΩ 2.5A 3225(1210) 1.0 µH Coilcraft XFL3012-102MEC 35 mΩ 2.5A 3012 1.0 µH Coilcraft LPS4012-102NL 70mΩ 3.0A 4012 2.2 µH Coilcraft XFL3012-222MEC 81 mΩ 1.6A 3012 2.2 µH Murata LQH55PN2R2NR0L 31 mΩ 2.5A 2220 Output and Input Capacitors Characteristics Special attention should be paid when selecting these components. As shown in the following figure, the DC bias of these capacitors can result in a capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g.0402) may not be suitable in the actual application. Figure 27. Typical Variation in Capacitance vs. DC Bias 32 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 44µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −30°C, so some guard band must be allowed. Output Capacitor Selection The output capacitor of a switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high frequencies. Their inductive component can usually be neglected at the frequency ranges at which the switcher operates. Figure 28. Output Capacitor Equivalent Circuit The output-filter capacitor smooths out the current flow from the inductor to the load and helps maintain a steady output voltage during transient load changes. It also reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and low enough ESR to perform these functions. Note that the output voltage ripple increases with the inductor current ripple and the Equivalent Series Resistance of the output capacitor (ESRCOUT). Also note that the actual value of the capacitor’s ESRCOUT is frequency and temperature dependent, as specified by its manufacturer. The ESR should be calculated at the applicable switching frequency and ambient temperature. VOUT RIPPLEPP 'IRIPPLE where 'IRIPPLE 8 u FS u COUT D u (VIN VOUT ) and D 2 u L u FS VOUT VIN (4) Output ripple can be estimated from the vector sum of the reactive (capacitance) voltage component and the real (ESR) voltage component of the output capacitor where: VOUT RIPPLEPP V 2ROUT V 2COUT (5) where: VROUT IRIPPLE u ESRCOUT and VCOUT IRIPPLE 8 u FS u COUT Where: • • • VOUT-RIPPLE-PP: estimated output ripple, VROUT: estimated real output ripple, VCOUT: estimated reactive output ripple. (6) 33 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com The device is designed to be used with ceramic capacitors on the outputs of the buck regulators. The recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over voltage and temperature. The recommended value for the output capacitors is 22μF, 6.3V with an ESR of 2mΩ or less. The output capacitors need to be mounted as close as possible to the output/ground pins of the device. Model Vendor Type Vendor Voltage Rating Case Size GRM155B03J225KE95 Ceramic, X5R Murata 6.3V 603 GRM155R60J475ME47 Ceramic, X5R Murata 6.3V 603 GRM188B03J226MEA0 Ceramic, X5R Murata 6.3V 603 GRM21BB30J476ME15 Ceramic, X5R Murata 6.3V 805 Input Capacitor Selection There are 3 buck regulators in the LM10524 device. Each of these buck regulators has its own input capacitor which should be located as close as possible to their corresponding SWx_VIN and SWx_GND pins, where x designates Buck 1, 2 or 3. The 3 buck regulators operate at 120° out of phase, which means that they switch on at equally spaced intervals, in order to reduce the input power rail ripple. It is recommended to connect all the supply/ground pins of the buck regulators, SWx_VIN to two solid internal planes located under the device. In this way, the 3 input capacitors work together and further reduce the input current ripple. A larger tantalum capacitor can also be located in the proximity of the device. The input capacitor supplies the AC switching current drawn from the switching action of the internal power FETs. The in- put current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle both the RMS current and the dissipated power. The input capacitor must be rated to handle this current: IRMS _ CIN IOUT VOUT (VIN VOUT ) VIN (7) The power dissipated in the input capacitor is given by: PD _ CIN I2RMS _ CIN u RESR _ CIN (8) The device is designed to be used with ceramic capacitors on the inputs of the buck regulators. The recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over voltage and temperature. The minimum recommended value for the input capacitor is 10 µF with an ESR of 10mΩ or less. The input capacitors need to be mounted as close as possible to the power/ground input pins of the device. The input power source supplies the average current continuously. During the PFET switch on-time, however, the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the input capacitor. A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is estimated as follows: VPPIN IOUT u D IOUT u ESRCIN CIN u FS where: • • • • VPPIN: estimated peak-to-peak input ripple voltage, IOUT: output Current CIN: input capacitor value ESRCIN: input capacitor ESR. (9) This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS current rating. Capacitor RMS current estimated as follows: 34 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 www.ti.com SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 IRMSCIN • § I2 D u ¨ I2OUT RIPPLE ¨ 12 © · ¸ ¸ ¹ IRMSCIN: estimated input capacitor RMS current. (10) PCB Layout Considerations PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC- DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. LOOP 1 VIN CIN P S G D N D G SW Vin CONTROL LM10524 LOOP 2 L S COUT PGND Figure 29. Buck Schematic Showing Layout Sensitive Nodes 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched rapidly. The first loop starts from the CIN input capacitor, to the regulator Vin pin, through to PGND and back to the CIN input capacitor. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the inductor and then out to COUT and the load (see Figure 29). To minimize both loop areas the input capacitor should be placed as close as possible to the PVIN pin. Grounding for both the input and output capacitors should consist of a small localized top side plane that connects to PGND. The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. The SW pins should be directly connected with a trace that runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible and with a sufficient width. However, a trace that is wider than 100 mils will increase the copper area and cause too much capacitive loading on the SW pin. The inductors should be placed as close as possible to the SW pins to further minimize the copper area of the switch node. 3. Have a single point ground for all device analog grounds. The ground connections for the feedback components should be connected together then routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding can result in degraded load regulation or erratic switching behavior. 4. Minimize trace length to the FB pin. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. 5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. PCB Layout Thermal Dissipation for Micro SMD Package 1. Position ground layer as close as possible to micro SMD package. Second PCB layer is usually good option. 2. Draw power traces as wide as possible. Bumps which carry high currents should be connected to wide traces. This helps the silicon to cool down. 35 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 LM10524 SNVS986A – AUGUST 2013 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Original (August 2013) to Revision A • Page Added Device Information Table .......................................................................................................................................... 6 36 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM10524 PACKAGE OPTION ADDENDUM www.ti.com 15-Feb-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM10524TME-A/NOPB ACTIVE DSBGA YFR 46 250 TBD Call TI Call TI -30 to 85 V089 LM10524TME/NOPB ACTIVE DSBGA YFR 46 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 V088 LM10524TMX-A/NOPB ACTIVE DSBGA YFR 46 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 V089 LM10524TMX/NOPB ACTIVE DSBGA YFR 46 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 V088 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Feb-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM10524TME/NOPB DSBGA YFR 46 250 178.0 12.4 LM10524TMX-A/NOPB DSBGA YFR 46 1000 178.0 LM10524TMX/NOPB DSBGA YFR 46 1000 178.0 3.02 3.42 0.76 8.0 12.0 Q1 12.4 3.02 3.42 0.76 8.0 12.0 Q1 12.4 3.02 3.42 0.76 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10524TME/NOPB DSBGA YFR 46 250 210.0 185.0 35.0 LM10524TMX-A/NOPB DSBGA YFR 46 1000 210.0 185.0 35.0 LM10524TMX/NOPB DSBGA YFR 46 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE YFR0046 DSBGA - 0.675 mm max height SCALE 5.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D 0.675 MAX C SEATING PLANE BALL TYP 0.205 0.165 2.4 TYP SYMM H G F 2.8 TYP SYMM E 0.4 TYP D D: Max = 3.24 mm, Min = 3.18 mm C E: Max = 2.84 mm, Min = 2.78 mm B A 0.005 0.28 46X 0.25 C A B 1 2 3 4 5 6 7 0.4 TYP 4219451/A 06/2014 NOTES: 1. All linear dimensions are in millimeters. Any Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YFR0046 DSBGA - 0.675 mm max height DIE SIZE BALL GRID ARRAY 46X 0.24 0.21 (0.4) TYP 1 2 4 3 5 6 7 A (0.4) TYP B C D SYMM E F G H SYMM LAND PATTERN EXAMPLE SCALE:20X 0.05 MAX ( 0.225) METAL METAL UNDER MASK 0.05 MIN ( 0.225) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219451/A 06/2014 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). www.ti.com EXAMPLE STENCIL DESIGN YFR0046 DSBGA - 0.675 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 46X ( 0.25) 1 A 2 3 4 5 6 7 B (0.4) TYP C METAL TYP D SYMM E F G H SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:20X 4219451/A 06/2014 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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