CY25901 Spread Spectrum Clock Generator Features • • • • • • • Description Supports clock requirements for Spread Spectrum 40-MHz Spread Spectrum clock output Reference clock output Two spread bandwidths: 1%, 3% External clock or Cera-Lock input 3.3V operation 8-pin SOIC package The CY25901 clock generator provides a low-electromagnetic interference (EMI) clock output. It features Spread Spectrum technology, a modulation technique designed specifically for reducing EMI at the fundamental frequency and its harmonics. Table 1. Function Table CLKOUT (Spread Spectrum) SSSEL SSON REFOUT 0 0 XIN CY25901SC CY25901SC-1 = XIN ± 0.35% (0.7% center) = XIN ± 0.5% (1.0% center) 1 0 XIN = XIN ± 1.20% (2.4% center) = XIN ± 1.5% (3.0% center) X (don’t care) 1 XIN = XIN (No Spread) = XIN (No Spread) Block Diagram Pin Configuration XIN REFOUT Oscillator XOUT SSON CLKOUT 1 8 SSON# VDD 2 7 REFOUT VSS 3 6 SSSEL XIN 4 5 XOUT PLL CLKOUT SSCG SSSEL Cypress Semiconductor Corporation Document #: 38-07521 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 18, 2003 CY25901 Pin Description Pin No. Name I/O 1 CLKOUT 2 VDD PWR Power Supply. 3 VSS PWR Common Ground. 4 XIN I Oscillator Buffer Input. Connect to an external parallel resonant crystal or externally generated reference clock. 5 XOUT O Oscillator Buffer Output. Connect to an external parallel resonant crystal. Do not connect when an externally generated reference clock is applied at XIN. 6 SSSEL I Spread Spectrum Select Input. See Table 1. internally pulled up. 7 REFOUT O Buffered Output of XIN. 8 SSON# I Spread Spectrum Enable Input. When asserted low, Spread Spectrum is enabled. Internally pulled down. O Description Spread Spectrum Clock Output. See Table 1 for frequency selections. Spread Spectrum Clock Generator Spread Spectrum Clock Generator (SSCG) is a frequency modulation technique used to reduce EMI radiation generated by repetitive digital signals, mainly clocks. A clock radiates EM energy at its fundamental frequency as well as its harmonics. Spread Spectrum distributes this energy over a small frequency bandwidth, and decreasing the peak value of radiated energy over the spectrum. This technique is achieved by modulating the clock around or below the center of its reference frequency by a certain percentage (which also determines the energy distribution bandwidth). The SSCG function is enabled when SSON pin is set to low. Resulting in a spread bandwidth that is center spread, amount as selected by SSSEL (see Table 1). Figure 1. Modulation Frequency Profile Spread Spectrum 0 -10 -20 dBm -30 SS-ON -40 SS-OFF -50 -60 -70 -80 38 38 39 39 40 41 41 42 43 Frequency(MHz) Figure 2. Spread Spectrum Document #: 38-07521 Rev. ** Page 2 of 5 CY25901 Absolute Maximum Ratings Parameter Description VDD Core Supply Voltage VIN Input Voltage Condition Min. Max. Unit –0.5 4.6 V Relative to VSS –0.5 VDD+0.5 VDC TS Temperature, Storage Non Functional –65 150 °C TA Temperature, Operating Ambient Functional –10 85 °C – 150 °C 2000 – V TJ Temperature, Junction Functional ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL–94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level V–0 1 DC Specifications Parameter VDD Description Condition Operating Voltage 3.3V @ ±10% Voltage[1] VIL Input Low VIH Input High Voltage[1] Inputs VthXIN XIN Threshold Voltage XIN IDD Dynamic Supply Current VDD = 3.3V and CL = 0 IIL Input Low Current IIH Input High Current VOL Output Low Voltage IOL = 4.0 mA VOH Output High Voltage IOH = –4.0 mA CIN Input Capacitance CX XIN, XOUT Capacitance[2] PU/PD SSON# and SSSEL [1] Pull-up/Pull-down Resistance Min. Typ. Max. Unit 2.97 3.3 3.63 V – – 0.8 V 2.2 – – V 0.3*VDDC 0.5*VDDC 0.7*VDDC 25 V – 20 mA SSSEL = VSS –55 –30 – µA SSON = VDD – 30 55 µA – – 0.4 V 2.4 – – V SSON# and SSSEL Inputs – 5 10 pF XIN and XOUT – 5 – pF SSON# and SSSEL Inputs 50 100 200 kΩ Unit AC Specifications[3] Parameter Description Condition Min. Typ. Max. FIR Input Frequency Range ERXIN XIN Edge Rate 36 40 44 MHz XIN driven by external clock – 1 – V/nS TDCXIN TR XIN Duty Cycle XIN driven by external clock 40 50 60 % Outputs Rise Time[4] REFOUT, CLKOUT – – 3 ns TF Outputs Fall Time[4] REFOUT, CLKOUT – BW%1 CY25901SC, Spread % SSON=0,SSSEL = 0 0.5 – 3 ns 0.7 0.9 % BW%2 CY25901SC, Spread % SSON=0,SSSEL = 1 1.7 2.4 3.1 % BW%3 CY25901SC–1, Spread % SSON=0,SSSEL = 0 0.7 1 1.3 % BW%4 CY25901SC–1, Spread % SSON=0,SSSEL = 1 2.1 3 3.9 % TPU Power up to Stable Output[5] All output clocks – – 3 ms TDC CLKOUT Duty Cycle[5] CL = 15pF 45 50 55 % TCCJ REFOUT Cycle to Cycle jitter[5] CL = 15pF – 110 200 ps TCCJ CLKOUT Cycle to Cycle jitter[5] CL = 15pF – 110 200 ps Fmod Frequency Modulation Rate – 31 – kHz SSON# = GND Internally pulled down Notes: 1. SSSEL has internal pull-up and SSON has pull-down resistors. 2. In applications if a crystal is used for the input reference clock, refer to crystal manufacturer’s specifications for the required crystal load capacitor value. 3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. All outputs loaded with 15 pF. 4. Measured between 0.2*VDD and 0.8*VDD Volts. 5. Triggering is done at 1.5V VDDC. Document #: 38-07521 Rev. ** Page 3 of 5 CY25901 Application Schematic R1 CLKOUT 1 CLKOUT SSON# 8 VDD(3.3V) 2 VDD REFOUT 7 3 VSS SSSEL 6 4 XIN XOUT 5 R2 REFOUT 0.1µF CL1 XTAL CL2 Figure 3. Application Schematic Use crystal or cera-lock filter manufacturer’s recommended values for CL1 and CL2 load capacitors. 0.1-µF bypass capacitor for power pins should always be used and placed close to their VDD pin. R1 and R2 are series termination resistors for impedance matching. Ordering Information Part Number Package Type Production Flow CY25901SC–1 8-pin SOIC Commercial, –10°C to +85°C CY25901SC–1T 8-pin SOIC – Tape and Reel Commercial, –10°C to +85°C CY25901SC 8-pin SOIC Commercial, –10°C to +85°C CY25901SCT 8-pin SOIC –Tape and Reel Commercial, –10°C to +85°C Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 51-85066-A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07521 Rev. ** Page 4 of 5 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY25901 Document History Page Document Title: CY25901 Spread Spectrum Clock Generator Document Number: 38-07521 REV. ECN NO. Issue Date Orig. of Change ** 124075 02/19/03 RGL Document #: 38-07521 Rev. ** Description of Change New Data Sheet Page 5 of 5