99Jul Jul,1997 ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD 1048576-BIT(65536-WORD BY BY 16-BIT)CMOS 16-BIT)CMOS STATIC STATIC RAM RAM DESCRIPTION Power supply current M5M51016BTP,RT-10VL M5M51016BTP,RT-10VLL Access time (max) Active (max) stand-by (max) 100ns 120µA (VCC = 3.6V) 100ns 24µA (VCC = 3.6V) 0.3µA (VCC = 3.0V, typ) 12mA (1MHz) Single +3.3V power supply Low stand-by current 0.3µA (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by CS, BC1 & BC2 Data hold on +2V power supply Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51016BTP,RT .............................. 44pin 400mil TSOP(II) APPLICATION Small capacity memory units ADDRESS INPUTS NC A12 1 44 NC 2 43 A7 A6 A5 A4 3 42 4 41 5 40 BC1 BC2 A14 A15 6 39 A3 A2 A1 A0 7 38 8 37 9 36 CHIP SELECT INPUT CS FEATURES Type name PIN CONFIGURATION (TOP VIEW) (0V)GND OUTPUT ENABLE INPUT OE NC DQ1 DQ2 DQ3 DATA DQ4 INPUTS/ OUTPUTS DQ5 DQ6 DQ7 DQ8 10 11 12 13 14 M5M51016BTP The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low stand-by current and low operation current and ideal for the battery back-up application. The M5M51016BTP,RT are packaged in a 44-pin thin small outline package which is a high reliability and high density surface mount device (SMD). Two types of devices are available. M5M51016BTP(normal lead bend type package), M5M51016BRT (reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board. 35 34 33 32 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 BYTE CONTROL INPUTS ADDRESS INPUTS A13 WRITE CONTROL W INPUTS A8 A9 ADDRESS INPUTS A11 A10 GND(0V) NC DQ16 DQ15 DQ14 DQ13 DATA INPUTS/ DQ12 OUTPUTS DQ11 DQ10 DQ9 VCC(5V) Outline 44P3W - H (400mil TSOP Normal Bend) 44 1 43 2 42 3 41 4 40 5 39 6 38 7 37 8 DATA INPUTS/ OUTPUTS 36 35 34 33 32 M5M51016BRT NC BC1 BC2 A14 ADDRESS INPUTS A15 A13 WRITE CONTROL W INPUTS A8 ADDRESS A9 INPUTS A11 A10 (0V)GND NC DQ16 DQ15 DQ14 BYTE CONTROL INPUTS 9 10 11 12 13 31 14 30 15 29 16 DQ13 DQ12 DQ11 DQ10 DQ9 28 17 27 18 26 19 25 20 24 21 (5V)VCC 23 22 NC A12 A7 A6 A5 ADDRESS A4 INPUTS A3 A2 A1 A0 SELECT CS CHIP INPUT GND(0V) OUTPUT ENABLE OE INPUT NC DQ1 DQ2 DQ3 DQ4 DATA INPUTS/ DQ5 OUTPUTS DQ6 DQ7 DQ8 Outline 44P3W - J (400mil TSOP Reverse Bend) NC : NO CONNECTION MITSUBISHI ELECTRIC 1 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M51016B series are determined by a combination of the device control inputs BC1, BC 2, CS, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the high level CS. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, BC1, BC2 or CS, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the databus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and CS are in an active state. (BC1 and/or BC2=L,CS=H) When setting BC1 at a high level and the other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enabled, and lower-Byte are in a non-selectable mode.And when setting BC2 at a high level and the other pins are in an active state, lower-Byte are in a selectable mode and upper -Byte are in a non-selectable mode. When setting BC1 and BC2 at a high level or CS at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and CS. The power supply current is reduced as low as the stand-by current which is specified as I CC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during powerfailure or power-down operation in the non-selected mode. DQ1~8 DQ9~16 ICC CS BC1 BC2 W OE Mode L X X X X Non selection High-Z High-Z Stand-by X H H X X Non selection High-Z High-Z Stand-by Din Active H H L L X Upper-Byte Write High-Z H H L H L Upper-Byte Read High-Z Dout Active H H L H H High-Z High-Z Active H L H L X Lower-Byte Write Din High-Z Active H L H H L Lower-Byte Read Dout High-Z Active L H H H High-Z High-Z Active H Din Din H L L L X Word Write Active H L L H L Word Read Dout Dout Active L L H H High-Z High-Z Active H (High-Z=High-impedance) A13 39 A2 8 COLUMN DECODER A4 6 ADDRESS INPUT BUFFER A9 36 A0 10 A5 5 CS 11 BYTE CONTROL INPUTS BC1 43 19 DQ5 20 DQ6 21 DQ7 24 DQ9 25 DQ10 DATA INPUTS/ OUTPUTS 26 DQ11 27 DQ12 28 DQ13 29 DQ14 30 DQ15 INPUT DATA CONTROL CLOCK GENERATOR INPUT DATA CONTROL CHIP SELECT INPUT BLOCK DECODER A11 35 17 DQ3 18 DQ4 31 DQ16 ADDRESS INPUT BUFFER A10 34 15 DQ1 16 DQ2 22 DQ8 A8 37 ADDRESS INPUTS OUTPUT BUFFER ( 1024 ROWS x 256 COLUMNS x 4 BLOCKS ) OUTPUT BUFFER A14 41 A1540 65536 WORDS x16 BITS SENSE AMP. A12 2 ROW DECODER A6 4 A7 3 ADDRESS INPUT BUFFER A1 9 A3 7 SENSE AMP. BLOCK DIAGRAM BC2 42 WRITE CONTROL W 38 INPUT OUTPUT ENABLE OE 13 INPUT 23 Vcc 33 GND(0V) 12 GND (0V) MITSUBISHI ELECTRIC 2 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Topr Tstg Parameter Ratings – 0.3 ~ 4.6 – 0.3* ~ Vcc + 0.3 Conditions Supply voltage Input voltage Output voltage With respect to GND 0 ~ Vcc 1 – 40 ~ 85 – 65 ~ 150 o Ta=25 C Power dissipation Operating temperature Storage temperature Unit V V V W C o C o * –3.0V in case of AC ( Pulse width < 50ns ) DC ELECTRICAL CHARACTERISTICS (Ta= -40 ~85 C, Vcc=3.3V _+ 0.3V, unless otherwise noted) o Symbol Parameter Test conditions VIH VIL VOH1 VOH2 VOL II High-level input voltage Low-level input voltage High-level output voltage 1 High-level output voltage 2 Low-level output voltage Input current IOH = – 1mA IOH = – 0.1mA IOL = 2mA VI =0 ~ Vcc IO Output current in off-state BC1 and BC2 = VIH or CS = VIL or OE = VIH, VI/O = 0 ~ Vcc ICC1W Word operation (16bit) Active supply current (AC,TTL level) BC1 and BC2 = VIL, CS = VIH other inputs = VIH or VIL Output-open(duty 100%) ICC2B Byte operation (8bit) Active supply current (AC,TTL level) (BC1 = VIH and BC2 = VIL) or (BC1 = VIL and BC2 = VIH), CS = VIH other inputs = VIH or VIL Output-open(duty 100%) ICC3 Stand-by current ICC2W ICC1B ICC4 1) CS < 0.2V, other inputs = 0~Vcc 2) BC1,BC2 > Vcc - 0.2V, CS > Vcc - 0.2V other inputs = 0~Vcc BC1 and BC2 = VIH or CS = VIL, other inputs = 0~Vcc Stand-by current Min Limits Typ Max Vcc+0.3V 2.0 – 0.3* 2.4 Unit 0.4 _+1 V V V V V µA _+1 µA Min cycle 50 mA 1MHz 12 mA Min cycle 30 mA 1MHz 10 mA 120 µA 24 µA 1 mA Max 6 9 8 Unit 0.6 Vcc–0.5V -VL -VLL * –3.0V in case of AC ( Pulse width < 30ns ) CAPACITANCE (Ta= -40 ~ 85 C , Vcc=3.3V _+ 0.3V, unless otherwise noted) o Symbol CI CIBC CO Parameter Input capacitance ( except BC1,BC2) Input capacitance ( BC1,BC2 ) Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ pF pF pF Note 1: Direction for current flowing into an IC is positive (no mark). o 2: Typical value is Vcc = 3.3V, Ta = 25 C MITSUBISHI ELECTRIC 3 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85 C , VCC = 3.3V _+ 0.3V, unless otherwise noted ) o (1) MEASUREMENT CONDITIONS Input pulse level ...................... VIH = 2.2V, VIL = 0.4V Input rise and fall time .............. 5ns Reference level ........................ VOH = 1.5V, VOL = 1.5V Output loads ............................ Fig.1,CL = 30pF CL = 5pF ( for ten, tdis ) Transition is measured _+ 500mV from steady state voltage. ( for ten, tdis ) 1TTL DQ CL ( Including scope and JIG ) Fig.1 Output load (2) READ CYCLE Limits Symbol tCR ta(A) ta(BC1) ta(BC2) ta(CS) ta(OE) tdis(BC1) tdis(BC2) tdis(CS) tdis(OE) ten(BC1) ten(BC2) ten(CS) ten(OE) tv(A) M5M51016B -10VL,-10VLL Min Typ Max 100 100 100 100 100 50 35 35 35 35 10 10 10 5 10 Parameter Read cycle time Address access time Byte control 1 access time Byte control 2 access time Chip select access time Output enable access time Output disable time after BC1 high Output disable time after BC2 high Output disable time after CS low Output disable time after OE high Output enable time after BC1 low Output enable time after BC2 low Output enable time after CS high Output enable time after OE low Data valid time after address Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2 ) tsu(CS) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Limits M5M51016B -10VL,-10VLL Max Min Typ 100 75 0 85 85 85 85 40 0 0 35 35 5 5 Parameter Write cycle time Write pulse width Address set up time Address set up time with respect to W Byte control 1 setup time Byte control 2 setup time Chip select set up time Data set up time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low MITSUBISHI ELECTRIC Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle tCR A0~15 ta(A) tv (A) ta (BC1) or ta (BC2) BC1 and/or BC2 (Note 3) tdis (BC1) or tdis (BC2) CS (Note 3) ta (CS) (Note 3) tdis (CS) ta (OE) (Note 3) ten (OE) OE (Note 3) tdis (OE) ten (BC1) ten (BC2) (Note 3) ten (CS) DQ1~16 DATA VALID W = "H" level Write cycle (W control mode) tCW A0~15 tsu (BC1) or tsu (BC2) BC1 and/or BC2 (Note 3) (Note 3) CS tsu (CS) (Note 3) (Note 3) tsu (A-WH) OE tsu (A) tw (W) trec (W) W tdis (W) ten(OE) ten (W) tdis (OE) DQ1~16 DATA IN STABLE tsu (D) th (D) MITSUBISHI ELECTRIC 5 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM Write cycle ( BC control mode) tCW A0~15 tsu (A) tsu (BC1) or tsu (BC2) trec (W) BC1 and/or BC2 CS (Note 3) (Note 3) (Note 5) W (Note 4) (Note 3) (Note 3) tsu (D) th (D) DATA IN STABLE DQ1~16 Write cycle (CS control mode) tCW A0~15 BC1 and/or BC2 (Note 3) (Note 3) tsu (A) tsu (CS) trec (W) CS (Note 5) W (Note 4) (Note 3) (Note 3) tsu (D) DQ1~16 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while CS high overlaps BC1 and/or BC2 low and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or rising edge of CS, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode. MITSUBISHI ELECTRIC 6 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-10VL-I, -10VLL-I 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85o C , unless otherwise noted) Symbol Parameter Test conditions VCC (PD) Power down supply voltage Min 2 VI (BC) Byte control input BC1 & BC2 2.0 VI (CS) Chip select input CS 3.0V < VCC(PD) VCC(PD) < 3.0V Power down supply current VCC = 3V -VL 1) CS < 0.2V other inputs = 0 ~ 3V 2) BC1 & BC2 > Vcc 0.2V, -VLL CS > VCC 0.2V,other inputs=0~3V ICC (PD) Limits Typ Max Unit V V 0.6 0.2 V 100 µA 20 0.3 (Note 7) Limits Typ Max o Note7. ICC (PD) = 1µA in case of Ta = 25 C (2) TIMING REQUIREMENTS (Ta = -40 ~ 85o C , unless otherwise noted ) Symbol tsu (PD) trec (PD) Parameter Test conditions Power down set up time Power down recovery time Min 0 5 Unit ns ms (3) POWER DOWN CHARACTERISTICS BC control mode VCC t su (PD) 3.0V 3.0V t rec (PD) 2.0V 2.0V BC1 & BC2 BC1 & BC2 > VCC 0.2V CS control mode VCC CS t su (PD) 3.0V 3.0V 0.2V t rec (PD) 0.2V CS < 0.2V MITSUBISHI ELECTRIC 7