Intersil ISL71090SEH12 Radiation hardened ultra low noise, precision voltage reference Datasheet

Radiation Hardened Ultra Low Noise, Precision Voltage
Reference
ISL71090SEH12
Features
The ISL71090SEH12 is an ultra low noise, high DC accuracy
precision voltage reference with a wide input voltage range
from 4V to 30V. The ISL71090SEH12 uses the Intersil
Advanced Bipolar technology to achieve sub 2µVP-P noise at
0.1Hz with an accuracy over temperature and radiation of
0.15%.
• Reference output voltage . . . . . . . . . . . . . . . . . 1.25V ±0.05%
• Accuracy over temperature and radiation . . . . . . . . . .±0.15%
• Output voltage noise . . . . . . . . . . 1µVP-P Typ (0.1Hz to 10Hz)
• Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930µA (Typ)
• Tempco (box method) . . . . . . . . . . . . . . . . . . . 10ppm/°C Max
The ISL71090SEH12 offers a 1.25V output voltage with
10ppm/°C temperature coefficient and also provides
excellent line and load regulation. The device is offered in an
8 Ld Flatpack package.
• Output current capability . . . . . . . . . . . . . . . . . . . . . . . . 20mA
The ISL71090SEH12 is ideal for high-end instrumentation,
data acquisition and applications requiring high DC precision
where low noise performance is critical.
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
Applications
• RH voltage regulators precision outputs
• Precision voltage sources for data acquisition system for
space applications
• Strain and pressure gauge for space applications
• Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/V
• Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ppm/mA
• Radiation environment
- High dose rate (50-300rad(Si)/s) . . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 100krad(Si)*
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm2/mg
*Product capability established by initial characterization. The
“EH” version is acceptance tested on a wafer by wafer basis to
50krad(Si) at low dose rate
• Electrically screened to SMD 5962-13211
Related Literature
• AN1862, “ISL71090SEH12 Evaluation Board User’s Guide”
• AN1863, “SEE Testing of the ISL71090SEH12”
• AN1864, “Radiation Report of the ISL71090SEH12”
ISL71090SEH12
1
2
VIN
0.1µF
3
4
DNC
DNC
VIN
DNC
COMP
VOUT
GND
TRIM
8
7
VREF
1.2530
6
5
UNIT3
1.2525
1µF
UNIT5
C
REFIN
VDD
VEE
VDD
DACOUT
BIPOFF
NOTE: Select C to minimize
settling time.
D0
1.1k
GND
UNIT2
UNIT4
1.2505
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
HS-565BRH
1
1.2515
1.2500
-60
FIGURE 1. ISL71090SEH12 TYPICAL APPLICATION DIAGRAM
June 26, 2013
FN8452.0
UNIT1
1.2510
D12
VEE
VOUT (V)
1.2520
FIGURE 2. VOUT vs TEMPERATURE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL71090SEH12
Ordering Information
ORDERING NUMBER
(Notes 1, 2, 3)
PART
NUMBER
VOUT OPTION
(V)
TEMP RANGE
(°C)
PACKAGE
TAPE & REEL
(Pb-Free)
PKG. DWG. #
5962R1321101VXC
ISL71090SEHVF12
1.25
-55 to +125
8 Ld Flatpack
K8.A
ISL71090SEHF12/PROTO
ISL71090SEHF12/PROTO
1.25
-55 to +125
8 Ld Flatpack
K8.A
ISL71090SEHF12EVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL71090SEH12. For more information on MSL please see tech brief
TB363
3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in this
“Ordering Information” table must be used when ordering.
Pin Configuration
ISL71090SEH12
(8 LD FLATPACK)
TOP VIEW
DNC
1
8
DNC
VIN
2
7
DNC
COMP
3
6
VOUT
GND
4
5
TRIM
Pin Descriptions
PIN NUMBER
PIN NAME
ESD CIRCUIT
DESCRIPTION
1, 7, 8
DNC
3
Do not Connect. Internally terminated.
2
VIN
1
Input Voltage Connection
3
COMP
2
Compensation and Noise Reduction Capacitor
4
GND
1
Ground Connection. Also connected to the lid.
5
TRIM
2
Voltage Reference Trim input
6
VOUT
2
Voltage Reference Output
VDD
VDD
CAPACITIVELY
TRIGGERED CLAMP
VDD
PIN
DNC
GND
GND
ESD CIRCUIT 1
2
ESD CIRCUIT 2
ESD CIRCUIT 3
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June 26, 2013
ISL71090SEH12
Functional Block Diagram
VIN
BIAS
REGULATOR
DNC
BAND
GAP
REFERENCE
DNC
3.7V
DNC
1.2V
Gm
VOUT
GND
COMP
TRIM
1.2V
3
FN8452.0
June 26, 2013
ISL71090SEH12
Absolute Maximum Ratings
Thermal Information
Max Voltage
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +40V
VIN to GND at an LET = 86MeV • cm2/mg . . . . . . . . . . . . . . -0.5V to +36V
VOUT to GND (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VOUT + 0.5V
Voltage on any Pin to Ground . . . . . . . . . . . . . . . . . -0.5V to +VOUT + 0.5V
Voltage on DNC Pins . . . . . . . . . . . . No connections permitted to these pins
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750V
θJA (°C/W) θJC (°C/W)
Thermal Resistance (Typical)
8 Ld Flatpack Package (Notes 4, 5). . . . . .
140
15
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile (Note 6). . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to +30V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the "case temp" location is the center of the ceramic on the package underside.
6. Post-reflow drift for the ISL71090SEH12 devices can be 100µV typical based on experimental results with devices on FR4 double sided boards. The
engineer must take this into account when considering the reference voltage after assembly.
7. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer by wafer basis to 50krad(Si) at low dose rate.
8. The output capacitance used for SEE testing is CIN = 0.1µF and COUT = 1µF.
Electrical Specifications
VIN = 5V, IOUT = 0, CL = 0.1µF and CC = 0.01µF unless otherwise specified. Boldface limits apply over the
operating temperature range, -55°C to +125°C.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
%
VOUT
Output Voltage
VIN = 5V
VOA
VOUT Accuracy @ TA = +25°C (Note 6)
VOUT = 1.25V
-0.05
+0.05
VOA
VOUT Accuracy @ TA = -55°C to +125°C VOUT = 1.25V
-0.15
+0.15
%
10
ppm/°C
30
V
TC VOUT
1.252
Output Voltage Temperature
Coefficient (Note 11)
VIN
Input Voltage Range (Note 10)
VOUT = 1.25V
4.0
V
IIN
Supply Current
ΔVOUT /ΔVIN
Line Regulation
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 20mA
VD
Dropout Voltage
(Note 10)
VOUT = 1.25V @ 10mA
ISC+
Short Circuit Current
TA = +25°C, VOUT tied to GND
53
mA
ISC-
Short Circuit Current
TA = +25°C, VOUT tied to VIN
-23
mA
tR
Turn-on Settling Time
90% of final value, CL = 1.0µF,
CC = open
250
µs
Ripple Rejection
f = 120Hz
90
dB
eN
Output Voltage Noise
0.1Hz ≤ f ≤ 10Hz, VOUT = 1.25V
1.0
µVP-P
VN
Broadband Voltage Noise
10Hz ≤ f ≤ 1kHz, VOUT = 1.25V
1.2
µVRMS
PSRR
ΔVOUT/Δt
VIN = 4.0V to 30V, VOUT = 1.25V
0.930
1.28
mA
8
18
ppm/V
35
55
ppm/mA
1.7
2.25
V
Noise Density
f = 1kHz, VOUT = 1.25V, VIN = 6V
21
nV/√Hz
Long Term Drift
TA = 125°C, 1000hrs
15
ppm
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. VIN-VOUT measured at the point where VOUT drops 1mV from the nominal measured value.
11. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT(max) - VOUT(min) is divided
by the temperature range; in this case, -55°C to +125°C = +180°C.
12. Dropout Voltage is the minimum VIN - VOUT differential voltage measured at the point where VOUT drops 1mV from VIN = nominal at TA = +25°C.
4
FN8452.0
June 26, 2013
ISL71090SEH12
Typical Performance Curves V
4
IN =
5V, VOUT = 1.25V, TA = +25°C, unless otherwise specified.
20
LINE REG ppm/V +125°C
10
2
LOAD REG (ppm/mA)
LINE REG (ppm/V)
3
LINE REG ppm/V +25°C
1
0
LINE REG ppm/V -55°C
-1
-2
0
5
10
15
20
25
30
0
-20
LOAD REG ppm/mA (VIN = 5V +25°C)
-30
-40
-50
35
LOAD REG ppm/mA (VIN = 5V -55°C)
-10
LOAD REG ppm/mA (VIN = 5V +125°C)
0
2
4
VIN (V)
6
8
10
12
14
16
18
20
IOUT (mA)
FIGURE 3. LINE REGULATION OVER TEMPERATURE (0mA)
FIGURE 4. LOAD REGULATION OVER TEMPERATURE AT VIN = 5V
(ppm/mA)
1.2520
1.2515
VOUT (V) -10mA +25°C
VOUT (V) -10mA -55°C
VOUT (V)
1.2510
VOUT (V) 0mA +25°C
1.2505
VOUT (V) 0mA -55°C
VOUT (V) 20mA -55°C
1.2500
VOUT (V) 20mA +25°C
VOUT (V) -10mA +125°C
1.2495
VOUT (V) 0mA +125°C
1.2490
1.2485
VOUT (V) 20mA +125°C
0
5
10
15
20
25
30
35
VIN (V)
FIGURE 5. VOUT vs VIN AT 0mA, 20mA AND -10mA
3.0
40
DROPOUT V AT +150°C
30
1.5
DROPOUT V AT +25°C
DROPOUT V AT +125°C
1.0
10
0
-10
-20
0.5
0
+25°C VIN = 5V, VOUT = 1.25V, IOUT = 0mA TO 1mA TO 0mA,
COMP = 1nF, COUT = 1µF, V/DIV = 20mV/DIV
20
2.0
ΔVOUT (mV)
DROPOUT (V)
2.5
-30
0
0.005
0.010
0.015
0.020
IOUT (mA)
FIGURE 6. DROPOUT VOLTAGE FOR 1.25V
5
0.025
-40
-200
0
200
400
600
800
TIME (µs)
FIGURE 7. LOAD TRANSIENT (0mA TO 1mA)
FN8452.0
June 26, 2013
ISL71090SEH12
Typical Performance Curves V
IN =
5V, VOUT = 1.25V, TA = +25°C, unless otherwise specified. (Continued)
VOUT 200mV/DIV
1.2530
UNIT3
1.2525
UNIT5
VOUT (V)
1.2520
VIN 10V/DIV
UNIT1
1.2515
UNIT2
1.2510
UNIT4
1.2505
1.2500
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
50µs/DIV
FIGURE 8. TURN-ON SETTLING TIME
FIGURE 9. TYPICAL TEMPERATURE COEFFICIENT PLOT FOR 5 UNITS
0
1.E-05
PSRR (dB)
NOISE (V/√Hz)
-20
1.E-06
1.E-07
-40
-60
-80
1.E-08
-100
1.E-09
0.1
f = 1kHz, En = 21.02nV/√Hz
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 10. NOISE DENSITY vs FREQUENCY (VIN = 6V, Rl = OPEN)
6
-120
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 11. PSRR (+25°C, VIN = 5V, VOUT = 1.25V, IOUT = 0mA,
CIN = 0.1µF, COUT = 1µF, COMP = 1nF, VSIG = 300mVP-P)
FN8452.0
June 26, 2013
ISL71090SEH12
Device Operation
Output Voltage Adjustment
Bandgap Precision Reference
The output voltage can be adjusted above and below the
factory-calibrated value via the trim terminal. The trim terminal is
the negative feedback divider point of the output op amp. The
positive input of the amplifier is about 1.216V, and in feedback,
so will be the trim voltage. The suggested method to adjust the
output is to connect a 1MΩ external resistor directly to the trim
terminal and connect the other end to the wiper of a
potentiometer that has a 100kΩ resistance and whose outer
terminals connect to VOUT and ground. If a 1MΩ resistor is
connected to trim, the output adjust range will be ±6.3mV. The
TRIM pin should not have any capacitor tied to its output, also it
is important to minimize the capacitance on the trim terminal
during layout to preserve output amplifier stability. It is also best
to connect the series resistor directly to the trim terminal, to
minimize that capacitance and also to minimize noise injection.
Small trim adjustments will not disturb the factory-set
temperature coefficient of the reference, but trimming near the
extreme values can.
The ISL71090SEH12 uses a bandgap architecture and special
trimming circuitry to produce a temperature compensated,
precision voltage reference with high input voltage capability and
moderate output current drive.
Applications Information
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting
location should be reviewed. The device uses a ceramic flatpack
package. Generally, mild stresses to the die when the printed
circuit (PC) board is heated and cooled, can slightly change the
shape. Because of these die stresses, placing the device in areas
subject to slight twisting can cause degradation of reference
voltage accuracy. It is normally best to place the device near the
edge of a board, or on the shortest side, because the axis of
bending is most limited in that location. Mounting the device in a
cutout also minimizes flex. Obviously, mounting the device on
flexprint or extremely thin PC material will likewise cause loss of
reference accuracy.
Board Assembly Considerations
Some PC board assembly precautions are necessary. Normal
output voltage shifts of typically 100µV can be expected with
Pb-free reflow profiles or wave solder on multi-layer FR4 PC
boards. Precautions should be taken to avoid excessive heat or
extended exposure to high reflow or wave solder temperatures.
Output Stage
The output stage of the device has a push pull configuration with
an high side PNP and a low side NPN. This helps the device to act
as a source and sink. The device can source 20mA.
Use of COMP Cap
The reference can be compensated for the COUT capacitors used
by adding a capacitor from COMP pin to GND. See Table 1 for
recommended values. of the COMP capacitor.
TABLE 1.
Noise Performance and Reduction
The output noise voltage over the 0.1Hz to 10Hz bandwidth is
typically 2µVP-P (VOUT = 1.25V). The noise measurement is made
with a 9.9Hz bandpass filter. Noise in the 10Hz to 1kHz
bandwidth is approximately 1.6µVRMS (VOUT = 1.25V), with 0.1µF
capacitance on the output. This noise measurement is made
with a band pass filter of 990Hz. Load capacitance up to 10µF
(with COMP) can be added but will result in only marginal
improvements in output noise and transient response.
Turn-On Time
Normal turn-on time is typically 250µs, the circuit designer must
take this into account when looking at power-up delays or
sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (Tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures which
provide for the maximum voltage deviation and take the total
variation, (VHIGH - VLOW), this is then divided by the temperature
extremes of measurement (THIGH – TLOW). The result is divided by
the nominal reference voltage (at T = +25°C) and multiplied by
106 to yield ppm/°C. This is the “Box” method for specifying
temperature coefficient.
7
COUT
(µF)
CCOMP
(nF)
0.1
1
1
1
10
10
SEE Testing
The device was tested under ion beam at an LET of
86MeV•cm2/mg. The device did not latch up or burn out to a
VDD of 36V and at +125°C. Single Event transients were
observed and are summarized in the Table 2:
TABLE 2.
VIN
(V)
IOUT
(mA)
COUT
(µF)
SET
(% VOUT)
4
5
1
-4.6
30
5
1
-4.4
30
5
10
-1.0
DNC Pins
These pins are for trimming purpose and for factory use only. Do
not connect these to the circuit in any way. It will adversely effect
the performance of the reference.
FN8452.0
June 26, 2013
ISL71090SEH12
Package Characteristics
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
Weight of Packaged Device
0. 31 Grams (Typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Connected to lead #4 (GND)
Case Isolation to Any Lead: 20 x 109 Ω (min)
ASSEMBLY RELATED INFORMATION
SUBSTRATE POTENTIAL
Floating
Die Characteristics
ADDITIONAL INFORMATION
Die Dimensions
1464µm x 1744µm (58mils x 69mils)
Thickness: 483µm ± 25µm (19mils ± 1 mil)
WORST CASE CURRENT DENSITY
<2 x 105 A/cm2
Interface Materials
PROCESS
Dielectrically Isolated Advanced Bipolar Technology- PR40 SOI
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
DNC
DNC
DNC
VS
COMP
VOUT
SENSE
GND
POWR
VOUT
FORCE
GND
QUIET
8
(see Note 13, Table 3)
TRIM
FN8452.0
June 26, 2013
ISL71090SEH12
TABLE 3. DIE LAYOUT X-Y COORDINATES
PAD NAME
PIN NUMBER
X
(µm)
Y
(µm)
BOND WIRES
PER PAD
GND PWR
4
-104
0
1
GND QUIET
4
0
0
1
COMP
3
-108
589
1
VS
2
-125
1350
1
DNC
1
-108
1452
1
DNC
8
1089
1452
1
DNC
7
1089
1350
1
VOUT SENSE
6
1072
598
1
VOUT FORCE
6
1088
1
1
TRIM
5
985
-25
1
NOTES:
13. Origin of coordinates is the centroid of GND QUIET.
14. Bond wire size is 1.0 mil.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
June 26, 2013
FN8452.0
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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9
FN8452.0
June 26, 2013
ISL71090SEH12
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 3, 3/13
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
0.005 (0.13)
MIN
4
PIN NO. 1
ID AREA
0.022 (0.56)
0.015 (0.38)
0.110 (2.79)
0.087 (2.21)
0.265 (6.73)
0.245 (6.22)
TOP VIEW
0.036 (0.92)
0.026 (0.66)
0.009 (0.23)
0.004 (0.10)
6
0.265 (6.75)
0.245 (6.22)
-D-
-H-
-C-
0.180 (4.57)
0.170 (4.32)
SEATING AND
BASE PLANE
0.370 (9.40)
0.325 (8.26)
0.03 (0.76) MIN
SIDE VIEW
0.007 (0.18)
0.004 (0.10)
NOTES:
LEAD FINISH
0.009 (0.23)
BASE
METAL
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
3
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
10
FN8452.0
June 26, 2013