TI DAC8564ICPWR 16-bit, quad channel, ultra-low glitch, voltage output digital-to-analog converter with 2.5v, 2ppm/â°c internal reference Datasheet

 DAC8564
DA
C8
564
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference
FEATURES
1
• Relative Accuracy: 4LSB
• Glitch Energy: 0.15nV-s
• Internal Reference:
– 2.5V Reference Voltage (enabled by default)
– 0.02% Initial Accuracy
– 2ppm/°C Temperature Drift (typ)
– 5ppm/°C Temperature Drift (max)
– 20mA Sink/Source Capability
• Power-On Reset to Zero-Scale
• Ultra-Low Power Operation: 1mA at 5V
• Wide Power Supply Range: +2.7V to +5.5V
• 16-Bit Monotonic Over Temperature Range
• Settling Time: 10µs to ±0.003% Full-Scale
Range (FSR)
• Low-Power Serial Interface with
Schmitt-Triggered Inputs
• On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
• Drop-In and Functionally Compatible with
DAC8534 and DAC8554
• Pin-Compatible with DAC8555 and DAC8565
• 1.8V to 5.5V Logic Compatibility
• Temperature Range: –40°C to +105°C
234
APPLICATIONS
•
•
•
•
•
•
DESCRIPTION
The DAC8564 is a low-power, voltage-output,
four-channel, 16-bit digital-to-analog converter (DAC).
The device includes a 2.5V, 2ppm/°C internal
reference (enabled by default), giving a full-scale
output voltage range of 2.5V. The internal reference
has an initial accuracy of 0.02% and can source up to
20mA at the VREFH/VREFOUT pin. The device is
monotonic, provides very good linearity, and
minimizes undesired code-to-code transient voltages
(glitch). The DAC8564 uses a versatile 3-wire serial
interface that operates at clock rates up to 50MHz.
The interface is compatible with standard SPI™,
QSPI™, Microwire™, and digital signal processor
(DSP) interfaces.
The DAC8564 incorporates a power-on-reset circuit
that ensures the DAC output powers up at zero-scale
and remains there until a valid code is written to the
device. The device contains a power-down feature,
accessed over the serial interface, that reduces the
current consumption of the device to 1.3µA at 5V.
The low-power consumption, internal reference, and
small footprint make this device ideal for portable,
battery-operated equipment. The power consumption
is 2.9mW at 3V, reducing to 1.5µW in power-down
mode.
The DAC8564 is drop-in and functionally compatible
with the DAC8534 and DAC8554, and pin-compatible
with DAC8555 and DAC8565. The DAC8564 is
available in a TSSOP-16 package.
AVDD
Portable Instrumentation
Closed-Loop Servo-Control
Process Control
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
DAC8564
Data Buffer A
DAC Register A
16-Bit DAC
VOUTA
Data Buffer B
DAC Register B
16-Bit DAC
VOUTB
Data Buffer C
DAC Register C
16-Bit DAC
VOUTC
Data Buffer D
DAC Register D
16-Bit DAC
VOUTD
Buffer
Control
Register
Control
SYNC
SCLK
24-Bit Shift Register
DIN
2.5V
Reference
Control Logic
GND
A0
A1
LDAC
ENABLE
Power-Down
Control Logic
VREF
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
DAC8564
www.ti.com
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
REFERENCE
DRIFT
(ppm/°C)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
DAC8564A
±12
±1
25
TSSOP-16
PW
–40°C to +105°C
D8564
DAC8564B
±8
±1
25
TSSOP-16
PW
–40°C to +105°C
D8564B
DAC8564C
±12
±1
5
TSSOP-16
PW
–40°C to +105°C
D8564
DAC8564D
±8
±1
5
TSSOP-16
PW
–40°C to +105°C
D8564D
(1)
PACKAGE
MARKING
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DAC8564
UNIT
–0.3 to +6
V
Digital input voltage to GND
–0.3 to +VDD + 0.3
V
VOUT to GND
–0.3 to +VDD + 0.3
V
VREF to GND
–0.3 to +VDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
+150
°C
(TJ max – TA)/θJA
W
Thermal impedance, θJA
+118
°C/W
Thermal impedance, θJC
+29
°C/W
Human body model (HBM)
4000
V
Charged device model (CDM)
1500
V
AVDD to GND
Junction temperature range (TJ max)
Power dissipation
ESD rating
(1)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8564
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC8564A, DAC8564C
±4
±12
LSB
DAC8564B, DAC8564D
±4
±8
LSB
±0.5
±1
LSB
±5
±8
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by the line
passing through
codes 485 and 64714
Differential nonlinearity
16-bit monotonic
Offset error
Offset error drift
Gain error
Gain temperature coefficient
PSRR
Power-supply rejection ratio
mV
µV/°C
±1
Measured by the line passing through codes 485 and
64714.
Full-scale error
Bits
±0.2
±0.5
% of FSR
±0.05
±0.2
% of FSR
AVDD = 5V
±1
AVDD = 2.7V
±2
ppm of
FSR/°C
1
mV/V
Output unloaded
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ,
0pF < CL < 200pF
8
RL = 2kΩ, CL = 500pF
V
10
µs
12
Slew rate
Capacitive load stability
VREF
2.2
RL = ∞
V/µs
470
pF
RL = 2kΩ
1000
Code change glitch impulse
1LSB change around major carry
0.15
nV-s
Digital feedthrough
SCLK toggling, SYNC high
0.15
nV-s
Channel-to-channel dc crosstalk
Full-scale swing on adjacent channel
0.25
LSB
Channel-to-channel ac crosstalk
1kHz full-scale sine wave, outputs unloaded
–100
dB
DC output impedance
At mid-code input
Short-circuit current
Power-up time
1
Ω
DAC at input code = 32768
50
mA
Coming out of power-down mode AVDD = 5V
2.5
Coming out of power-down mode AVDD = 3V
5
µs
AC PERFORMANCE (2)
SNR
90
dB
THD
–77
dB
78
dB
SFDR
TA = +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz.
First 19 harmonics removed for SNR calculation.
SINAD
DAC output noise density
TA = +25°C, at mid-code input, fOUT = 1kHz
DAC output noise
TA = +25°C, at mid-code input, 0.1Hz to 10Hz
77
dB
130
nV/√Hz
µVPP
6
REFERENCE
Internal reference current consumption
AVDD = 5.5V
360
µA
AVDD = 3.6V
348
µA
80
µA
External reference current
External VREF = 2.5V, if internal reference is disabled,
all four channels active
Reference input range VREFH voltage
VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V
0
AVDD
Reference input range VREFL voltage
VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V
0
AVDD/2
Reference input impedance
(1)
(2)
31
V
V
kΩ
Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
Ensured by design or characterization, not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8564
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE OUTPUT
Output voltage
TA = +25°C
2.4995
2.5
2.5005
V
Initial accuracy
TA = +25°C
–0.02
%
Output voltage temperature drift
Output voltage noise
±0.004
0.02
DAC8564A, DAC8564B (3)
5
25
DAC8564C, DAC8564D (4)
2
5
ppm/°C
µVPP
f = 0.1Hz to 10Hz
12
TA = +25°C, f = 1MHz, CL = 0µF
50
TA = +25°C, f = 1MHz, CL = 1µF
20
TA = +25°C, f = 1MHz, CL = 4µF
16
Load regulation, sourcing (5)
TA = +25°C
30
µV/mA
Load regulation, sinking (5)
TA = +25°C
15
µV/mA
Output voltage noise density
(high-frequency noise)
Output current load capability (6)
Line regulation
TA = +25°C
Long-term stability/drift (aging) (5)
TA = +25°C, time = 0 to 1900 hours
Thermal hysteresis (5)
First cycle
nV/√Hz
±20
mA
10
µV/V
50
ppm
100
Additional cycles
ppm
25
LOGIC INPUTS (6)
Input current
µA
±1
VINL
Logic input LOW voltage
VINH
Logic input HIGH voltage
2.7V ≤ IOVDD ≤ 5.5V
0.3 × IOVDD
1.8V ≤ IOVDD ≤ 2.7V
0.1 × IOVDD
2.7V ≤ IOVDD ≤ 5.5V
0.7 × IOVDD
1.8V ≤ IOVDD ≤ 2.7V
0.95 × IOVDD
V
V
Pin capacitance
3
pF
V
POWER REQUIREMENTS
AVDD
2.7
5.5
IOVDD
1.8
5.5
V
10
20
µA
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
1
1.55
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
0.95
1.5
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
1.3
3.5
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
0.5
2.5
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
5
8.5
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
2.9
5.4
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
6.5
19
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
1.5
9
IOIDD (6)
Normal mode
IDD (7)
All power-down modes
Normal mode
Power
Dissipation
(7)
All power-down modes
mA
µA
mW
µW
TEMPERATURE RANGE
Specified performance
(3)
(4)
(5)
(6)
(7)
4
–40
+105
°C
Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +120°C.
Explained in more detail in the Application Information section of this data sheet.
Ensured by design or characterization, not production tested.
Input code = 32768, reference current included, no load.
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PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
VOUTA
1
16
LDAC
VOUTB
2
15
ENABLE
VREFH/VREFOUT
3
14
A1
AVDD
4
13
A0
DAC8564
VREFL
5
12
IOVDD
GND
6
11
DIN
VOUTC
7
10
SCLK
VOUTD
8
9
SYNC
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
VOUTA
Analog output voltage from DAC A
2
VOUTB
Analog output voltage from DAC B
3
VREFH/
VREFOUT
Positive reference input / reference output 2.5V if internal reference used
4
AVDD
Power supply input, 2.7V to 5.5V
5
VREFL
Negative reference input
6
GND
Ground reference point for all circuitry on the part
7
VOUTC
Analog output voltage DAC C
8
VOUTD
Analog output voltage DAC D
9
SYNC
Level-triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes
low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8564. Schmitt-Trigger logic Input.
10
SCLK
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic Input.
11
DIN
12
IOVDD
13
A0
Address 0—sets device address; see Table 5.
14
A1
Address 1—sets device address; see Table 5.
15
ENABLE
16
LDAC
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic Input.
Digital input-output power supply
Active low, ENABLE low connects the SPI interface to the serial port
Load DACs; rising edge triggered, loads all DAC registers
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6
DB0
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LDAC
DIN
SYNC
SCLK
ENABLE
t8
1
t11
t4
DB23
t5
t6
t3
t1
t2
t10
24
t7
t13
t12
t14
t9
t15
DB23
SERIAL WRITE OPERATION
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TIMING REQUIREMENTS (1) (2)
At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8564
PARAMETER
TEST CONDITIONS
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
t11
ENABLE falling edge to SYNC falling edge
t12
24th SCLK falling edge to ENABLE rising edge
t13
24th SCLK falling edge to LDAC rising edge
t14
LDAC rising edge to ENABLE rising edge
t15
LDAC HIGH time
(1)
(2)
(3)
MIN
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
20
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
5
IOVDD = AVDD = 3.6V to 5.5V
5
IOVDD = AVDD = 2.7V to 3.6V
4.5
IOVDD = AVDD = 3.6V to 5.5V
4.5
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
130
IOVDD = AVDD = 3.6V to 5.5V
130
IOVDD = AVDD = 2.7V to 3.6V
15
IOVDD = AVDD = 3.6V to 5.5V
15
IOVDD = AVDD = 2.7V to 3.6V
15
IOVDD = AVDD = 3.6V to 5.5V
15
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
50
IOVDD = AVDD = 3.6V to 5.5V
50
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See the Serial Write Operation timing diagram.
Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: Internal Reference
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades A and B)
2.503
2.503
2.502
2.502
2.501
2.501
VREF (V)
VREF (V)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades C and D)
2.500
2.499
2.500
2.499
2.498
2.498
10 Units Shown
2.497
-40
-20
0
20
40
60
80
100
13 Units Shown
2.497
-40
120
-20
0
20
Temperature (°C)
40
60
80
100
120
Temperature (°C)
Figure 1.
Figure 2.
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°C, Grades C and D)
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°, Grades A and B)
40
30
Typ: 5ppm/°C
Max: 25ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
Population (%)
Population (%)
30
20
20
10
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
5.0
5
7
9
11
13
15
Temperature Drift (ppm/°C)
Figure 3.
Figure 4.
REFERENCE OUTPUT TEMPERATURE DRIFT
(0°C to +120°C, Grades C and D)
LONG-TERM
STABILITY/DRIFT (1)
40
17
19
200
Typ: 1.2ppm/°C
Max: 3ppm/°C
150
30
100
Drift (ppm)
Population (%)
3
Temperature Drift (ppm/°C)
20
10
50
0
-50
Average
-100
-150
-200
0.5
(1)
8
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
300
600
900
1200
Temperature Drift (ppm/°C)
Time (Hours)
Figure 5.
Figure 6.
1500
1800
1900
20 Units Shown
0
Explained in more detail in the Application Information section of this data sheet.
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TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY
vs FREQUENCY
INTERNAL REFERENCE NOISE
0.1Hz TO 10Hz
300
250
VNOISE (5mV/div)
VN (nV/ÖHz)
12mV (peak-to-peak)
200
Reference Unbuffered
CREF = 0mF
150
100
50
CREF = 4.8mF
0
10
100
1k
10k
100k
Time (2s/div)
1M
Frequency (Hz)
Figure 7.
Figure 8.
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades A and B)
2.505
2.505
2.504
2.504
2.503
2.503
2.502
+120°C
2.501
VREF (V)
VREF (V)
2.502
2.500
2.499
+25°C
2.498
2.501
+25°C
2.500
2.499
2.498
-40°C
2.497
+120°C
2.497
-40°C
2.496
2.496
2.495
-25
-20 -15 -10
0
-5
5
10
15
20
2.495
-25
25
-20 -15 -10
0
-5
ILOAD (mA)
5
10
15
20
25
ILOAD (mA)
Figure 9.
Figure 10.
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades A and B)
2.503
2.503
2.502
2.502
-40°C
+120°C
2.501
VREF (V)
VREF (V)
+120°C
2.500
2.501
+25°C
2.500
+25°C
2.499
2.499
2.498
2.498
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40°C
2.5
3.0
3.5
4.0
AVDD (V)
AVDD (V)
Figure 11.
Figure 12.
4.5
5.0
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
Channel A
VDD = 5.0V, Internal VREF = 4.99V
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
-0.5
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LE (LSB)
Digital Input Code
Channel C
VDD = 5.0V, Internal VREF = 4.99V
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
0
-0.5
Channel D
VDD = 5.0V, Internal VREF = 4.99V
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 15.
Figure 16.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
2
0
-2
-4
-6
Channel A
VDD = 5.0V, Internal VREF = 4.99V
LE (LSB)
0
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
0
57344 65536
DLE (LSB)
LE (LSB)
DLE (LSB)
6
4
2
0
-2
-4
-6
8192
-1.0
DLE (LSB)
Channel B
VDD = 5.0V, Internal VREF = 4.99V
-1.0
0
0
-0.5
-1.0
Channel B
VDD = 5.0V, Internal VREF = 4.99V
0
-0.5
-1.0
0
10
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 17.
Figure 18.
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57344 65536
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
Channel C
VDD = 5.0V, Internal VREF = 4.99V
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
0
-0.5
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 19.
Figure 20.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
6
4
2
0
-2
-4
-6
Channel A
VDD = 5.0V, Internal VREF = 4.99V
LE (LSB)
Digital Input Code
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
DLE (LSB)
8192
0
-0.5
-1.0
Channel B
VDD = 5.0V, Internal VREF = 4.99V
0
-0.5
-1.0
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 21.
Figure 22.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LE (LSB)
0
Channel C
VDD = 5.0V, Internal VREF = 4.99V
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
Channel D
VDD = 5.0V, Internal VREF = 4.99V
-1.0
0
DLE (LSB)
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
0
-0.5
-1.0
Channel D
VDD = 5.0V, Internal VREF = 4.99V
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 23.
Figure 24.
57344 65536
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
OFFSET ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
4
0.50
VDD = 5.0V
Internal VREF Enabled
VDD = 5.0V
Internal VREF Enabled
Full-Scale Error (mV)
Offset Error (mV)
3
Ch C
2
1
Ch D
Ch A
0.25
Ch C
Ch D
0
0
Ch B
Ch A
Ch B
-1
-40
-20
0
40
20
80
60
-0.25
-40
105
0
-20
Temperature (°C)
40
Figure 26.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
DAC Loaded with FFFFh
3.5
Analog Output Voltage (V)
4.5
VDD = 5V, Ch A
Internal Reference Enabled
2.5
1.5
0.5
105
DAC Loaded with FFFFh
4.5
3.5
VDD = 5V, Ch B
Internal Reference Enabled
2.5
1.5
0.5
DAC Loaded with 0000h
-0.5
-0.5
0
5
10
15
20
0
5
ISOURCE/SINK (mA)
10
15
20
ISOURCE/SINK (mA)
Figure 27.
Figure 28.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
5.5
5.5
DAC Loaded with FFFFh
4.5
3.5
Analog Output Voltage (V)
Analog Output Voltage (V)
80
5.5
DAC Loaded with 0000h
VDD = 5V, Ch C
Internal Reference Enabled
2.5
1.5
0.5
DAC Loaded with FFFFh
4.5
3.5
VDD = 5V, Ch D
Internal Reference Enabled
2.5
1.5
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
-0.5
-0.5
0
5
10
15
20
0
ISOURCE/SINK (mA)
5
10
15
20
ISOURCE/SINK (mA)
Figure 29.
12
60
Figure 25.
5.5
Analog Output Voltage (V)
20
Temperature (°C)
Figure 30.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1400
VDD = 5.5V
Internal VREF Included
1200
Power-Supply Current (mA)
Power-Supply Current (mA)
1300
1100
1000
900
800
0
VDD = 5.5V
Internal VREF Included
DAC Loaded with 8000h
1300
1200
1100
1000
900
800
-40
8192 16384 24576 32768 40960 49152 57344 65536
Figure 31.
Figure 32.
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE
80
105
5.1
5.5
1.2
VDD = 2.7V to 5.5V
Internal VREF Included
VDD = 2.7V to 5.5V
Internal VREF Included
DAC Loaded with 8000h
1090
1.0
1080
IDD (mA)
Power-Supply Current (mA)
60
40
Temperature (°C)
1100
1070
0.8
0.6
0.4
1060
0.2
1050
2.7
3.1
3.5
3.9
4.3
4.7
5.1
2.7
5.5
3.1
3.5
AVDD (V)
4.3
4.7
Figure 33.
Figure 34.
POWER-DOWN CURRENT
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
3200
VDD = IOVDD = 5.5V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
Power-Supply Current (mA)
VDD = 5.5V
1
0
-40
3.9
VDD (V)
2
Power-Down Current (mV)
20
0
-20
Digital Input Code
2800
2400
Sweep from
0V to 5.5V
2000
1600
Sweep from
5.5V to 0V
1200
800
-20
0
20
40
60
80
105
0
1
2
3
4
5
VLOGIC (V)
Temperature (°C)
Figure 35.
Figure 36.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
POWER-SUPPLY CURRENT
HISTOGRAM
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
60
VDD = 5.5V
Internal VREF Included
-50
-60
40
THD (dB)
Occurrence (%)
50
VDD = 5V, External VREF = 4.9V, Ch A
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
30
-70
THD
-80
20
3rd Harmonic
10
-90
0
-100
2nd Harmonic
950
1000
1050
1100
1150
0
1200
1
2
-40
Figure 38.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
5
VDD = 5V, External VREF = 4.9V, Ch C
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
-60
THD (dB)
-60
THD (dB)
4
Figure 37.
VDD = 5V, External VREF = 4.9V, Ch B
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
3
fOUT (kHz)
Power-Supply Current (mA)
THD
-70
2nd Harmonic
-70
THD
-80
-80
-90
-90
3rd Harmonic
3rd Harmonic
2nd Harmonic
-100
-100
0
1
2
4
3
5
0
1
2
3
fOUT (kHz)
fOUT (kHz)
Figure 39.
Figure 40.
4
5
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
VDD = 5V, External VREF = 4.9V, Ch D
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
THD (dB)
-60
-70
THD
2nd Harmonic
-80
-90
3rd Harmonic
-100
-110
0
1
2
3
4
5
fOUT (kHz)
Figure 41.
14
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
94
POWER SPECTRAL DENSITY
0
VDD = 5V, External VREF = 4.9V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
92
Gain (dB)
SNR (dB)
-40
Ch D
Ch A
90
Ch C
Ch B
88
VDD = 5V, External VREF = 4.9V
fOUT = 1kHz, fS = 225kSPS
Measurement Bandwidth = 20kHz
-20
-60
-80
-90
-120
86
-140
0
1
2
3
4
5
0
fOUT (kHz)
5
10
15
Figure 42.
Figure 43.
FULL-SCALE SETTLING TIME:
5V RISING EDGE
FULL-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: 0000h
To Code: FFFFh
Rising Edge
1V/div
20
Frequency (Hz)
Zoomed Rising Edge
1mV/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: FFFFh
To Code: 0000h
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 44.
Figure 45.
HALF-SCALE SETTLING TIME:
5V RISING EDGE
HALF-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: CFFFh
To Code: 4000h
Rising
Edge
1V/div
VDD = 5V
Ext VREF = 4.096V
From Code: 4000h
To Code: CFFFh
Zoomed Rising Edge
1mV/div
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 46.
Figure 47.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
VDD = 5V
Ext VREF = 4.096V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 48.
Figure 49.
GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 16LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
VDD = 5V
Ext VREF = 4.096V
From Code: 8010h
To Code: 8000h
Glitch: 0.08nV-s
VOUT (500mV/div)
VOUT (500mV/div)
Time (400ns/div)
Time (400ns/div)
Figure 50.
Figure 51.
GLITCH ENERGY:
5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 256LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
16
GLITCH ENERGY:
5V, 1LSB STEP, FALLING EDGE
VOUT (500mV/div)
VOUT (500mV/div)
GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 52.
Figure 53.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (1)
1200
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (2)
400
Internal Reference Enabled
No Load at VREFH/VREFOUT Pin
1000
DAC = Full-Scale
Internal Reference Enabled
4.8mF versus No Load at VREFH/VREFOUT Pin
350
Noise (nV/ÖHz)
Noise (nV/ÖHz)
300
800
600
Mid-Scale
400
Full Scale
250
200
No Load on Reference
150
100
Zero Scale
200
4.8mF Capacitor
On Reference
50
0
0
10
100
1k
10k
100k
1M
10
Frequency (Hz)
100
1k
10k
100k
1M
Frequency (Hz)
Figure 54.
Figure 55.
DAC OUTPUT NOISE
0.1Hz TO 10Hz
Noise (nV/ÖHz)
6mV (peak-to-peak)
DAC = Mid-Scale
Internal Reference Enabled
Frequency (Hz)
Figure 56.
(1)
(2)
Explained in more detail in the Application Information section of this data sheet.
See the Application Information section for more information.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 3.6V
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
vs TEMPERATURE
2400
1400
Power-Supply Current (mA)
VDD = IOVDD = 3.6V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
IDD (mA)
2000
1600
Sweep from 0V to 3.6V
1200
Sweep from
3.6V to 0V
800
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VDD = 2.7V
Internal VREF Included
DAC Loaded with 8000h
1200
1000
800
-40
4.0
-20
0
VLOGIC (V)
20
40
60
80
105
Temperature (°C)
Figure 57.
Figure 58.
POWER-SUPPLY CURRENT
HISTOGRAM
80
VDD = 3.6V
Internal VREF Included
Occurrence (%)
60
40
20
0
900
950
1000
1050
1100
1150
1200
Power-Supply Current (mA)
Figure 59.
18
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
Channel A
VDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
0
-0.5
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 60.
Figure 61.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LE (LSB)
Digital Input Code
Channel C
VDD = 2.7V, Internal VREF = 2.5V
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
DLE (LSB)
6
4
2
0
-2
-4
-6
8192
0
-0.5
-1.0
Channel D
VDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 62.
Figure 63.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
2
0
-2
-4
-6
Channel A
VDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
0
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
Channel B
VDD = 2.7V, Internal VREF = 2.5V
-1.0
0
DLE (LSB)
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
0
-0.5
-1.0
Channel B
VDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 64.
Figure 65.
57344 65536
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
Channel C
VDD = 2.7V, Internal VREF = 2.5V
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 66.
Figure 67.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
Channel A
VDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
Digital Input Code
6
4
2
0
-2
-4
-6
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
0
-0.5
Channel B
VDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 68.
Figure 69.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
6
4
2
0
-2
-4
-6
Channel C
VDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
0
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
0
-0.5
57344 65536
DLE (LSB)
LE (LSB)
DLE (LSB)
8192
-1.0
DLE (LSB)
Channel D
VDD = 2.7V, Internal VREF = 2.5V
-1.0
0
0
-0.5
-1.0
Channel D
VDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
0
20
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 70.
Figure 71.
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
OFFSET ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
4
0.50
VDD = 2.7V
Internal VREF Enabled
Ch C
Full-Scale Error (mV)
Offset Error (mV)
3
VDD = 2.7V
Internal VREF Enabled
2
1
Ch D
Ch B
0.25
Ch C
Ch D
0
0
-1
-40
Ch A
0
-20
40
20
80
60
-0.25
-40
105
0
-20
Temperature (°C)
20
40
Figure 72.
Figure 73.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
80
105
3.0
DAC Loaded with FFFFh
DAC Loaded with FFFFh
2.5
2.0
Analog Output Voltage (V)
Analog Output Voltage (V)
60
Temperature (°C)
3.0
VDD = 2.7V, Ch A
Internal Reference Enabled
1.5
1.0
0.5
2.5
2.0
VDD = 2.7V, Ch B
Internal Reference Enabled
1.5
1.0
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
0
0
0
5
10
15
20
0
5
10
15
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 74.
Figure 75.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
3.0
20
3.0
DAC Loaded with FFFFh
DAC Loaded with FFFFh
2.5
2.0
Analog Output Voltage (V)
Analog Output Voltage (V)
Ch B
Ch A
VDD = 2.7V, Ch C
Internal Reference Enabled
1.5
1.0
0.5
2.5
2.0
VDD = 2.7V, Ch D
Internal Reference Enabled
1.5
1.0
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
0
0
0
5
10
15
20
0
5
10
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 76.
Figure 77.
15
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
1600
VDD = 2.7V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
VDD = 2.7V
Internal VREF Included
1200
Power-Supply Current (mA)
Power-Supply Current (mA)
1300
1100
1000
900
1400
1200
Sweep from 0V to 2.7V
Sweep from
2.7V to 0V
1000
800
800
0
8192 16384 24576 32768 40960 49152 57344 65536
0
0.5
1.0
1.5
2.0
2.5
3.0
VLOGIC (V)
Digital Input Code
Figure 78.
Figure 79.
FULL-SCALE SETTLING TIME:
2.7V RISING EDGE
FULL-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: FFFFh
To Code: 0000h
Rising
Edge
0.5V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: 0000h
To Code: FFFFh
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 80.
Figure 81.
HALF-SCALE SETTLING TIME:
2.7V RISING EDGE
HALF-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: CFFFh
To Code: 4000h
VDD = 2.7V
Int VREF = 2.5V
From Code: 4000h
To Code: CFFFh
Rising
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Time (2ms/div)
Figure 82.
22
Zoomed Falling Edge
1mV/div
Figure 83.
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Figure 84.
Figure 85.
GLITCH ENERGY:
2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 16LSB STEP, FALLING EDGE
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
VOUT (200mV/div)
Time (400ns/div)
VDD = 2.7V
Int VREF = 2.5V
From Code: 8010h
To Code: 8000h
Glitch: 0.12nV-s
Time (400ns/div)
Time (400ns/div)
Figure 86.
Figure 87.
GLITCH ENERGY:
2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 256LSB STEP, FALLING EDGE
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
GLITCH ENERGY:
2.7V, 1LSB STEP, FALLING EDGE
VOUT (200mV/div)
VDD = 2.7V
Int VREF = 2.5V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
VOUT (200mV/div)
VOUT (200mV/div)
GLITCH ENERGY:
2.7V, 1LSB STEP, RISING EDGE
VDD = 2.7V
Int VREF = 2.5V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 88.
Figure 89.
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs TEMPERATURE
POWER-DOWN CURRENT
vs TEMPERATURE
1.5
VDD = 2.7V
VDD = 2.7V
Internal VREF = 2.5V
DAC Loaded with 8000h
Power-Down Current (mA)
Power-Supply Current (mA)
1400
1200
1000
800
-40
0
40
80
100
1.0
0.5
0
-40
Temperature (°C)
0
20
40
60
80
105
Temperature (°C)
Figure 90.
24
-20
Figure 91.
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THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
VREF
The DAC8564 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 92
shows a block diagram of the DAC architecture.
VREFH
50kW
RDIVIDER
VREF
2
50kW
R
62kW
DAC
Register
VOUTX
REF(+)
Resistor String
REF(-)
To Output Amplifier
(2x Gain)
R
VREFL
Figure 92. DAC8564 Architecture
The input coding to the DAC8564 is straight binary,
so the ideal output voltage is given by Equation 1.
DIN
V OUTX + 2 V REFL ) (V REFH * V REFL)
65536 (1)
R
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535. X represents channel A, B, C, or D.
R
RESISTOR STRING
The resistor string section is shown in Figure 93. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
Figure 93. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to AVDD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 2.2V/µs,
with a full-scale settling time of 8µs with the output
unloaded.
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INTERNAL REFERENCE
VREF
The DAC8564 includes a 2.5V internal reference that
is enabled by default. The internal reference is
externally available at the VREFH / VREFOUT pin. A
minimum 100nF capacitor is recommended between
the reference output and GND for noise filtering.
Reference
Disable
The internal reference of the DAC8564 is a bipolar
transistor-based,
precision
bandgap
voltage
reference. Figure 94 shows the basic bandgap
topology. Transistors Q1 and Q2 are biased such that
the current density of Q1 is greater than that of Q2.
The difference of the two base-emitter voltages
(VBE1 – VBE2) has a positive temperature coefficient
and is forced across resistor R1. This voltage is
gained up and added to the base-emitter voltage of
Q2, which has a negative temperature coefficient. The
resulting output voltage is virtually independent of
temperature. The short-circuit current is limited by
design to approximately 100mA.
Enable/Disable Internal Reference
The internal reference in the DAC8564 is enabled by
default and operates in automatic mode; however, the
reference can be disabled for debugging, evaluation
purposes, or when using an external reference. A
serial command that requires a 24-bit write sequence
(see the Serial Interface section) must be used to
disable the internal reference, as shown in Table 1.
During the time that the internal reference is disabled,
the DAC functions normally using an external
reference. At this point, the internal reference is
disconnected from the VREF pin (3-state output). Do
not attempt to drive the VREF pin externally and
internally at the same time indefinitely.
Q1
1
N
Q2
R1
R2
Figure 94. Simplified Schematic of the Bandgap
Reference
To then enable the internal reference, either perform
a power-cycle to reset the device, or write the 24-bit
serial command shown in Table 2. These actions put
the internal reference back into the default mode. In
the default mode, the internal reference powers down
automatically when all DACs power down in any of
the power-down modes (see the Power-Down Modes
section); the internal reference powers up
automatically when any DAC is powered up.
The DAC8564 also provides the option of keeping the
internal reference powered on all the time, regardless
of the DAC(s) state (powered up or down). To keep
the internal reference powered on, regardless of the
DAC(s) state, write the 24-bit serial command shown
in Table 3.
Table 1. Write Sequence for Disabling Internal Reference
(internal reference always powered down—012000h)
DB23
0
DB16
0
0
0
0
0
0
1
DB13
0
0
1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2. Write Sequence for Enabling Internal Reference
(internal reference powered up to default mode—010000h)
DB23
0
DB16
0
0
0
0
0
0
1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 3. Write Sequence for Enabling Internal Reference
(internal reference always powered up—011000h)
DB23
0
26
DB16
0
0
0
0
0
0
1
DB12
0
0
0
1
DB0
0
0
0
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0
0
0
0
0
0
0
0
0
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SERIAL INTERFACE
IOVDD AND VOLTAGE TRANSLATORS
The DAC8564 has a 3-wire serial interface (SYNC,
SCLK, and DIN) compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram for an
example of a typical write sequence.
The IOVDD pin powers the the digital input structures
of the DAC8564. For single-supply operation, it can
be tied to AVDD. For dual-supply operation, the IOVDD
pin provides interface flexibility with various CMOS
logic families and should be connected to the logic
supply of the system. Analog circuits and internal
logic of the DAC8564 use AVDD as the supply
voltage. The external logic high inputs translate to
AVDD by level shifters. These level shifters use the
IOVDD voltage as a reference to shift the incoming
logic HIGH levels to AVDD. IOVDD is ensured to
operate from 2.7V to 5.5V regardless of the AVDD
voltage, assuring compatibility with various logic
families. Although specified down to 2.7V, IOVDD
operates at as low as 1.8V with degraded timing and
temperature performance. For lowest power
consumption, logic VIH levels should be as close as
possible to IOVDD, and logic VIL levels should be as
close as possible to GND voltages.
The write sequence begins by bringing the SYNC line
low. Data from the DIN line are clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
the DAC8564 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked into the shift register and the shift
register locks. Further clocking does not change the
shift register data. Once 24 bits are locked into the
shift register, the eight MSBs are used as control bits
and the 16 LSBs are used as data. After receiving the
24th falling clock edge, the DAC8564 decodes the
eight control bits and 16 data bits to perform the
required function, without waiting for a SYNC rising
edge. A new write sequence starts at the next falling
edge of SYNC. A rising edge of SYNC before the
24-bit sequence is complete resets the SPI interface;
no data transfer occurs. After the 24th falling edge of
SCLK is received, the SYNC line may be kept LOW
or brought HIGH. In either case, the minimum delay
time from the 24th falling SCLK edge to the next
falling SYNC edge must be met in order to properly
begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that
the levels are as close to each rail as possible. (Refer
to the Typical Characteristics section for Figure 36,
Figure 57, and Figure 79 (Supply Current vs Logic
Input Voltage).
INPUT SHIFT REGISTER
The input shift register (SR) of the DAC8564 is 24
bits wide, as shown in Table 4, and consists of eight
control bits (DB23 and DB22) and 16 data bits (DB15
to DB0). The first two control bits (DB23 and DB22)
are the address match bits. The DAC8564 offers
hardware-enabled addressing capability, allowing a
single host to talk to up to four DAC8564s through a
single SPI bus without any glue logic, enabling up to
16-channel operation. The state of DB23 should
match the state of pin A1; similarly, the state of DB22
should match the state of pin A0. If there is no match,
the control command and the data (DB21...DB0) are
ignored by the DAC8564. That is, if there is no
match, the DAC8564 is not addressed. Address
matching can be overridden by the broadcast update.
Table 4. Data Input Register Format
DB23
A1
DB12
A0
LD1
LD0
0
DAC Select 1
DAC Select 0
PD0
D15
D14
D13
DB11
D11
D12
DB0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
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LD1 (DB21) and LD0 (DB20) control the loading of
each analog output with the specified 16-bit data
value or power-down command. Bit DB19 must
always be '0'. The DAC channel select bits (DB18,
DB17) control the destination of the data (or
power-down command) from DAC A through DAC D.
The final control bit, PD0 (DB16), selects the
power-down mode of the DAC8564 channels as well
as the power-down mode of the internal reference.
DB21 = 0 and DB20 = 1: Single-channel update.
The data buffer and DAC register corresponding to a
DAC selected by DB18 and DB17 update with the
contents of SR data (or power-down).
The DAC8564 supports a number of different load
commands. The load commands include broadcast
commands to address all the DAC8564s on an SPI
bus. The load commands are summarized as follows:
DB21 = 1 and DB20 = 1: Broadcast update. All the
DAC8564s on the SPI bus respond, regardless of
address matching. If DB18 = 0, SR data are ignored
and any channels from all DAC8564s update with
previously stored data (or power-down). If DB18 = 1,
SR data (or power-down) update any channels of all
DAC8564s in the system. This broadcast update
feature allows the simultaneous update of up to 16
channels.
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 updates with
the SR data; simultaneously, all the other channels
update with previously stored data (or power-down)
from data buffers.
DB21 = 0 and DB20 = 0: Single-channel store. The
data buffer corresponding to a DAC selected by
DB18 and DB17 updates with the contents of SR
data (or power-down).
Refer to Table 5 for more information.
Table 5. Control Matrix for the DAC8564
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13-DB0
A1
A0
LD 1
LD 0
0
DAC Sel 1
DAC Sel 0
PD0
MSB
MSB-1
MSB-2...LSB
(Address Select)
0/1
DESCRIPTION
0/1
This address selects 1 of 4 possible devices on a
single SPI data bus based on each device's address
pin(s) state.
See Below
A0 and A1 should
correspond to the
package address
set via pins 13
and 14
0
0
0
0
0
0
Data
Write to buffer A with data
0
0
0
0
1
0
Data
Write to buffer B with data
0
0
0
1
0
0
Data
Write to buffer C with data
0
0
0
1
1
0
Data
0
0
0
(00, 01, 10, or 11)
1
0
1
0
(00, 01, 10, or 11)
0
0
1
0
(00, 01, 10, or 11)
1
1
0
0
(00, 01, 10, or 11)
0
1
0
0
(00, 01, 10, or 11)
1
See Table 6
Write to buffer D with data
0
Write to buffer with data and load DAC (selected by
DB17 and DB18)
Data
See Table 6
0
Write to buffer with power-down command and load
DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and DB18)
and then load all DACs simultaneously from their
corresponding buffers
Data
See Table 6
Write to buffer (selected by DB17 and DB18) with
power-down command
0
Write to buffer with power-down command (selected by
DB17 and DB18) and then load all DACs
simultaneously from their corresponding buffers
Broadcast Modes
28
X
X
1
1
0
0
X
X
X
X
1
1
0
1
X
0
X
X
1
1
0
1
X
1
Simultaneously update all channels of all DAC8554
devices in the system with data stored in each
channels data buffer
X
Data
See Table 6
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Write to all devices and load all DACs with SR data
0
Write to all devices and load all DACs with power-down
command in SR
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SYNC INTERRUPT
LDAC FUNCTIONALITY
In a normal write sequence, the SYNC line stays low
for at least 24 falling edges of SCLK and the
addressed DAC register updates on the 24th falling
edge. However, if SYNC is brought high before the
24th falling edge, it acts as an interrupt to the write
sequence; the shift register resets and the write
sequence is discarded. Neither an update of the data
buffer contents, DAC register contents, nor a change
in the operating mode occurs (as shown in
Figure 95).
The DAC8564 offers both a software and hardware
simultaneous
update
function.
The
DAC
double-buffered architecture has been designed so
that new data can be entered for each DAC without
disturbing the analog outputs.
POWER-ON RESET TO ZERO-SCALE
The DAC8564 contains a power-on reset circuit that
controls the output voltage during power-up. On
power-up, the DAC registers are filled with zeros and
the output voltages are set to zero-scale; they remain
that way until a valid write sequence and load
command are made to the respective DAC channel.
The power-on reset is useful in applications where it
is important to know the state of the output of each
DAC while the device is in the process of powering
up. No device pin should be brought high before
power is applied to the device. The internal reference
is powered on by default and remains that way until a
valid reference-change command is executed.
DAC8564 data updates are synchronized with the
falling edge of the 24th SCLK cycle, which follows a
falling edge of SYNC. For such synchronous updates,
the LDAC pin is not required and it must be
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
asynchronous DAC updates. To do an LDAC
operation, single-channel store(s) should be done
(loading DAC buffers) by setting LD0 and LD1 to '0'.
Multiple single-channel updates can be done in order
to set different channel buffers to desired values and
then make a rising edge on LDAC. Data buffers of all
channels must be loaded with desired data before an
LDAC rising edge. After a low-to-high LDAC
transition, all DACs are simultaneously updated with
the contents of the corresponding data buffers. If the
contents of a data buffer are not changed by the
serial interface, the corresponding DAC output
remains unchanged after the LDAC trigger.
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB0
DB23
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
DB0
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 95. SYNC Interrupt Facility
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ENABLE PIN
For normal operation, the enable pin must be driven
to a logic low. If the enable pin is driven high, the
DAC8564 stops listening to the serial port. However,
SCLK, SYNC, and DIN must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
POWER-DOWN MODES
The DAC8564 has two separate sets of power-down
commands. One set is for the DAC channels and the
other set is for the internal reference. For more
information on powering down the reference, see the
Enable/Disable Internal Reference section.
DAC Power-Down Commands
The DAC8564 uses four modes of operation. These
modes are accessed by setting three bits (PD2, PD1,
and PD0) in the shift register. Table 6 shows how to
control the operating mode with data bits PD0
(DB16), PD1 (DB15), and PD2 (DB14).
Table 6. DAC Operating Modes
PD0
(DB16)
PD1
(DB15)
PD2
(DB14)
0
X
X
Normal operation
1
0
1
Output typically 1kΩ to GND
1
1
0
Output typically 100 kΩ to GND
1
1
1
Output high-impedance
The advantage of this switching is that the output
impedance of the device is known while it is in
power-down mode. As described in Table 6, there are
three different power-down options. VOUT can be
connected internally to GND through a 1kΩ resistor, a
100kΩ resistor, or open circuited (High-Z). The output
stage is shown in Figure 96. In other words, DB16,
DB15, and DB14 = '111' represent a power-down
condition with Hi-Z output impedance for a selected
channel. '101' represents a power-down condition
with 1kΩ output impedance, and '110' represents a
power-down condition with 100kΩ output impedance.
Resistor
String
DAC
Amplifier
VOUTX
DAC OPERATING MODES
The DAC8564 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a power-down
condition to all the DAC8564s in a system; it is also
possible to simultaneously power-down a channel
while updating data on other channels.
When the PD0 bit is set to '0', the device works
normally with its typical current consumption of 1mA
30
at 5.5V with an input code = 32768. The reference
current is included with the operation of all four
DACs. However, for the three power-down modes,
the supply current falls to 1.3µA at 5.5V (0.5µA at
3.6V). Not only does the supply current fall, but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values.
Power-Down
Circuitry
Resistor
Network
Figure 96. Output Stage During Power-Down
All analog channel circuitries are shut down when the
power-down mode is exercised. However, the
contents of the DAC register are unaffected when in
power down. The time required to exit power-down is
typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V.
See the Typical Characteristics for more information.
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OPERATION EXAMPLES: DAC8564
For the following examples, ensure that DAC pins A0 and A1 are both connected to ground. Pins A0 and A1
must always match data bits DB22 and DB23 within the SPI write sequence/protocol. X = Don't care. Value can
be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
• 1st: Write to data buffer A:
•
•
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
DB11–DB0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
DB11–DB0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
DB11–DB0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
DB11–DB0
2nd: Write to data buffer B:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
3rd: Write to data buffer C:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
4th: Write to data buffer D and simultaneously update all DACs:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
• 1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
•
•
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
D11–DB0
2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
D11–DB0
3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
D11–DB0
4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
D11–DB0
After completion of each write cycle, DAC analog output settles to the voltage specified.
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Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ
Simultaneously
• 1st: Write power-down command to data buffer A: DAC A to 1kΩ.
•
•
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
1
X
X
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
1
X
X
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
0
X
X
X
2nd: Write power-down command to data buffer B: DAC B to 1kΩ.
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
3rd: Write power-down command to data buffer C: DAC C to 100kΩ.
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
4th: Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
0
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
• 1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
•
•
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
32
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Example 5: Power-Down All Channels Simultaneously while Reference is Always Powered Up
• 1st: Write sequence for enabling the DAC8564 internal reference all the time:
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
0
0
1
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
2nd: Write sequence to power-down all DACs to high-impedance:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first and second write sequences, respectively.
Example 6: Write a Specific Value to All DACs while Reference is Always Powered Down
• 1st: Write sequence for disabling the DAC8564 internal reference all the time (after this sequence, the
DAC8564 requires an external reference source to function):
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
0
1
0
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
DB11–DB0
2nd: Write sequence to write specified data to all DACs:
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the fourth write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling
edge of the fourth write cycle). Reference is always powered-down.
Example 7: Write a Specific Value to DAC A, while Reference is Placed in Default Mode and All Other
DACs are Powered Down to High-Impedance
• 1st: Write sequence for placing the DAC8564 internal reference into default mode. Alternately, this step can
be replaced by performing a power-on reset (see the Power-On Reset section):
•
•
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
0
0
0
X
2nd: Write sequence to power-down all DACs to high-impedance (after this sequence, the DAC8564 internal
reference powers down automatically):
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
3rd: Write sequence to power-up DAC A to a specified value (after this sequence, the DAC8564 internal
reference powers up automatically):
A1
A0
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
DB15
DB14
DB13
DB12
DB11–DB0
The DAC B, DAC C, and DAC D analog outputs simultaneously power-down to high-impedance, and DAC A
settles to the specified value upon completion.
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APPLICATION INFORMATION
INTERNAL REFERENCE
The internal reference of the DAC8564 does not
require an external load capacitor for stability
because it is stable with any capacitive load.
However, for improved noise performance, an
external load capacitor of 150nF or larger connected
to the VREFH/VREFOUT output is recommended.
Figure 97 shows the typical connections required for
operation of the DAC8564 internal reference. A
supply bypass capacitor at the AVDD input is also
recommended.
DAC8564
AVDD
1
VOUTA
LDAC 16
2
VOUTB
ENABLE 15
3
VREFH/VREFOUT
A1 14
4
AVDD
A0 13
5
VREFL
6
GND
7
VOUTC
SCLK 10
8
VOUTD
SYNC
IOVDD 12
DIN 11
9
Temperature Drift
The internal reference is designed to exhibit minimal
drift error, defined as the change in reference output
voltage over varying temperature. The drift is
calculated using the box method described by
Equation 2:
Drift Error =
VREF_MAX - VREF_MIN
VREF ´ TRANGE
6
´ 10 (ppm/°C)
(2)
Where:
VREF_MAX = maximum reference voltage observed
within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed
within temperature range TRANGE.
VREF = 2.5V, target value for reference output
voltage.
The internal reference (grades C and D) features an
exceptional typical drift coefficient of 2ppm/°C from
–40°C to +120°C. Characterizing a large number of
units, a maximum drift coefficient of 5ppm/°C (grades
C and D) is observed. Temperature drift results are
summarized in the Typical Characteristics.
Noise Performance
Figure 97. Typical Connections for Operating the
DAC8564 Internal Reference
Supply Voltage
The internal reference features an extremely low
dropout voltage. It can be operated with a supply of
only 5mV above the reference output voltage in an
unloaded condition. For loaded conditions, refer to
the Load Regulation section. The stability of the
internal reference with variations in supply voltage
(line regulation, dc PSRR) is also exceptional. Within
the specified supply voltage range of 2.7V to 5.5V,
the variation at VREFH/VREFOUT is less than 10µV/V;
see the Typical Characteristics.
34
Typical 0.1Hz to 10Hz voltage noise can be seen in
Figure 8, Internal Reference Noise. Additional filtering
can be used to improve output noise levels, although
care should be taken to ensure the output impedance
does not degrade the ac performance. The output
noise spectrum at VREFH/VREFOUT without any
external components is depicted in Figure 7, Internal
Reference Noise Density vs Frequency. Another
noise density spectrum is also shown in Figure 7.
This spectrum was obtained using a 4.8µF load
capacitor at VREFH/VREFOUT for noise filtering.
Internal reference noise impacts the DAC output
noise; see the DAC Noise Performance section for
more details.
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Load Regulation
Thermal Hysteresis
Load regulation is defined as the change in reference
output voltage as a result of changes in load current.
The load regulation of the internal reference is
measured using force and sense contacts as shown
in Figure 98. The force and sense lines reduce the
impact of contact and trace resistance, resulting in
accurate measurement of the load regulation
contributed solely by the internal reference.
Measurement results are summarized in the Typical
Characteristics. Force and sense lines should be
used for applications that require improved load
regulation.
Thermal hysteresis for a reference is defined as the
change in output voltage after operating the device at
+25°C, cycling the device through the specified
temperature range, and returning to +25°C.
Hysteresis is expressed by Equation 3:
Output Pin
Contact and
Trace Resistance
VOUT
Force Line
IL
Sense Line
Meter
VHYST =
|VREF_PRE - VREF_POST|
VREF_NOM
6
´ 10 (ppm/°C)
(3)
Where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at +25°C
pre-temperature cycling.
VREF_POST = output voltage measured after the
device cycles through the temperature range of
–40°C to +120°C, and returns to +25°C.
DAC NOISE PERFORMANCE
Load
Figure 98. Accurate Load Regulation of the
DAC8564 Internal Reference
Long-Term Stability
Long-term stability/aging refers to the change of the
output voltage of a reference over a period of months
or years. This effect lessens as time progresses (see
Figure 26, the typical long-term stability curve). The
typical drift value for the internal reference is 50ppm
from 0 hours to 1900 hours. This parameter is
characterized by powering-up and measuring 20 units
at regular intervals for a period of 1900 hours.
Typical noise performance for the DAC8564 with the
internal reference enabled is shown in Figure 54 to
Figure 56. Output noise spectral density at the VOUT
pin versus frequency is depicted in Figure 54 for
full-scale, mid-scale, and zero-scale input codes. The
typical noise density for mid-scale code is 130nV/√Hz
at 1kHz and 100nV/√Hz at 1MHz. High-frequency
noise can be improved by filtering the reference noise
as shown in Figure 55, where a 4µF load capacitor is
connected to the VREFH/VREFOUT pin and compared
to the no-load condition. Integrated output noise
between 0.1Hz and 10Hz is close to 6µVPP
(mid-scale), as shown in Figure 56.
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BIPOLAR OPERATION USING THE DAC8564
The DAC8564 is designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in either Figure 99 or Figure 100.
The circuit shown gives an output voltage range of
±VREF. Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
The output voltage for any input code can be
calculated with Equation 4:
VO =
VREF ´
D
65536
´
R 1 + R2
R1
- VREF ´
V
REF
H
AV
R2
10kW
DD
OPA703
AVDD
0.1mF
VREFH
-6V
GND
3-Wire
Serial Interface
R1
Figure 99. Bipolar Output Range Using External
Reference at 5V
where D represents the input code in decimal
(0–65535).
R2
10kW
AV
With VREFH = 5V, R1 = R2 = 10kΩ.
10 ´ D
65536
±5V
VOUT
VREFH DAC8564
10mF
R2
(4)
VO =
+6V
R1
10kW
DD
+6V
R1
10kW
- 5V
(5)
This result has an output voltage range of ±5V with
0000h corresponding to a –5V output and FFFFh
corresponding to a +5V output, as shown in
Figure 99. Similarly, using the internal reference, a
±2.5V output voltage range can be achieved, as
shown in Figure 100.
OPA703
AVDD
VREF
150nF
±2.5V
VOUT
DAC8564
VREFL
GND
-6V
3-Wire
Serial Interface
Figure 100. Bipolar Output Range Using Internal
Reference
36
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MICROPROCESSOR INTERFACING
Microwire(1)
DAC8564(1)
DAC8564 to an 8051 Interface
CS
SYNC
Figure 101 shows a serial interface between the
DAC8564 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8564, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051; in this case, port line P3.3 is used. When
data are to be transmitted to the DAC8564, P3.3 is
taken low. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken high following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8564 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
take this requirement into account, and mirror the
data as needed.
SK
SCLK
SO
DIN
80C51/80L51(1)
DAC8564(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 101. DAC8564 to 80C51/80L51 Interface
DAC8564 to Microwire Interface
Figure 102 shows an interface between the DAC8564
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
are clocked into the DAC8564 on the rising edge of
the SK signal.
NOTE: (1) Additional pins omitted for clarity.
Figure 102. DAC8564 to Microwire Interface
DAC8564 to 68HC11 Interface
Figure 103 shows a serial interface between the
DAC8564 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8564, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal derives from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
DAC8564(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 103. DAC8564 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8564, PC7 is left low after the first eight bits are
transferred; then, a second and third serial write
operation are performed to the DAC. PC7 is taken
high at the end of this procedure.
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LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8564 offers single-supply operation, and is
often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
As a result of the single ground pin of the DAC8564,
all return currents (including digital and analog return
currents for the DAC) must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
38
The power applied to VDD should be well-regulated
and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
As with the GND connection, VDD should be
connected to a power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1µF to 10µF capacitor and 0.1µF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the supply and
remove the high-frequency noise.
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PARAMETER DEFINITIONS
With the increased complexity of many different specifications listed in product data sheets, this section
summarizes selected specifications related to digital-to-analog converters.
STATIC PERFORMANCE
Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity
(INL). Those are dc specifications and provide information on the accuracy of the DAC. They are most important
in applications where the signal is slowly changing and accuracy is required.
Resolution
Full-Scale Error
Generally, the DAC resolution can be expressed in
different forms. Specifications such as IEC 60748-4
recognize the numerical, analog, and relative
resolution. The numerical resolution is defined as the
number of digits in the chosen numbering system
necessary to express the total number of steps of the
transfer characteristic, where a step represents both
a digital input code and the corresponding discrete
analogue output value. The most commonly-used
definition of resolution provided in data sheets is the
numerical resolution expressed in bits.
Full-scale error is defined as the deviation of the real
full-scale output voltage from the ideal output voltage
while the DAC register is loaded with the full-scale
code (0xFFFF). Ideally, the output should be VDD – 1
LSB. The full-scale error is expressed in percent of
full-scale range (%FSR).
Least Significant Bit (LSB)
The least significant bit (LSB) is defined as the
smallest value in a binary coded system. The value of
the LSB can be calculated by dividing the full-scale
output voltage by 2n, where n is the resolution of the
converter.
Offset Error
The offset error is defined as the difference between
actual output voltage and the ideal output voltage in
the linear region of the transfer function. This
difference is calculated by using a straight line
defined by two codes (code 485 and 64714). Since
the offset error is defined by a straight line, it can
have a negative or positve value. Offset error is
measured in mV.
Zero-Code Error
The most significant bit (MSB) is defined as the
largest value in a binary coded system. The value of
the MSB can be calculated by dividing the full-scale
output voltage by 2. Its value is one-half of full-scale.
The zero-code error is defined as the DAC output
voltage, when all '0's are loaded into the DAC
register. Zero-scale error is a measure of the
difference between actual output voltage and ideal
output voltage (0V). It is expressed in mV. It is
primarily caused by offsets in the output amplifier.
Relative Accuracy or Integral Nonlinearity (INL)
Gain Error
Relative accuracy or integral nonlinearity (INL) is
defined as the maximum deviation between the real
transfer function and a straight line passing through
the endpoints of the ideal DAC transfer function. DNL
is measured in LSBs.
Gain error is defined as the deviation in the slope of
the real DAC transfer characteristic from the ideal
transfer function. Gain error is expressed as a
percentage of full-scale range (%FSR).
Most Significant Bit (MSB)
Full-Scale Error Drift
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is defined as the
maximum deviation of the real LSB step from the
ideal 1LSB step. Ideally, any two adjacent digital
codes correspond to output analog voltages that are
exactly one LSB apart. If the DNL is less than 1LSB,
the DAC is said to be monotonic.
Full-scale error drift is defined as the change in
full-scale error with a change in temperature.
Full-scale error drift is expressed in units of
%FSR/°C.
Offset Error Drift
Offset error drift is defined as the change in offset
error with a change in temperature. Offset error drift
is expressed in µV/°C.
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SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
Zero-Code Error Drift
Power-Supply Rejection Ratio (PSRR)
Zero-code error drift is defined as the change in
zero-code error with a change in temperature.
Zero-code error drift is expressed in µV/°C.
Power-supply rejection ratio (PSRR) is defined as the
ratio of change in output voltage to a change in
supply voltage for a full-scale output of the DAC. The
PSRR of a device indicates how the output of the
DAC is affected by changes in the supply voltage.
PSRR is measured in decibels (dB).
Gain Temperature Coefficient
The gain temperature coefficient is defined as the
change in gain error with changes in temperature.
The gain temperature coefficient is expressed in ppm
of FSR/°C.
Monotonicity
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output
changes in the same direction or remains at least
constant for each step increase (or decrease) in the
input code.
DYNAMIC PERFORMANCE
Dynamic performance parameters are specifications such as settling time or slew rate. Those are important in
applications where the signal is rapidly changing and/or high frequency signals are present.
Slew Rate
Channel-to-Channel DC Crosstalk
The output slew-rate (SR) of an amplifier or other
electronic circuit is defined as the maximum rate of
change of the output voltage for all possible input
signals.
Channel-to-channel dc crosstalk is defined as the dc
change in the output level of one DAC channel in
response to a change in the output of another DAC
channel. It is measured with a full-scale output
change on one DAC channel while monitoring
another DAC channel remains at mid-scale. It is
expressed in LSB.
SR = max
DVOUT(t)
Dt
Where ΔVOUT(t) is the output produced by the
amplifier as a function of time t.
Output Voltage Settling Time
Settling time is the total time (including slew time) for
the DAC output to settle within an error band around
its final value after a change in input. Settling times
are specified to within ±0.003% (or whatever value is
specified) of full-scale range (FSR).
Code Change/Digital-to-Analog Glitch Energy
Channel-to-Channel AC Crosstalk
AC crosstalk in multi-channel DAC is defined as
amount of ac interference experienced on the output
of a channel at a frequency (f) (and its harmonics),
when the output of an adjacent channel changes its
value at the rate of frequency (f). It is measured with
one channel output oscillating with sine wave of 1KHz
frequency while monitoring amplitude of 1KHz
harmonics on an adjacent DAC channel output (kept
at zero scale). It is expressed in dB.
Digital-to-analog glitch impulse is the impulse injected
into the analog output when the input code in the
DAC register changes state. It is normally specified
as the area of the glitch in nanovolts-second (nV-s),
and is measured when the digital input code is
changed by 1LSB at the major carry transition
(0x7FFF to 0x8000).
Signal-to-Noise Ratio (SNR)
Digital Feedthrough
Total Harmonic Distortion (THD)
Digital feedthrough is defined as impulse seen at the
output of the DAC from the digital inputs of the DAC.
It is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale
code change on the data bus; that is, from all '0's to
all '1's and vice versa.
Total harmonic distortion + noise is defined as the
ratio of the RMS values of the harmonics and noise
to the value of the fundamental frequency. It is
expressed in a percentage of the fundamental
frequency amplitude at sampling rate fS.
40
Signal-to-noise ratio (SNR) is defined as the ratio of
root mean-squared (RMS) value of the output signal
divided by the RMS values of the sum of all other
spectral components below one-half the output
frequency, not including harmonics or dc. SNR is
measured in dB.
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Spurious-Free Dynamic Range (SFDR)
DAC Output Noise Density
Spurious-free dynamic range (SFDR) is the usable
dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is
the measure of the difference in amplitude between
the fundamental and the largest harmonically or
non-harmonically related spur from dc to the full
Nyquist bandwidth (half the DAC sampling rate, or
fS/2). A spur is any frequency bin on a spectrum
analyzer, or from a Fourier transform, of the analog
output of the DAC. SFDR is specified in decibels
relative to the carrier (dBc).
Output
noise
density
is
defined
as
internally-generated random noise. Random noise is
characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to mid-scale and
measuring noise at the output.
Signal-to-Noise plus Distortion (SINAD)
SINAD includes all the harmonic and outstanding
spurious components in the definition of output noise
power in addition to quantizing any internal random
noise power. SINAD is expressed in dB at a specified
input frequency and sampling rate, fS.
DAC Output Noise
DAC output noise is defined as any voltage deviation
of DAC output from the desired value (within a
particular frequency band). It is measured with a DAC
channel kept at mid-scale while filtering the output
voltage within a band of 0.1Hz to 10Hz and
measuring its amplitude peaks. It is expressed in
terms of peak-to-peak voltage (Vpp).
Full-Scale Range (FSR)
Full-scale range (FSR) is the difference between the
maximum and minimum analog output values that the
DAC is specified to provide; typically, the maximum
and minimum values are also specified. For an n-bit
DAC, these values are usually given as the values
matching with code 0 and 2n.
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41
PACKAGE OPTION ADDENDUM
www.ti.com
26-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8564IAPW
ACTIVE
TSSOP
PW
16
DAC8564IAPWR
ACTIVE
TSSOP
PW
16
DAC8564IBPW
ACTIVE
TSSOP
PW
16
DAC8564IBPWR
ACTIVE
TSSOP
PW
16
DAC8564ICPW
ACTIVE
TSSOP
PW
16
DAC8564ICPWR
ACTIVE
TSSOP
PW
16
DAC8564IDPW
ACTIVE
TSSOP
PW
16
DAC8564IDPWR
ACTIVE
TSSOP
PW
16
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
90
90
90
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8564IAPWR
PW
16
SITE 60
330
12
7.0
5.6
1.6
8
12
Q1
DAC8564IBPWR
PW
16
SITE 60
330
12
7.0
5.6
1.6
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
DAC8564IAPWR
PW
16
SITE 60
346.0
346.0
29.0
DAC8564IBPWR
PW
16
SITE 60
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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