TI1 MSP430FG4616IPZR Mixed-signal microcontroller Datasheet

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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode: 400 µA at 1 MHz, 2.2 V
– Standby Mode: 1.3 µA
– Off Mode (RAM Retention): 0.22 µA
• Five Power-Saving Modes
• Wakeup From Standby Mode in Less Than 6 µs
• 16-Bit RISC Architecture, Extended Memory,
125‑ns Instruction Cycle Time
• Three-Channel Internal DMA
• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference, Sample-and-Hold and
Autoscan Feature
• Three Configurable Operational Amplifiers
• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
• 16-Bit Timer_A With Three Capture/Compare
Registers
• 16-Bit Timer_B With Seven Capture/CompareWith-Shadow Registers
• On-Chip Comparator
• Supply Voltage Supervisor and Monitor With
Programmable Level Detection
• Serial Communication Interface (USART1), Select
Asynchronous UART or Synchronous SPI by
Software
1.2
•
Applications
Portable Medical Applications
1.3
• Universal Serial Communication Interface
– Enhanced UART Supports Automatic BaudRate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
• Serial Onboard Programming, Programmable
Code Protection by Security Fuse
• Brownout Detector
• Basic Timer With Real-Time Clock (RTC) Feature
• Integrated LCD Driver up to 160 Segments With
Regulated Charge Pump
• Section 3 Summarizes the Available Family
Members
– MSP430FG4616, MSP430FG4616
92KB+256B of Flash or ROM
4KB of RAM
– MSP430FG4617, MSP430CG4617
92KB+256B of Flash or ROM
8KB of RAM
– MSP430FG4618, MSP430CG4618
116KB+256B of Flash or ROM
8KB of RAM
– MSP430FG4619, MSP430CG4619
120KB+256B of Flash or ROM
4KB of RAM
• For Complete Module Descriptions, see the
MSP430x4xx Family User’s Guide (SLAU056)
•
E-Meter Applications
Description
The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in less than 6 µs.
The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance
12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a segment liquid crystal display (LCD) driver with regulated charge
pump.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
Device Information (1)
PACKAGE
BODY SIZE (2)
LQFP (100)
14 mm × 14 mm
MicroStar Junior™ BGA (113)
7 mm × 7 mm
PART NUMBER
MSP430FG4619IPZ
MSP430FG4619IZQW
(1)
(2)
1.4
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
XIN /
XT2 IN
XOUT/
XT2 OUT
2
DVCC 1 /2
DVSS1 /2
AVCC
AVSS
P1. x/P2.x
2
Oscillators
FLL +
2x8
Flash (FG)
ROM (CG)
ACLK
120KB
116KB
92KB
92KB
SMCLK
MCLK
8MHz
CPUX
incl. 16
Registers
Enhanced
Emulation
(FG only )
JTAG
Interface
RAM
4KB
8KB
8KB
4KB
ADC 12
12-Bit
DAC 12
12-Bit
12
Channels
2 Channels
Voltage out
OA0, OA 1,
OA 2
Ports
P1/P2
Comparator
_A
P3. x/P4.x
P5. x/P6.x
4 x8
P 7.x/ P8. x
P 9.x/P 10.x
4x8/2x16
Ports
P3/P4
P5/P6
Ports
P7/P8
P9/P10
4x8 I/O
4x8, 2x16 I/O
2x8 I/O
3 Op Amps
Interrupt
capability
MAB
DMA
Controller
3 Channels
MDB
Brownout
Protection
SVS/ SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B 7
Watchdog
WDT+
15/16-Bit
Timer_A3
3 CC
Registers
7 CC
Registers,
Shadow
Reg
LCD_A
Basic Timer
and
Real-Time
Clock
160
Segments
1, 2,3,4 Mux
USCI_A 0:
UART,
IrDA, SPI
USART 1
UART , SPI
USCI_B 0:
SPI, I2 C
RST/NMI
Figure 1-1. Functional Block Diagram
2
Device Overview
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
5.30
12-Bit ADC, Timing Parameters
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
5.31
5.32
1.3
Description ............................................ 1
12-Bit ADC, Linearity Parameters................... 37
12-Bit ADC, Temperature Sensor and Built-In VMID
...................................................... 38
1.4
Functional Block Diagram ............................ 2
5.33
12-Bit DAC, Supply Specifications .................. 38
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
5.34
12-Bit DAC, Linearity Specifications ................ 39
5.35
12-Bit DAC, Output Specifications .................. 41
5.36
12-Bit DAC, Reference Input Specifications ........ 41
4.1
Pin Diagrams ......................................... 6
5.37
12-Bit DAC, Dynamic Specifications ................ 42
4.2
Signal Descriptions ................................... 8
5.38
12-Bit DAC, Dynamic Specifications Continued
Specifications ........................................... 14
5.39
5.40
Operational Amplifier OA, Supply Specifications ... 44
Operational Amplifier OA, Input/Output
Specifications........................................ 44
5.41
Operational Amplifier OA, Dynamic Specifications
5.42
5.43
Operational Amplifier OA, Typical Characteristics .. 45
Operational Amplifier OA Feedback Network,
Noninverting Amplifier Mode (OAFCx = 4) .......... 46
Operational Amplifier OA Feedback Network,
Inverting Amplifier Mode (OAFCx = 6) .............. 46
........................
........................................
Recommended Operating Conditions ...............
5.1
Absolute Maximum Ratings
14
5.2
ESD Ratings
14
5.3
5.4
14
Supply Current Into AVCC + DVCC Excluding
External Current .................................... 16
5.5
5.6
Thermal Characteristics ............................. 17
Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI,
JTAG (TCK, TMS, TDI/TCLK,TDO/TDI) ............ 18
5.7
Inputs Px.x, TAx, TBX............................... 18
5.8
................
Outputs – Ports P1 to P10 ..........................
Output Frequency ...................................
Typical Characteristics – Outputs ...................
Wake-up Timing From LPM3 .......................
RAM .................................................
LCD_A ...............................................
Comparator_A ......................................
Typical Characteristics – Comparator_A ............
POR, BOR ..........................................
SVS (Supply Voltage Supervisor and Monitor) .....
DCO .................................................
Crystal Oscillator, LFXT1 Oscillator ................
Crystal Oscillator, XT2 Oscillator ...................
USCI (UART Mode) .................................
USCI (SPI Master Mode)............................
USCI (SPI Slave Mode) .............................
USCI (I2C Mode) ....................................
USART1 .............................................
18
...................
34
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
5.26
5.27
Leakage Current – Ports P1 to P10
18
19
5.44
6
21
21
21
22
23
24
25
27
29
29
7
29
30
30
33
33
12-Bit ADC, Power Supply and Input Range
Conditions .......................................... 34
5.28
12-Bit ADC, External Reference
5.29
12-Bit ADC, Built-In Reference...................... 35
8
.
43
45
Flash Memory (FG461x Devices Only) ............. 47
5.46
JTAG Interface ...................................... 47
5.47
JTAG Fuse
.........................................
47
Detailed Description ................................... 48
................................................. 48
6.2
Instruction Set ....................................... 49
6.3
Operating Modes .................................... 50
6.4
Interrupt Vector Addresses.......................... 51
6.5
Special Function Registers (SFRs) ................. 52
6.6
Memory Organization ............................... 54
6.7
Bootstrap Loader (BSL) ............................. 55
6.8
Flash Memory ....................................... 55
6.9
Peripherals .......................................... 55
6.10 Input/Output Schematics ............................ 65
Device and Documentation Support .............. 100
7.1
Device Support..................................... 100
7.2
Documentation Support ............................ 103
7.3
Related Links ...................................... 103
7.4
Community Resources............................. 104
7.5
Trademarks ........................................ 104
7.6
Electrostatic Discharge Caution ................... 104
7.7
Export Control Notice .............................. 104
7.8
Glossary............................................ 104
CPU
Mechanical, Packaging, and Orderable
Information ............................................. 105
Table of Contents
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MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
....
37
5.45
6.1
20
....................
3
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from March 2, 2011 to June 19, 2015
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Document format and organization changes throughout, including the addition of section numbering ................... 1
Added Device Information table .................................................................................................... 2
Moved functional block diagram to Section 1.4 ................................................................................... 2
Added Section 3, Device Comparison ............................................................................................. 5
Added signal names to ZQW pinout figure ........................................................................................ 7
Changed table note that starts "Segments S0 through S3 are disabled when..." ............................................ 8
Added row for unassigned ball locations on ZQW package ................................................................... 13
Added Section 5 and moved all electrical specifications to it ................................................................. 14
Added Section 5.2, ESD Ratings.................................................................................................. 14
In Recommended Operating Conditions, added test conditions for TYP values ........................................... 14
Added Section 5.5, Thermal Characteristics .................................................................................... 17
Changed table note that starts "Segments S0 through S3 are disabled when..." .......................................... 21
Changed the value of DAC12_xDAT from 7F7h to F7Fh in Figure 5-33 .................................................... 43
Added Table 6-19 and moved P4.6 and P4.7 from Table 6-18 to insert correct LCDS32 control bit name ............ 75
Added Table 6-29 and moved P7.2 and P7.3 from Table 6-28 to insert correct LCDS28 control bit name ............ 88
Added Table 6-31 and moved P7.6 and P7.7 from Table 6-30 to insert correct LCDS24 control bit name ............ 89
Added Table 6-33 and moved P8.2 to P8.5 from Table 6-32 to insert correct LCDS20 control bit name............... 90
Added Table 6-36 and moved P9.2 to P9.5 from Table 6-35 to insert correct LCDS12 control bit name............... 92
Corrected LCD segment numbers in PIN NAME column of Table 6-36 ..................................................... 92
Added Table 6-37 and moved P9.6 and P9.7 from Table 6-35 to insert correct LCDS8 control bit name .............. 93
Corrected LCD segment numbers in PIN NAME column of Table 6-37 ..................................................... 93
Corrected LCD segment numbers in PIN NAME and FUNCTION columns of Table 6-38 ................................ 94
Added Table 6-39 and moved P10.2 to P10.5 from Table 6-38 to insert correct LCDS4 control bit name ............. 94
Added Section 7 and moved Trademarks and ESD Caution sections to it ................................................ 100
Added Section 8 ................................................................................................................... 105
Revision History
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
DEVICE
FLASH
(KB)
ROM
(KB)
RAM
(KB)
EEM
Timer_A
Timer_B
ADC12
(Channels)
OP AMP
DAC12
(Channels)
COMP_A
(Channels)
USART
USCI
I/O
PACKAGE
MSP430FG4619
120
–
4
1
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430FG4618
116
–
8
1
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430FG4617
92
–
8
1
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430FG4616
92
–
4
1
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430CG4619
–
120
4
–
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430CG4618
–
116
8
–
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430CG4617
–
92
8
–
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
MSP430CG4616
–
92
4
–
TA3
TB7
12
3
2
2
1
A0, B0
80
PZ 100
ZQW 113
(1)
(2)
For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2006–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Device Comparison
5
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
78
77
76
P1.5/TACLK/ACLK
P1.6/CA0
82
79
P1.4/TBCLK/SMCLK
83
80
P1.3/TBOUTH/SVSOUT
84
81
P1.1/TA0/MCLK
P1.2/TA1
86
85
XT2OUT
P1.0/TA0
87
88
89
TDI/TCLK
TDO/TDI
XT2IN
TMS
92
90
TCK
93
91
P6.0/A0/OA0I0
RST/NMI
95
94
P6.2/A2/OA0I1
P6.1/A1/OA0O
96
97
98
99
100
AV CC
DV SS1
AV SS
Figure 4-1 shows the pinout for the 100-pin PZ package.
DVCC2
P10.4/S5
17
59
LCDCAP/R33
P10.3/S6
18
58
P5.7/R23
P10.2/S7
19
57
P5.6/LCDREF/R13
P10.1/S8
20
56
P5.5/R03
P10.0/S9
21
55
P5.4/COM3
P9.7/S10
22
54
P5.3/COM2
P9.6/S11
23
53
P5.2/COM1
P9.5/S12
24
52
COM0
P9.4/S13
25
51
P4.2/STE1/S39
50
60
P4.3/SIMO1/S38
16
49
DVSS2
P10.5/S4
48
61
P4.4/SOMI1/S37
15
P4.5/UCLK1/S36
P4.1/URXD1
P10.6/S3/A15
47
62
46
14
P4.6/UCA0TXD/S35
P4.0/UTXD1
P10.7/S2/A14/OA2I1
P4.7/UCA0RXD/S34
63
45
13
P7.0/UCA0STE/S33
P3.7/TB6
P5.0/S1/A13/OA1I1
44
64
43
12
42
P3.6/TB5
P5.1/S0/A12/DAC1
P7.3/UCA0CLK/S30
65
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
11
41
P3.5/TB4
VREF-/VeREF-
40
66
P7.5/S28
P7.4/S29
10
39
P3.4/TB3
VeREF+/DAC0
P7.6/S27
67
38
9
37
P3.3/UCB0CLK
XOUT
P7.7/S26
68
P8.0/S25
8
36
P3.2/UCB0SOMI/UCB0SCL
XIN
P8.1/S24
69
35
7
P8.2/S23
P3.1/UCB0SIMO/UCB0SDA
VREF+
34
70
33
6
P8.4/S21
P8.3/S22
P3.0/UCB0STE
P6.7/A7/DAC1/SVSIN
32
71
31
5
P8.5/S20
P2.7/ADC12CLK/DMAE0
P6.6/A6/DAC0/OA2I0
P8.6/S19
72
30
4
P8.7/S18
P2.6/CAOUT
P6.5/A5/OA2O
29
73
28
3
P9.0/S17
P2.5/UCA0RXD
P6.4/A4/OA1I0
27
P2.4/UCA0TXD
74
26
75
2
P9.3/S14
1
P9,2/S15
P9.1/S16
DVCC1
P6.3/A3/OA1O
Figure 4-1. 100-Pin PZ Package (Top View)
6
Terminal Configuration and Functions
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Figure 4-2 shows the pinout for the 113-pin ZQW package. This figure shows only the default pin
assignments; for all pin assignments, see Table 4-1.
DVCC1
AVCC
AVSS
P6.0
TCK
P6.3
P6.4
DVSS1
P6.2
RST
P6.6
P6.5
P6.7
XIN
VREF+
N/A
P6.1
TDI
P1.2
P2.1
XOUT
VeREF+
VREF–
P10.7
TMS
P1.1
P5.1
P5.0
P10.4
P10.6
P10.5
P10.3
P1.3
P1.6
P2.0
P2.3
N/A
XT2IN XT2OUT P1.4
P1.5
P1.7
N/A
P2.4
P2.5
P2.6
N/A
P3.0
P3.1
P2.2
P2.7
P3.3
P3.4
P10.1
N/A
P3.2
P3.6
P3.7
P9.6
P8.4
N/A
P3.5
P4.1
DVSS2
P10.2
P8.7
P8.1
P7.3
P4.4
N/A
P4.0
P10.0
P9.7
N/A
P8.0
P7.5
P4.7
P5.3
N/A
P9.5
P9.2
P9.4
N/A
P9.1
P8.6
P8.3
P7.6
P7.2
P7.0
P4.5
N/A
P9.3
P9.0
P8.5
P8.2
P7.7
P7.4
P7.1
P4.6
TDO
P1.0
A
B
C
D
E
F
G
LCDCAP DVCC2
H
P5.7
P5.6
P5.5
P5.4
COM0
N/A
P5.2
P4.3
P4.2
N/A
J
K
L
M
1
2
3
4
5
6
7
8
9
10
11
12
N/A = Not Assigned. All unassigned ball locations on the ZQW package should be electrically tied to the ground
supply. The shortest ground return path to the device should be established to ball location B3, DVSS1.
Figure 4-2. 113-Pin ZQW Package (Top View)
Terminal Configuration and Functions
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Copyright © 2006–2015, Texas Instruments Incorporated
7
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
4.2
www.ti.com
Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
SIGNAL NAME
DVCC1
PIN NO.
PZ
ZQW
1
A1
2
B1
I/O
Digital supply voltage, positive terminal
P6.3
A3
General-purpose digital I/O
I/O
OA1O
General-purpose digital I/O
3
B2
I/O
OA1I0
Analog input A4 for 12-bit ADC
OA1 input multiplexer on + terminal and – terminal
P6.5
A5
Analog input A3 for 12-bit ADC
OA1 output
P6.4
A4
DESCRIPTION
General-purpose digital I/O
4
C2
I/O
Analog input A5 for 12-bit ADC
OA2O
OA2 output
P6.6
General-purpose digital I/O
A6
DAC0
5
C1
I/O
Analog input A6 for 12-bit ADC
DAC12.0 output
OA2I0
OA2 input multiplexer on + terminal and – terminal
P6.7
General-purpose digital I/O
A7
Analog input A7 for 12-bit ADC
6
C3
I/O
VREF+
7
D2
O
Output of positive terminal of the reference voltage in the ADC
XIN
8
D1
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
E1
O
Output terminal of crystal oscillator XT1
10
E2
I/O
11
E4
I
DAC1
SVSIN
VeREF+
DAC0
VREF
VeREF–
Analog input to brownout, supply voltage supervisor
P5.1
S0
Input for an external reference voltage to the ADC
DAC12.0 output
Internal reference voltage, negative terminal for the ADC reference voltage
External applied reference voltage, negative terminal for the ADC reference voltage
General-purpose digital I/O
(1)
12
A12
DAC12.1 output
F1
I/O
LCD segment output 0
Analog input A12 for 12-bit ADC
DAC1
DAC12.1 output
P5.0
General-purpose digital I/O
S1
(1)
13
A13
F2
I/O
LCD segment output 1
Analog input A13 for 12-bit ADC
OA1I1
OA1 input multiplexer on + terminal and – terminal
P10.7
General-purpose digital I/O
S2 (1)
A14
14
E5
I/O
OA2I1
General-purpose digital I/O
15
G1
I/O
A15
(1)
8
Analog input A14 for 12-bit ADC
OA2 input multiplexer on + terminal and – terminal
P10.6
S3 (1)
LCD segment output 2
LCD segment output 3
Analog input A15 to 12-bit ADC
Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used
together with the LCD charge pump. On the MSP430xG461x devices only, S0 through S3 are also disabled if VLCDEXT = 1. This
setting is typically used to apply an external LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0,
VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal.
Terminal Configuration and Functions
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 4-1. Signal Descriptions (continued)
SIGNAL NAME
P10.5
S4
P10.4
S5
P10.3
S6
P10.2
S7
P10.1
S8
P10.0
S9
P9.7
S10
P9.6
S11
P9.5
S12
P9.4
S13
P9.3
S14
P9.2
S15
P9.1
S16
P9.0
S17
P8.7
S18
P8.6
S19
P8.5
S20
P8.4
S21
P8.3
S22
P8.2
S23
P8.1
S24
P8.0
S25
P7.7
S26
PIN NO.
I/O
PZ
ZQW
16
G2
I/O
17
F4
I/O
18
H1
I/O
19
H2
I/O
20
F5
I/O
21
J1
I/O
22
J2
I/O
23
G4
I/O
24
K1
I/O
25
L1
I/O
26
M2
I/O
27
K2
I/O
28
L3
I/O
29
M3
I/O
30
H4
I/O
31
L4
I/O
32
M4
I/O
33
G5
I/O
34
L5
I/O
35
M5
I/O
36
H5
I/O
37
J5
I/O
38
M6
I/O
DESCRIPTION
General-purpose digital I/O
LCD segment output 4
General-purpose digital I/O
LCD segment output 5
General-purpose digital I/O
LCD segment output 6
General-purpose digital I/O
LCD segment output 7
General-purpose digital I/O
LCD segment output 8
General-purpose digital I/O
LCD segment output 9
General-purpose digital I/O
LCD segment output 10
General-purpose digital I/O
LCD segment output 11
General-purpose digital I/O
LCD segment output 12
General-purpose digital I/O
LCD segment output 13
General-purpose digital I/O
LCD segment output 14
General-purpose digital I/O
LCD segment output 15
General-purpose digital I/O
LCD segment output 16
General-purpose digital I/O
LCD segment output 17
General-purpose digital I/O
LCD segment output 18
General-purpose digital I/O
LCD segment output 19
General-purpose digital I/O
LCD segment output 20
General-purpose digital I/O
LCD segment output 21
General-purpose digital I/O
LCD segment output 22
General-purpose digital I/O
LCD segment output 23
General-purpose digital I/O
LCD segment output 24
General-purpose digital I/O
LCD segment output 25
General-purpose digital I/O
LCD segment output 26
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
SIGNAL NAME
P7.6
S27
P7.5
S28
P7.4
S29
PIN NO.
I/O
PZ
ZQW
39
L6
I/O
40
J6
I/O
41
M7
I/O
P7.3
DESCRIPTION
General-purpose digital I/O
LCD segment output 27
General-purpose digital I/O
LCD segment output 28
General-purpose digital I/O
LCD segment output 29
General-purpose digital I/O
UCA0CLK
42
H6
I/O
S30
External clock input – USCI_A0 in UART or SPI mode,
Clock output – USCI_A0 in SPI mode
LCD segment 30
P7.2
General-purpose digital I/O
UCA0SOMI
43
L7
I/O
S31
Slave out/master in of USCI_A0 in SPI mode
LCD segment output 31
P7.1
General-purpose digital I/O
UCA0SIMO
44
M8
I/O
Slave in/master out of USCI_A0 in SPI mode
S32
LCD segment output 32
P7.0
General-purpose digital I/O
UCA0STE
45
L8
I/O
Slave transmit enable – USCI_A0 in SPI mode
S33
LCD segment output 33
P4.7
General-purpose digital I/O
UCA0RXD
46
J7
I/O
Receive data in – USCI_A0 in UART or IrDA mode
S34
LCD segment output 34
P4.6
General-purpose digital I/O
UCA0TXD
47
M9
I/O
Transmit data out – USCI_A0 in UART or IrDA mode
S35
LCD segment output 35
P4.5
General-purpose digital I/O
UCLK1
48
L9
I/O
External clock input – USART1 in UART or SPI mode,
Clock output – USART1 in SPI MODE
S36
LCD segment output 36
P4.4
General-purpose digital I/O
SOMI1
49
H7
I/O
Slave out/master in of USART1 in SPI mode
S37
LCD segment output 37
P4.3
General-purpose digital I/O
SIMO1
50
M10
I/O
S38
LCD segment output 38
P4.2
STE1
General-purpose digital I/O
51
M11
I/O
52
L10
O
53
L12
I/O
54
J8
I/O
55
K12
I/O
56
K11
I/O
S39
COM0
P5.2
COM1
P5.3
COM2
P5.4
COM3
P5.5
R03
10
Slave in/master out of USART1 in SPI mode
Slave transmit enable – USART1 in SPI mode
LCD segment output 39
Terminal Configuration and Functions
Common output, COM0 for LCD backplanes
General-purpose digital I/O
Common output, COM1 for LCD backplanes
General-purpose digital I/O
Common output, COM2 for LCD backplanes
General-purpose digital I/O
Common output, COM3 for LCD backplanes
General-purpose digital I/O
Input port of lowest analog LCD level (V5)
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 4-1. Signal Descriptions (continued)
SIGNAL NAME
PIN NO.
PZ
ZQW
57
J12
I/O
P5.6
LCDREF
General-purpose digital I/O
I/O
R13
P5.7
DESCRIPTION
External reference voltage input for regulated LCD voltage
Input port of third most positive analog LCD level (V4 or V3)
General-purpose digital I/O
58
J11
I/O
59
H11
I
DVCC2
60
H12
Digital supply voltage, positive terminal
DVSS2
61
G12
Digital supply voltage, negative terminal
62
G11
I/O
63
H9
I/O
64
F12
I/O
65
F11
I/O
66
G9
I/O
67
E12
I/O
68
E11
I/O
69
F9
I/O
R23
LCDCAP
R33
P4.1
URXD1
P4.0
UTXD1
P3.7
TB6
P3.6
TB5
P3.5
TB4
P3.4
TB3
P3.3
UCB0CLK
D12
I/O
71
D11
I/O
CAOUT
P2.5
UCA0RXD
P2.4
UCA0TXD
P2.3
TB2
P2.2
TB1
P2.1
TB0
Transmit data out – USART1 in UART mode
General-purpose digital I/O
Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6 output
General-purpose digital I/O
Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5 output
General-purpose digital I/O
Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O
Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output
External clock input – USCI_B0 in UART or SPI mode,
Clock output – USCI_B0 in SPI mode
Slave out/master in of USCI_B0 in SPI mode
Slave in/master out of USCI_B0 in SPI mode
General-purpose digital I/O
Slave transmit enable – USCI_B0 in SPI mode
General-purpose digital I/O
72
E9
I/O
DMAE0
P2.6
General-purpose digital I/O
I2C data – USCI_B0 in I2C mode
P2.7
ADC12CLK
Receive data in – USART1 in UART mode
General-purpose digital I/O
70
UCB0SDA
UCB0STE
General-purpose digital I/O
I2C clock – USCI_B0 in I2C mode
P3.1
P3.0
Input/output port of most positive analog LCD level (V1)
General-purpose digital I/O
UCB0SCL
UCB0SIMO
LCD capacitor connection
General-purpose digital I/O
P3.2
UCB0SOMI
Input port of second most positive analog LCD level (V2)
Conversion clock for 12-bit ADC
DMA channel 0 external trigger
73
C12
I/O
74
C11
I/O
75
B12
I/O
76
A11
I/O
77
E8
I/O
78
D8
I/O
General-purpose digital I/O
Comparator_A output
General-purpose digital I/O
Receive data in – USCI_A0 in UART or IrDA mode
General-purpose digital I/O
Transmit data out – USCI_A0 in UART or IrDA mode
General-purpose digital I/O
Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O
Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O
Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
SIGNAL NAME
P2.0
TA2
P1.7
CA1
P1.6
CA0
PIN NO.
I/O
PZ
ZQW
79
A10
I/O
80
B10
I/O
81
A9
I/O
82
B9
I/O
P1.5
DESCRIPTION
General-purpose digital I/O
Timer_A Capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
Comparator_A input
General-purpose digital I/O
Comparator_A input
General-purpose digital I/O
TACLK
Timer_A, clock signal TACLK input
ACLK
ACLK output (divided by 1, 2, 4, or 8)
P1.4
General-purpose digital I/O
TBCLK
83
B8
I/O
Input clock TBCLK – Timer_B7
SMCLK
Submain system clock SMCLK output
P1.3
General-purpose digital I/O
TBOUTH
84
A8
I/O
SVSOUT
P1.2
TA1
Switch all PWM digital output ports to high impedance – Timer_B7 TB0 to TB6
SVS: output of SVS comparator
85
D7
I/O
86
E7
I/O
P1.1
General-purpose digital I/O
Timer_A, Capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
TA0
MCLK
Timer_A. Capture: CCI0B input. Note: TA0 is only an input on this pin. BSL receive.
MCLK output
P1.0
General-purpose digital I/O
87
A7
I/O
XT2OUT
88
B7
O
Output terminal of crystal oscillator XT2
XT2IN
89
B6
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
90
A6
I/O
91
D6
I
TMS
92
E6
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
93
A5
I
Test clock. TCK is the clock input port for device programming and test.
94
B5
I
TA0
TDO
TDI
TDI
TCLK
RST
NMI
P6.0
A0
Timer_A. Capture: CCI0A input, compare: Out0 output. BSL transmit.
Test data output port. TDO/TDI data output.
Programming data input terminal
Test data input
Test clock input. The device protection fuse is connected to TDI/TCLK.
Reset input
Nonmaskable interrupt input port
General-purpose digital I/O
95
A4
I/O
Analog input A0 for 12-bit ADC
OA0I0
OA0 input multiplexer on + terminal and – terminal
P6.1
General-purpose digital I/O
A1
96
D5
I/O
OA0O
OA0 output
P6.2
A2
Analog input A1 for 12-bit ADC
General-purpose digital I/O
97
B4
I/O
OA0I1
Analog input A2 for 12-bit ADC
OA0 input multiplexer on + terminal and – terminal
AVSS
98
A3
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator,
Comparator_A, port 1
DVSS1
99
B3
Digital supply voltage, negative terminal
AVCC
100
A2
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator,
Comparator_A, port 1. Do not power up before powering DVCC1 and DVCC2.
12
Terminal Configuration and Functions
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 4-1. Signal Descriptions (continued)
SIGNAL NAME
Not Assigned
PIN NO.
PZ
ZQW
–
A12,
B11, D4,
D9, F8,
G8, H8,
J4, J9,
L2, L11,
M1, M12
I/O
DESCRIPTION
–
All unassigned ball locations on the ZQW package should be electrically tied to the ground
supply. The shortest ground return path to the device should be established to ball location
B3, DVSS1.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
Voltage applied to any pin
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device terminal
Storage temperature, Tstg
(1)
(2)
UNIT
V
V
±2
Unprogrammed device
–55
105
Programmed device
–40
85
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to VSS.The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
During program execution
(AVCC = DVCC1/2 = VCC)
VCC
Supply voltage
TA
Operating free-air temperature range
f(LFXT1)
f(XT2)
f(System)
(1)
(2)
(3)
14
Crystal frequency (3)
2.7
3.6
2
3.6
0
0
V
85
°C
450
8000
kHz
1000
8000
450
8000
1000
8000
VCC = 1.8 V
DC
3
VCC = 2.0 V
DC
4.6
VCC = 3.6 V
DC
8
–40
LF selected, XTS_FLL = 0 (3)
Watch crystal
XT1 selected, XTS_FLL = 1
Ceramic resonator
XT1 selected, XTS_FLL = 1
Crystal
Crystal frequency
Processor frequency (signal MCLK)
UNIT
3.6
During program execution, SVS enabled and PORON = 1 (1)
(AVCC = DVCC1/2 = VCC) (2)
Supply voltage (AVSS = DVSS1/2 = VSS)
MAX
1.8
During flash memory programming (FG461x)
(AVCC = DVCC1/2 = VCC) (1)
VSS
NOM
(1)
Ceramic resonator
Crystal
V
32.768
kHz
MHz
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
fSystem (MHz)
8.0 MHz
Supply voltage range,
MSP430xG461x, during
program execution
Supply voltage range, MSP430FG461x,
during flash memory programming
4.6 MHz
3.0 MHz
1.8
2.0
2.7
3
Supply Voltage (V)
3.6
Figure 5-1. Frequency vs Supply Voltage
Specifications
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.4
www.ti.com
Supply Current Into AVCC + DVCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITION
(1) (2)
I(AM)
Active mode
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32768 Hz,
XTS = 0, SELM = (0, 1),
(FG461x: program executes from flash)
I(LPM0)
Low power mode (LPM0) (1)
I(LPM2)
Low-power mode (LPM2),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 0 (3)
I(LPM3)
(2)
CG461x
FG461x
TA = –40°C to 85°C
TA = –40°C to 85°C
Low-power mode (LPM3),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 1,
Basic Timer1 enabled, ACLK selected,
LCD_A enabled, LCDCPEN = 0,
(static mode, fLCD = f(ACLK)/32) (3) (4) (2)
I(LPM3)
280
370
VCC = 3 V
470
580
VCC = 2.2 V
400
480
VCC = 3 V
600
740
70
75
110
VCC = 2.2 V
11
20
VCC = 3 V
17
24
TA = –40°C
1.3
4.0
TA = 25°C
1.3
4.0
TA = –40°C to 85°C
TA = 60°C
VCC = 2.2 V
2.22
6.5
TA = 85°C
6.5
15.0
TA = –40°C
1.9
5.0
1.9
5.0
TA = 25°C
VCC = 3 V
2.5
7.5
TA = 85°C
7.5
18.0
TA = –40°C
1.5
5.5
TA = 25°C
1.5
5.5
TA = 60°C
VCC = 2.2 V
2.8
7.0
TA = 85°C
7.2
17.0
TA = –40°C
2.5
6.5
2.5
6.5
3.2
8.0
TA = 85°C
8.5
20.0
TA = –40°C
0.13
1.0
TA = 25°C
0.22
1.0
TA = 25°C
TA = 60°C
I(LPM4)
VCC = 2.2 V
45
TA = 60°C
Low-power mode (LPM4),
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1 (3) (2)
MAX
VCC = 3 V
TA = 60°C
Low-power mode (LPM3),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 1,
Basic Timer1 enabled, ACLK selected,
LCD_A enabled, LCDCPEN = 0,
(4-mux mode; fLCD = f(ACLK)/32) (3) (4) (2)
TYP
VCC = 2.2 V
TA = –40°C to 85°C
(2)
VCC = 3 V
VCC = 2.2 V
0.9
2.5
TA = 85°C
4.3
12.5
TA = –40°C
0.13
1.6
0.3
1.6
TA = 25°C
TA = 60°C
VCC = 3 V
TA = 85°C
(1)
(2)
(3)
(4)
MIN
1.1
3.0
5.0
15.0
UNIT
µA
µA
µA
µA
µA
µA
Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for brownout included.
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The LPM3 currents are characterized with a Micro Crystal CC4V-T1A (9 pF) crystal and OSCCAPx = 1h.
Current consumption of active mode versus system frequency, FG version:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, FG version:
I(AM) = I(AM) [3 V] + 200 µA/V × (VCC – 3 V)
16
Specifications
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5.5
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Thermal Characteristics
PARAMETER
PACKAGE
Junction-to-ambient thermal resistance, still air (1)
θJA
(2)
VALUE
UNIT
42
°C/W
10
°C/W
12
°C/W
12
°C/W
θJC,TOP
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (3)
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
0.3
°C/W
θJA
Junction-to-ambient thermal resistance, still air (1)
43.5
°C/W
θJC,TOP
Junction-to-case (top) thermal resistance (2)
6.2
°C/W
(3)
ZQW (S-PBGA-N113)
θJB
Junction-to-board thermal resistance
21.8
°C/W
ΨJB
Junction-to-board thermal characterization parameter
21.2
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
(1)
(2)
(3)
PZ (S-PQFP-G100)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.6
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Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT– )
5.7
MIN
MAX
VCC = 2.2 V
1.1
1.55
VCC = 3 V
1.5
1.98
VCC = 2.2 V
0.4
0.9
VCC = 3 V
0.9
1.3
VCC = 2.2 V
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
Inputs Px.x, TAx, TBX
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
62
3V
50
2.2 V
62
3V
50
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag (1)
t(cap)
Timer_A, Timer_B capture timing
TA0, TA1, TA2
TB0, TB1, TB2, TB3, TB4, TB5, TB6
f(TAext)
Timer_A or Timer_B clock frequency TACLK, TBCLK
externally applied to pin
INCLK t(H) = t(L)
f(TBext)
f(TAint)
f(TBint)
(1)
Timer A or Timer B clock frequency
SMCLK or ACLK signal selected
MIN
MAX
UNIT
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
Leakage Current – Ports P1 to P10 (1)
5.8
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
5.9
TEST CONDITIONS
V(Px.y) (2)
(1 ≤ × ≤ 10, 0 ≤ y ≤ 7)
Leakage current, Port Px
MIN
MAX
UNIT
±50
nA
UNIT
VCC = 2.2 V, 3 V
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The port pin must be selected as input.
Outputs – Ports P1 to P10
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
VCC – 0.25
VCC
IOH(max) = –6 mA, VCC = 2.2 V (2)
VCC – 0.6
VCC
(1)
VCC – 0.25
VCC
IOH(max) = –1.5 mA, VCC = 2.2 V (1)
VOH
High-level output voltage
IOH(max) = –1.5 mA, VCC = 3 V
IOH(max) = –6 mA, VCC = 3 V (2)
VOL
(1)
(2)
18
Low-level output voltage
VCC – 0.6
VCC
IOL(max) = 1.5 mA, VCC = 2.2 V (1)
VSS
VSS + 0.25
IOL(max) = 6 mA, VCC = 2.2 V (2)
VSS
VSS + 0.6
IOL(max) = 1.5 mA, VCC = 3 V (1)
VSS
VSS + 0.25
IOL(max) = 6 mA, VCC = 3 V (2)
VSS
VSS + 0.6
V
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified
voltage drop.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified
voltage drop.
Specifications
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5.10
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Output Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f(Px.y)
(1 ≤ × ≤ 10, 0 ≤ y ≤ 7)
CL = 20 F, IL = ±1.5 mA
f(MCLK)
f(SMCLK)
P1.1/TA0/MCLK
P1.4/TBCLK/SMCLK
CL = 20 pF
f(ACLK)
P1.5/TACLK/ACLK
Duty cycle of output
frequency
P1.1/TA0/MCLK,
CL = 20 pF, VCC = 2.2 V, 3 V
P1.4/TBCLK/SMCLK,
CL = 20 pF, VCC = 2.2 V, 3 V
MAX
DC
10
VCC = 3 V
DC
12
VCC = 2.2 V
10
DC
12
f(ACLK) = f(LFXT1) = f(XT1)
40%
60%
f(ACLK) = f(LFXT1) = f(LF)
30%
70%
f(ACLK) = f(LFXT1)
t(Xdc)
TYP
VCC = 2.2 V
VCC = 3 V
P1.5/TACLK/ACLK,
CL = 20 pF, VCC = 2.2 V, 3 V
MIN
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
f(SMCLK) = f(XT2)
f(SMCLK) = f(DCOCLK)
MHz
MHz
50%
40%
60%
50% –
15 ns
50%
50%+
15 ns
40%
60%
50% –
15 ns
50%
50% +
15 ns
Specifications
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UNIT
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5.11 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
50.0
VCC = 2.2 V
P2.0
TA = 25°C
IOL - Typical Low-Level Output Current - mA
IOL - Typical Low-Level Output Current - mA
25.0
TA = 85°C
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
VOL – Low-Level Output Voltage – V
Figure 5-2. Typical Low-Level Output Current vs Typical LowLevel Output Current
30.0
20.0
10.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL - Low-Level Output Voltage - V
Figure 5-3. Typical Low-Level Output Current vs Typical LowLevel Output Current
IOH - Typical High-Level Output Curren - mA
IOH - typical High-Level Output Current - mA
TA = 85°C
0.0
VCC = 2.2 V
P2.0
-5.0
-10.0
-15.0
TA = 85°C
0.5
1.0
1.5
2.0
2.5
VOH - High-Level Output Voltage - V
Figure 5-4. Typical High-Level Output Current vs Typical HighLevel Output Current
Specifications
VCC = 3 V
P2.0
-10.0
-20.0
-30.0
-40.0
TA = 85°C
TA = 25°C
TA = 25°C!
-25.0
0.0
20
TA = 25°C
40.0
0.0
0.0
0.0
-20.0
VCC = 3 V
P2.0
-50.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH - High-Level Output Voltage - V
Figure 5-5. Typical High-Level Output Current vs Typical HighLevel Output Current
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5.12
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Wake-up Timing From LPM3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
f = 1 MHz
td(LPM3)
Delay time
6
f = 2 MHz
VCC = 2.2 V, 3 V
6
f = 3 MHz
5.13
UNIT
µs
6
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
CPU halted (1)
VRAMh
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
5.14
LCD_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(LCD)
Supply voltage
ICC(LCD)
Supply current (1)
CLCD
Capacitor on LCDCAP (3)
fLCD
LCD frequency
VLCD
RLCD
(1)
(2)
(3)
(4)
TEST CONDITIONS
VCC
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
(1)
VLCD(typ) = 3 V, LCDCPEN = 1,
VLCDx= 1000, all segments on, fLCD = fACLK/32,
no LCD connected (2), TA = 25°C
(4)
LCD voltage (4)
LCD driver output impedance
MIN
TYP
2.2
2.2 V
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
MAX
3.6
3
µF
1.1
VCC
VLCDx = 0001
2.60
VLCDx = 0010
2.66
VLCDx = 0011
2.72
VLCDx = 0100
2.78
VLCDx = 0101
2.84
VLCDx = 0110
2.90
VLCDx = 0111
2.96
VLCDx = 1000
3.02
VLCDx = 1001
3.08
VLCDx = 1010
3.14
VLCDx = 1011
3.20
VLCDx = 1100
3.26
VLCDx = 1101
3.32
VLCDx = 1110
3.38
VLCDx = 1111
3.44
2.2 V
V
µA
4.7
VLCDx = 0000
VLCD= 3 V, CPEN = 1,
VLCDx = 1000, ILOAD = ±10 µΑ
UNIT
kHz
V
3.60
10
kΩ
Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
Connecting an actual display increases the current consumption depending on the size of the LCD.
Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used
together with the LCD charge pump. On the MSP430xG461x devices only, S0 through S3 are also disabled if VLCDEXT = 1. This
setting is typically used to apply an external LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0,
VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal.
Specifications
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5.15 Comparator_A (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(CC)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = (1, 2, 3),
No load at P1.6/CA0 and P1.7/CA1
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V
0.23
0.24
0.25
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0 and P1.7/CA1,
TA = 85°C
V(RefVT)
Common-mode input
voltage range
VIC
CAON = 1
(2)
Vp – VS
Offset voltage
Vhys
Input hysteresis
CAON = 1
(1)
(2)
22
µA
µA
mV
2.2 V, 3 V
0
2.2 V, 3 V
–30
30
mV
2.2 V, 3 V
0
0.7
1.4
mV
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V
160
210
300
3V
80
150
240
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V
130
210
300
3V
80
150
240
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
t(response LH)
t(response HL)
VCC – 1
UNIT
V
ns
µs
ns
µs
The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The
two successive measurements are then summed together.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.16 Typical Characteristics – Comparator_A
650
650
VCC = 2.2 V
VREF - Reference Voltage - mV
VREF - Reference Voltage - mV
VCC = 3 V
600
Typical
550
500
450
400
-45
-25
15
-5
35
55
75
95
TA - Free-Air Temperature - °C
Figure 5-6. Reference Voltage vs Free-Air Temperature
0V
600
Typical
550
500
450
400
-45
-25
-5
15
35
55
75
95
TA - Free-Air Temperature - °C
Figure 5-7. Reference Voltage vs Free-Air Temperature
VCC
0
1
CAF
CAON
Low-Pass Filter
V+
V-
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
t » 2 µs
Figure 5-8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-
400 mV
V+
t(response)
Figure 5-9. Overdrive Definition
Specifications
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5.17 POR, BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
Brownout (2)
V(B_IT–)
V(B_IT–
2000
µs
dVCC/dt ≤ 3 V/s (see Figure 5-10)
t(reset)
Pulse duration needed at RST/NMI pin to accepted
reset internally, VCC = 2.2 V, 3 V
70
V
)
dVCC/dt ≤ 3 V/s (see Figure 5-10 through Figure 512)
(3)
Vhys(B_IT–)
(1)
(2)
(3)
UNIT
0.7 ×
dVCC/dt ≤ 3 V/s (see Figure 5-10)
VCC(start)
MAX
130
1.79
V
210
mV
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data.
The voltage level V(B_IT–) + Vhys(B_IT–) ≤ 1.89 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default FLL+ settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the
MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout and SVS circuit.
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(start)
1
0
td(BOR)
Figure 5-10. POR, BOR vs Supply Voltage
V CC
2
tpw
3V
VCC = 3 V
Typical Conditions
VCC(drop) - V
1.5
1
V CC(drop)
0.5
0
0.001
1
1000
1 ns
tpw - Pulse Width - m s
1 ns
tpw - Pulse Width - ms
Figure 5-11. VCC(drop) Level with a Square Voltage Drop to Generate a POR or BOR Signal
24
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
V CC
2
tpw
3V
VCC = 3 V
Typical Conditions
V C C (drop) - V
1.5
1
V CC(drop)
0.5
tf = tr
0
0.001
1
1000
tf
tr
tpw - Pulse Width - ms
tpw - Pulse Width - m s
Figure 5-12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
5.18
SVS (Supply Voltage Supervisor and Monitor)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 5-13)
t(SVSR)
SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0 (1)
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-13)
2000
150
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 5-13)
Vhys(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage
applied on A7
VCC/dt ≤ 3 V/s (see Figure 5-13)
V(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage
applied on A7
(1)
(2)
(3)
(3)
VLD ≠ 0, VCC = 2.2 V, 3 V
MAX
150
dVCC/dt ≤ 30 V/ms
td(SVSon)
ICC(SVS)
TYP
5
VLD = 2 to 14
VLD = 15
70
120
µs
300
µs
12
µs
1.7
V
155
mV
V(SVS_IT–)
× 0.001
V(SVS_IT–)
× 0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.35
VLD = 4
2.14
2.3
2.46
VLD = 5
2.24
2.4
2.58
VLD = 6
2.33
2.5
2.69
VLD = 7
2.46
2.65
2.84
VLD = 8
2.58
2.8
2.97
VLD = 9
2.69
2.9
3.10
VLD = 10
2.83
3.05
3.26
VLD = 11
2.94
3.2
3.39
VLD = 12
3.11
3.35
3.58 (2)
VLD = 13
3.24
3.5
3.73 (2)
VLD = 14
3.43
(2)
3.96 (2)
VLD = 15
1.1
1.2
1.3
10
15
3.7
UNIT
mV
V
µA
tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD
value from 2 to 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
The current consumption of the SVS module is not included in the ICC current consumption data.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Software Sets VLD>0:
SVS is Active
VCC
Vhys(SVS_IT-)
V(SVS_IT-)
V(SVSstart)
Vhys(B_IT-)
V(B_IT-)
VCC(start)
Brown
Out
Region
Brownout
Region
Brownout
1
0
t d(BOR)
SVSOut
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT-)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 5-13. SVS Reset (SVSR) vs Supply Voltage
V CC
tpw
3V
2
Rectangular Drop
V CC(drop)
V C C (drop) - V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
V CC
t pw
3V
0
1
10
100
1000
tpw - Pulse Width - m s
V CC(drop)
tf = tr
tf
tr
t - Pulse Width - ms
Figure 5-14. VCC(drop) with a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
26
Specifications
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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5.19
SLAS508J – APRIL 2006 – REVISED JUNE 2015
DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
f(DCOCLK)
N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0
f(DCO = 2)
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO = 27)
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO = 2)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO = 27)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO = 2)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO = 27)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO = 2)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO = 27)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO = 2)
FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO = 27)
FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) /fDCO(Tap n) (see Figure 5-16 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
MIN
TYP
2.2 V, 3 V
f(DCO)
f(DCO)
f(DCO20°C)
MHz
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
1.0
UNIT
1
2.2 V
f(DCO3V)
MAX
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/°C
%/V
1.0
0
1.8
2.4
3.0
3.6
-40
-20
0
20
40
60
VCC - V
85
TA - ° C
Figure 5-15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
Specifications
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S n - S tepsize R atio betw een D C O Taps
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1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 5-16. DCO Tap Step Size
Legend
f(DCO)
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 5-17. Five Overlapping DCO Ranges Controlled by FN_x Bits
28
Specifications
Copyright © 2006–2015, Texas Instruments Incorporated
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5.20
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Crystal Oscillator, LFXT1 Oscillator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
CXIN
Integrated input capacitance (3)
TEST CONDITIONS
MIN
(2)
TYP
OSCCAPx = 0h, VCC = 2.2 V, 3 V
0
OSCCAPx = 1h, VCC = 2.2 V, 3 V
10
OSCCAPx = 2h, VCC = 2.2 V, 3 V
14
OSCCAPx = 3h, VCC = 2.2 V, 3 V
18
OSCCAPx = 0h, VCC = 2.2 V, 3 V
0
OSCCAPx = 1h, VCC = 2.2 V, 3 V
10
OSCCAPx = 2h, VCC = 2.2 V, 3 V
14
MAX
UNIT
pF
CXOUT
Integrated output capacitance (3)
VIL
Low-level input voltage at XIN
VCC = 2.2 V, 3 V (4)
VSS
0.2 × VCC
V
VIH
High-level input voltage at XIN
VCC = 2.2 V, 3 V (4)
0.8 × VCC
VCC
V
OSCCAPx = 3h, VCC = 2.2 V, 3 V
(1)
(2)
(3)
(4)
pF
18
The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN × CXOUT) / (CXIN+ CXOUT). This is independent of XTS_FLL.
To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
• Keep the trace between the MCU and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
TI recommends external capacitance for precision real-time clock applications; OSCCAPx = 0h.
Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
5.21
Crystal Oscillator, XT2 Oscillator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
CXT2IN
Integrated input capacitance
VCC = 2.2 V, 3 V
2
CXT2OUT
Integrated output capacitance
VCC = 2.2 V, 3 V
2
VIL
Input levels at XT2IN
VIH
(1)
(2)
VCC = 2.2 V, 3 V
(2)
MAX UNIT
pF
pF
VSS
0.2 × VCC
V
0.8 × VCC
VCC
V
The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
5.22
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time UART (1)
(1)
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX UNIT
fSYSTEM MHz
2.2 V, 3 V
1 MHz
2.2 V
50
150
600
3V
50
100
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.23
www.ti.com
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18
and Figure 5-19)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
iSOMI input data hold time
tVALID,MO
SIMO output data valid time
5.24
TEST CONDITIONS
VCC
MIN
SMCLK, ACLK
Duty cycle = 50% ±10%
UCLK edge to SIMO valid, CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
30
3V
20
ns
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20
and Figure 5-21)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V, 3 V
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V, 3 V
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V, 3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V, 3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
30
Specifications
UCLK edge to SOMI valid, CL = 20 pF
50
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
1/fUCx CLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU ,MI
tHD ,MI
SOMI
tVALID ,MO
SIMO
Figure 5-18. SPI Master Mode, CKPH = 0
1/fUC xC LK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tHD ,MI
tSU ,MI
SO MI
tVALID
,MO
SIMO
Figure 5-19. SPI Master Mode, CKPH = 1
Specifications
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31
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tSTE ,LEAD
tSTE ,LAG
STE
1/fUCx CLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU ,SIMO
tHD ,SIMO
SIMO
tACC
tVALID ,SOMI
tDIS
SO MI
Figure 5-20. SPI Slave Mode, CKPH = 0
tSTE ,LEAD
tSTE ,LAG
STE
1/fUCx CLK
CKPL =0
UCLK
CKPL =1
tLOW /HIGH
tLOW /HIGH
tHD ,SI
tSU ,SI
SI MO
tACC
tVALID ,SO
tDIS
SO MI
Figure 5-21. SPI Slave Mode, CKPH = 1
32
Specifications
Copyright © 2006–2015, Texas Instruments Incorporated
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5.25
SLAS508J – APRIL 2006 – REVISED JUNE 2015
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-22)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ±10%
MAX UNIT
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V, 3 V
4
µs
tSP
Pulse duration of spikes suppressed by
input filter
2.2 V
50
150
600
3V
50
100
600
t HD
fSYSTEM MHz
2.2 V, 3 V
0
fSCL ≤ 100 kHz
2.2 V, 3 V
4
fSCL > 100 kHz
2.2 V, 3 V
0.6
fSCL ≤ 100 kHz
2.2 V, 3 V
4.7
fSCL > 100 kHz
2.2 V, 3 V
0.6
tSU
, STA
, STA
t HD
400
kHz
µs
µs
ns
ns
tBUF
, STA
SDA
t
t HIGH
LOW
t SP
SCL
t SU , DAT
tHD
t SU
, STO
, DAT
Figure 5-22. I2C Mode Timing
5.26
USART1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
t(τ)
(1)
USART1 deglitch time
TEST CONDITIONS
MIN
TYP
MAX
VCC = 2.2 V, SYNC = 0, UART mode
200
430
800
VCC = 3 V, SYNC = 0, UART mode
150
280
500
UNIT
ns
The signal applied to the USART1 receive signal (terminal) (URXD1) must meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses that meet the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD1 line.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.27
www.ti.com
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
V(P6.x/Ax)
All external Ax terminals, Analog inputs selected in
Analog input voltage range (2) ADC12MCTLx register, P6Sel.x = 1,
V(AVSS) ≤ VAx ≤ V(AVCC)
IADC12
f
= 5.0 MHz,
Operating supply current into ADC12CLK
ADC12ON = 1, REFON = 0,
AVCC terminal (3)
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
IREF+
fADC12CLK = 5.0 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 1
Operating supply current into
AVCC terminal (4)
fADC12CLK = 5.0 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 0
CI
RI
(1)
(2)
(3)
(4)
TYP
MAX
2.2
3.6
V
0
VAVCC
V
VCC = 2.2 V
0.65
1.3
VCC = 3 V
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
Input capacitance
Only one terminal can be selected at one
time, Ax
VCC = 2.2 V
Input MUX ON resistance
0 V ≤ VAx ≤ VAVCC
VCC = 3 V
UNIT
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
5.28
12-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VeREF+
Positive external reference
voltage input
VeREF+ > VREF–/VeREF–
(2)
1.4
VAVCC
V
VREF–/VeREF–
Negative external reference
voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference
voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
VAVCC
V
IVeREF+
Input leakage current
0 V ≤ VeREF+ ≤ VAVCC
VCC = 2.2 V, 3 V
±1
µA
IVREF–/VeREF–
Input leakage current
0 V ≤ VeREF– ≤ VAVCC
VCC = 2.2 V, 3 V
±1
µA
(1)
(2)
(3)
(4)
34
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Specifications
Copyright © 2006–2015, Texas Instruments Incorporated
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5.29
SLAS508J – APRIL 2006 – REVISED JUNE 2015
12-Bit ADC, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REF2_5V = 1 for 2.5 V,
Positive built in reference voltage IVREF+max ≤ IVREF+ ≤ IVREF+min
output
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
VREF+
AVCC(min)
AVCC minimum voltage, Positive
built in reference active
IL(VREF+)
Load-current regulation, VREF+
terminal
2.5
2.6
1.44
1.5
1.56
2.8
2.9
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
V
VCC = 2.2 V
0.01
–0.5
VCC = 3 V
0.01
–1
VCC = 2.2 V
±2
VCC = 3 V
±2
VCC = 3 V
±2
IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, Ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB
VCC = 3 V
20
REFON = 1,
0 mA ≤ IVREF+ ≤ IVREF+max
VCC = 2.2 V, 3 V
TREF+
Temperature coefficient of builtin reference
tREFON
Settling time of internal reference IVREF+ = 0.5 mA, CVREF+ = 10 µF,
voltage (see Figure 5-23 ) (2)
VREF+ = 1.5 V, VAVCC = 2.2 V
mA
LSB
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
Capacitance at pin VREF+
UNIT
V
VCC = 2.2 V, 3 V
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ – 1 mA
CVREF+
(2)
2.4
2.2
Load current regulation, VREF+
terminal
(1)
MAX
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ –0.5 mA
IDL(VREF+)
(1)
TYP
REF2_5V = 0, IVREF+max ≤ IVREF+ ≤ IVREF+min
Load current out of VREF+
terminal
IVREF+
VCC = 3 V
MIN
5
IVREF+ is a constant in the range of
VCC = 2.2 V, 3 V
0 mA ≤ IVREF+ ≤ 1 mA
10
ns
µF
±100 ppm/°C
17
ms
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10-µF tantalum and 100-nF ceramic.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 mF
tREFON » .66 x CVREF+ [ms] with CVREF+ in mF
10 mF
1 mF
0
1 ms
10 ms
100 ms
tREFON
Figure 5-23. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
Specifications
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35
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
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From
Power
Supply
DVCC1/2
+
DVSS1/2
10 m F
100 nF
AVCC
+
-
MSP430FG461x
AVSS
10 m F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
VREF+ or VeREF+
+
10 m F
Apply
External
Reference
100 nF
VREF-/VeREF-
+
10 m F
100 nF
Figure 5-24. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
From
Power
Supply
DVCC1/2
+
DVSS1/2
10 m F
100 nF
AVCC
+
-
MSP430FG461x
AVSS
10 m F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
VREF+ or VeREF+
+
10 m F
Reference Is Internally
Switched to AVSS
100 nF
100 nF
VREF-/VeREF-
Figure 5-25. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected
36
Specifications
Copyright © 2006–2015, Texas Instruments Incorporated
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5.30
SLAS508J – APRIL 2006 – REVISED JUNE 2015
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC12CLK
fADC12OSC
Internal ADC12
oscillator
tCONVERT
Conversion time
tADC12ON
Turnon settling time
of the ADC
tSample
Sampling time
(1)
(2)
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12
linearity parameters
2.2 V, 3 V
0.45
5
6.3
MHz
ADC12DIV = 0,
fADC12CLK = fADC12OSC
2.2 V, 3 V
3.7
5
6.3
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V, 3 V
2.06
External fADC12CLK from ACLK, MCLK, or
SMCLK,
ADC12SSEL ≠ 0
3.51
µs
13 × ADC12DIV
× 1/fADC12CLK
(1)
100
RS = 400 Ω,RI = 1000 Ω,
CI = 30pF, τ = [RS +RI] × CI
(2)
3V
1220
2.2 V
1400
ns
ns
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
5.31
12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
EI
Integral linearity
error
1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V
ED
Differential linearity
error
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EO
Offset error
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EG
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted
error
(VeREF+ -– VREF–/VeREF– )min ≤ (VeREF+ –VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ [VAVCC]
MIN
TYP
MAX
±2
2.2 V, 3 V
±1.7
LSB
±1
LSB
±2
±4
LSB
2.2 V, 3 V
±1.1
±2
LSB
2.2 V, 3 V
±2
±5
LSB
Specifications
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UNIT
37
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.32
www.ti.com
12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Operating supply current
into AVCC terminal (1)
ISENSOR
(2)
VSENSOR
TCSENSOR
TEST CONDITIONS
VCC
REFON = 0, INCH = 0Ah,
ADC12ON = N/A, TA = 25°C
MIN
TYP
MAX
2.2 V
40
120
3V
60
160
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V, 3 V
986
ADC12ON = 1, INCH = 0Ah
2.2 V, 3 V
30
3V
30
tSENSOR(sample)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC12ON = 1, INCH = 0Bh
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
mV/°C
µs
2.2 V
N/A (4)
3V
N/A (4)
1.1
3V
µA
mV
3.55 ±3%
2.2 V
Sample time required if
channel 10 is selected (3)
UNIT
1.1 ±0.04
1.5 1.50 ±0.04
µA
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
5.33
12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply voltage
Supply current, single DAC
channel (1) (2)
IDD
TEST CONDITIONS
VCC
AVCC = DVCC, AVSS = DVSS = 0 V
PSRR
(1)
(2)
(3)
(4)
38
TYP
MAX
UNIT
3.60
V
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
50
110
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
50
110
200
440
700
1500
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
2.2 V, 3 V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
Power-supply rejection
ratio (3) (4)
MIN
2.20
DAC12_xDAT = 800h, VREF = 1.5 V,
ΔAVCC = 100 mV
DAC12_×DAT = 800h, VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
µA
2.2 V
70
dB
3V
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.
PSRR = 20 × log{ΔAVCC/ΔVDAC12_xOUT}.
VREF is applied externally. The internal reference is not used.
Specifications
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5.34
SLAS508J – APRIL 2006 – REVISED JUNE 2015
12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-26)
PARAMETER
TEST CONDITIONS
Resolution
DNL
Differential nonlinearity
MIN
12-bit monotonic
Integral nonlinearity (1)
INL
VCC
(1)
Offset voltage without calibration
(1) (2)
EO
Offset voltage with calibration (1)
(2)
dE(O)/dT
Offset error temperature coefficient (1)
EG
Gain error (1)
dE(G)/dT
Gain temperature coefficient (1)
tOffset_Cal
Time for offset calibration (3)
TYP
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
bits
±2.0
±8.0
LSB
±0.4
±1.0
LSB
±21
mV
±2.5
2.2 V, 3 V
VREF = 1.5 V
2.2 V
VREF = 2.5 V
3V
±30
µV/°C
±3.5
2.2 V, 3 V
%FSR
ppm of
FSR/°C
10
100
DAC12AMPx = 3, 5
2.2 V, 3 V
32
DAC12AMPx = 4, 6, 7
(2)
(3)
UNIT
12
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
DAC12AMPx = 2
(1)
MAX
ms
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of
the first order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. TI recommends that the DAC12 module be configured before initiating calibration. Port activity during calibration may effect
accuracy and is not recommended.
DAC VOUT
DAC Output
V R+
R Load =
Ideal transfer
function
AVCC
2
Offset Error
C Load = 100pF
Gain Error
Positive
Negative
DAC Code
Figure 5-26. Linearity Test Load Conditions and Gain and Offset Definition
Specifications
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INL – Integral Nonlinearity Error – LSB
4
VCC = 2.2 V, VREF = 1.5 V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-1
-2
-3
-4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT – Digital Code
Figure 5-27. Typical INL Error vs Digital Input Data
DNL - Differential Nonlinearity Error - LSB
2.0
VCC = 2.2 V, VREF = 1/.5 V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT - Digital Code
Figure 5-28. Typical DNL Error vs Digital Input Data
40
Specifications
Copyright © 2006–2015, Texas Instruments Incorporated
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5.35
SLAS508J – APRIL 2006 – REVISED JUNE 2015
12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Output voltage range (see
Figure 5-29) (1)
VO
No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
Max DAC12 load
capacitance
IL(DAC12)
Max DAC12 load current
0
0.005
AVCC –
0.05
AVCC
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
AVCC –
0.13
AVCC
2.2 V, 3 V
RLoad = 3 kΩ,
VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh
Output resistance (see
Figure 5-29)
100
2.2 V
–0.5
+0.5
3V
–1.0
+1.0
2.2 V, 3 V
150
250
150
250
1
4
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1)
UNIT
V
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC12)
MAX
2.2 V, 3 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
TYP
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
R O/P(DAC12_x)
Max
R Load
I Load
AVCC
DAC12
2
C Load = 100pF
O/P(DAC12_x)
Min
0.3
AVCC -0.3V
V OUT
AVCC
Figure 5-29. DAC12_x Output Resistance Tests
5.36
12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
Reference input voltage
range
TEST CONDITIONS
DAC12IR = 0 (1)
(2)
DAC12IR = 1 (3)
(4)
VCC
2.2 V, 3 V
DAC12_0 IR = DAC12_1 IR = 0
(1)
(2)
(3)
(4)
(5)
Reference input resistance
DAC12_0 IR = 0, DAC12_1 IR = 1
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1
SREFx (5)
TYP
MAX
AVCC/3
AVCC + 0.2
AVCC
AVCC + 0.2
20
DAC12_0 IR = 1, DAC12_1 IR = 0
Ri(VREF+),
(Ri(VeREF+)
MIN
UNIT
V
MΩ
40
48
56
20
24
28
2.2 V, 3 V
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.37
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12-Bit DAC, Dynamic Specifications
Vref = VCC, DAC12IR = 1, over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted) (see Figure 5-30 and Figure 5-31)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1)
(see Figure 5-30)
DAC12 on time
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
DAC12_xDAT =
80h→F7Fh→80h
Settling time, full scale
DAC12AMPx = 3,5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C–C)
Settling time, code to code
DAC12_xDAT =
3F8h→408h→3F8h
BF8h→C08h→BF8h
DAC12AMPx = 2
DAC12_xDAT =
80h→F7Fh→80h (2)
Slew rate
DAC12AMPx = 3,5
2.2 V, 3 V
30
6
12
100
200
40
80
15
30
2.2 V, 3 V
0.05
0.12
0.35
0.7
1.5
DAC12AMPx = 2
µs
µs
µs
V/µs
2.7
600
DAC12AMPx = 3,5
2.2 V, 3 V
150
DAC12AMPx = 4, 6, 7
(1)
(2)
15
UNIT
1
DAC12AMPx = 3,5
DAC12_xDAT =
80h→F7Fh→80h
120
2
DAC12AMPx = 4, 6, 7
DAC12AMPx = 4, 6, 7
Glitch energy, full-scale
60
5
DAC12AMPx = 2
SR
TYP MAX
nV-s
30
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-30.
Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
V OUT
DAC Output
I Load
R Load = 3 k W
Conversion 2
Conversion 3
+/- 1/2 LSB
Glitch
Energy
AVCC
2
R O/P(DAC12.x)
+/- 1/2 LSB
C Load = 100pF
t settleLH
t settleHL
Figure 5-30. Settling Time and Glitch Energy Testing
Conversion 1
Conversion 2
Conversion 3
V OUT
90%
90%
10%
10%
t SRLH
t SRHL
Figure 5-31. Slew Rate Testing
42
Specifications
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5.38
SLAS508J – APRIL 2006 – REVISED JUNE 2015
12-Bit DAC, Dynamic Specifications Continued
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
BW–3dB
3-dB bandwidth,
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
VDC = 1.5 V, VAC = 0.1 VPP
DAC12IR = 1, DAC12_xDAT = 800h
(see Figure 5-32)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
(1)
MAX
UNIT
40
2.2 V, 3 V
180
kHz
550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h↔F7Fh, RLoad = 3 kΩ
fDAC12_1OUT = 10 kHz at 50/50 duty cycle
Channel-to-channel
crosstalk
(see Figure 5-33) (1)
TYP
–80
2.2 V, 3 V
DAC12_0DAT = 80h↔F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No Load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle
dB
–80
RLOAD = 3 kΩ, CLOAD = 100 pF
I Load
VeREF+
R Load = 3 k W
AVCC
DAC12_x
2
DACx
AC
C Load = 100pF
DC
Figure 5-32. Test Conditions for 3-dB Bandwidth Specification
I Load
R Load
AVCC
2
DAC12_0
DAC0
DAC12_xDAT
080h
080h
F7Fh
F7Fh
080h
V OUT
C Load = 100 pF
VREF+
I Load
V DAC12_yOUT
R Load
AVCC
2
DAC12_1
DAC1
V DAC12_xOUT
1/fToggle
C Load = 100 pF
Figure 5-33. Crosstalk Test Conditions
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.39
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Operational Amplifier OA, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
MIN
TYP
MAX
Fast Mode, OARRIP = 1 (rail-to-rail mode off)
180
290
Medium Mode, OARRIP = 1 (rail-to-rail mode off)
110
190
50
80
300
490
190
350
90
190
Supply voltage
Supply current (1)
ICC
2.2
Slow Mode, OARRIP = 1 (rail-to-rail mode off)
2.2 V, 3 V
Fast Mode, OARRIP = 0 (rail-to-rail mode on)
Medium Mode, OARRIP = 0 (rail-to-rail mode on)
Slow Mode, OARRIP = 0 (rail-to-rail mode on)
PSRR Power supply rejection ratio
(1)
Noninverting
2.2 V, 3 V
3.6
70
UNIT
V
µA
dB
P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
5.40
Operational Amplifier OA, Input/Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VI/P
Voltage supply, I/P
IIkg
Input leakage current, I/P (1)
TEST CONDITIONS
(2)
VCC
MIN
VCC – 1.2
OARRIP = 0 (rail-to-rail mode on)
–0.1
VCC + 0.1
TA = –40 to +55°C
–5
±0.5
5
TA = +55 to +85°C
–20
±5
20
Medium Mode
Voltage noise density, I/P
140
Fast Mode
30
fV(I/P) = 10 kHz
Offset voltage, I/P
Offset voltage drift with supply,
I/P
VOH
High-level output voltage, O/P
VOL
Low-level output voltage, O/P
Output resistance (see
Figure 5-34) (4)
(3)
0.3 V ≤ VIN ≤ VCC – 0.3 V
ΔVCC ≤ ±10%, TA = 25°C
(1)
(2)
(3)
(4)
44
Common-mode rejection ratio
nV/√HZ
65
2.2 V, 3 V
±10
2.2 V, 3 V
±10
2.2 V, 3 V
±1.5
2.2 V
VCC – 0.2
VCC
Slow Mode, ISOURCE ≤ –150 µA
3V
VCC – 0.1
VCC
Fast Mode, ISOURCE ≤ +500 µA
2.2 V
VSS
0.2
Slow Mode, ISOURCE ≤ +150 µA
3V
VSS
0.1
RLoad = 3 kΩ, CLoad = 50 pF,
OARRIP = 0 (rail-to-rail mode on),
VO/P(OAx) > AVCC – 0.2 V
2.2 V, 3 V
Noninverting
2.2 V, 3 V
mV
µV/°C
Fast Mode, ISOURCE ≤ –500 µA
RLoad = 3 kΩ, CLoad = 50 pF,
OARRIP = 0 (rail-to-rail mode on),
0.2 V ≤ VO/P(OAx) ≤ AVCC – 0.2 V
CMRR
nA
50
RLoad = 3 kΩ, CLoad = 50 pF,
OARRIP = 0 (rail-to-rail mode on),
VO/P(OAx) < 0.2 V
RO/P (OAx)
V
80
fV(I/P) = 1 kHz
Slow Mode
Offset temperature drift, I/P
UNIT
50
Slow Mode
Medium Mode
VIO
MAX
–0.1
Fast Mode
Vn
TYP
OARRIP = 1 (rail-to-rail mode off)
150
250
150
250
0.1
4
70
mV/V
V
V
Ω
dB
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method.
Specification valid for voltage-follower OAx configuration.
Specifications
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
R O/P(OAx)
Max
R Load
I Load
AVCC
2
OAx
C Load
O/P(OAx)
Min
0.2V
AVCC -0.2V AV
V OUT
CC
Figure 5-34. OAx Output Resistance Tests
5.41
Operational Amplifier OA, Dynamic Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SR
TEST CONDITIONS
Slew rate
VCC
MIN
Fast Mode
1.2
Medium Mode
0.8
Slow Mode
0.3
Open-loop voltage gain
φm
GBW
TYP
MAX
UNIT
V/µs
100
dB
Phase margin
CL = 50 pF
60
deg
Gain margin
CL = 50 pF
20
dB
ten(on)
Enable time on
ten(off)
Enable time off
2.2
Noninverting, Fast Mode, RL = 47 kΩ, CL = 50 pF
Gain-bandwidth product
(see Figure 5-35 and
Figure 5-36)
Noninverting, Medium Mode, RL = 300 kΩ, CL = 50 pF
1.4
2.2 V, 3 V
0.5
Noninverting, Slow Mode, RL = 300 kΩ, CL = 50 pF
ton, Noninverting, Gain = 1
MHz
2.2 V, 3 V
10
2.2 V, 3 V
20
µs
1
µs
5.42 Operational Amplifier OA, Typical Characteristics
0
140
120
Fast Mode
100
-50
80
Phase - degrees
Medium Mode
Gain = dB
60
40
20
0
Slow Mode
Fast Mode
-100
Medium Mode
-150
Slow Mode
-20
-200
-40
-60
-80
0.001
0.01
0.1
1
10
100
1000 10000
Input Frequency - kHz
Figure 5-35. Typical Open-Loop Gain vs Frequency
-250
1
10
100
1000
10000
Input Frequency - kHz
Figure 5-36. Typical Phase vs Frequency
Specifications
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5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
G
Gain
TEST CONDITIONS
VCC
MIN
MAX
OAFBRx = 0
0.996
1.00
1.002
OAFBRx = 1
1.329
1.334
1.340
OAFBRx = 2
1.987
2.001
2.016
OAFBRx = 3
2.64
2.667
2.70
OAFBRx = 4
2.2 V, 3 V
3.93
4.00
4.06
OAFBRx = 5
5.22
5.33
5.43
OAFBRx = 6
7.76
7.97
8.18
15.0
15.8
16.6
OAFBRx = 7
THD
Total harmonic distortion and nonlinearity
All gains
tSettle
Settling time (1)
All power modes
(1)
TYP
2.2 V
–60
3V
–70
2.2 V, 3 V
UNIT
dB
7
12
µs
The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6) (1)
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
G
Gain
MIN
TYP
MAX
OAFBRx = 1
TEST CONDITIONS
–0.371
–0.335
–0.298
OAFBRx = 2
–1.031
–1.002
–0.972
OAFBRx = 3
–1.727
–1.668
–1.609
–3.142
–3.00
–2.856
OAFBRx = 5
–4.581
–4.33
–4.073
OAFBRx = 6
–7.529
–6.97
–6.379
OAFBRx = 7
–17.040
–14.8
–12.279
OAFBRx = 4
THD
Total harmonic distortion and nonlinearity
All gains
tSettle
Settling time (2)
All power modes
(1)
(2)
46
VCC
2.2 V, 3 V
2.2 V
–60
3V
–70
2.2 V, 3 V
7
UNIT
dB
12
µs
This includes the two OA configuration "inverting amplifier with input buffer". Both OAs need to be set to the same power mode, OAPMx.
The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
Specifications
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5.45
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Flash Memory (FG461x Devices Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.7
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
5
mA
2.7 V, 3.6 V
3
IERASE
Supply current from DVCC during erase
(1)
2.7 V, 3.6 V
3
7
mA
IGMERASE
Supply current from DVCC during global mass erase
(2)
2.7 V, 3.6 V
6
14
mA
tCPT
Cumulative program time
(3)
2.7 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.7 V, 3.6 V
20
ms
104
Program and erase endurance
tRetention
Data retention duration
tWord
Word or byte program time
30
Block program time for 1st byte or word
25
tBlock,
0
TJ = 25°C
105
100
years
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
10593
tGlobal Mass Erase
Global mass erase time
10593
tSeg Erase
Segment erase time
(1)
(2)
(3)
(4)
cycles
18
(4)
6
tFTG
4819
Lower 64KB or upper 64KB flash memory erased.
All flash memory erased.
The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
These values are hardwired into the flash controller state machine (tFTG = 1/fFTG).
5.46
JTAG Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTCK
TCK input frequency
(1)
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
(2)
(1)
(2)
VCC
MIN
TYP
MAX
2.2 V
0
5
3V
0
10
2.2 V, 3 V
25
60
90
UNIT
MHz
kΩ
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
5.47
JTAG Fuse (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow (FG461x)
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
Specifications
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6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The MSP430xG461x device family uses the MSP430X CPU and is completely backwards compatible with
the MSP430 CPU. For a complete description of the MSP430X CPU, refer to the MSP430x4xx Family
User’s Guide (SLAU056).
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
48
Detailed Description
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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6.2
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 shows examples of the three types of instruction formats; the address modes are
listed in Table 6-2.
Table 6-1. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC→ (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, un/conditional
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
•
•
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
•
•
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)→ M(6+R6)
Symbolic (PC relative)
•
•
MOV EDE,TONI
Absolute
•
•
MOV & MEM, & TCDAT
Indirect
•
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
•
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2→ R10
Immediate
•
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
NOTE: S = source D = destination
Detailed Description
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6.3
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Operating Modes
These devices have one active mode and five software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– FLL+ loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL+ loop control is disabled
– ACLK and SMCLK remain active. MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL+ loop control and DCOCLK are disabled
– DCO DC generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO DC generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO DC generator is disabled
– Crystal oscillator is stopped
50
Detailed Description
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6.4
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV (1) (2)
Reset
0FFFEh
31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (1) (3)
OFIFG (1) (3)
ACCVIFG (1) (4) (2)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
30
Timer_B7
TBCCR0 CCIFG0 (4)
Maskable
0FFFAh
29
Timer_B7
TBCCR1 CCIFG1 to TBCCR6 CCIFG6,
TBIFG (1) (4)
Maskable
0FFF8h
28
Comparator_A
CAIFG
Maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
Maskable
0FFF4h
26
Maskable
0FFF2h
25
Maskable
0FFF0h
24
Maskable
0FFEEh
23
Maskable
0FFECh
22
Maskable
0FFEAh
21
Maskable
0FFE8h
20
USCI_A0, USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG
(1)
USCI_A0, USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG
(1)
ADC12
ADC12IFG
Timer_A3
Timer_A3
I/O Port P1 (Eight Flags)
TACCR0 CCIFG0
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (1) (4)
P1IFG.0 to P1IFG.7 (1)
(4)
USART1 Receive
URXIFG1
Maskable
0FFE6h
19
UTXIFG1
Maskable
0FFE4h
18
Maskable
0FFE2h
17
Maskable
0FFE0h
16
Maskable
0FFDEh
15
Maskable
0FFDCh
14
0FFDAh
13
P2IFG.0 to P2IFG.7
Basic Timer 1, RTC
(1) (4)
BTIFG
DMA
DMA0IFG, DMA1IFG, DMA2IFG (1)
DAC12
DAC12.0IFG, DAC12.1IFG (1)
Reserved
(4)
(5)
(4)
USART1 Transmit
I/O Port P2 (Eight Flags)
(1)
(2)
(3)
(1) (4)
Reserved
(5)
(4)
(4)
⋮
⋮
0FFC0h
0, lowest
Multiple source flags
Access and key violations, KEYV and ACCVIFG, only applicable to FG devices.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Detailed Description
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6.5
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Special Function Registers (SFRs)
The MSP430 SFRs are in the lowest address space and are organized as byte mode registers. SFRs
should be accessed with byte instructions.
Legend
rw
Bit can be read and written.
rw-0, rw-1
Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-(1)
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
6.5.1
Interrupt Enable 1 and 2
7
Address
6
0h
5
4
ACCVIE
rw*0
3
2
NMIIE
1
OFIE
rw*0
rw*0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE
Oscillator fault-interrupt enable
NMIIE
Nonmaskable interrupt enable
ACCVIE
Flash access violation interrupt enable
7
BTIE
01h
6
5
UTXIE1
rw*0
rw*0
4
URXIE1
rw*0
3
UCB0TXIE
rw*0
2
UCB0RXIE
rw*0
WDTIE
rw*0
WDTIE
Address
0
1
UCA0TXIE
rw*0
0
UCA0RXIE
rw*0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
52
URXIE1
USART1 UART and SPI receive-interrupt enable
UTXIE1
USART1 UART and SPI transmit-interrupt enable
BTIE
Basic timer interrupt enable
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6.5.2
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Interrupt Flag Register 1 and 2
7
Address
6
5
02h
4
3
2
NMIIFG
1
0
OFIFG
rw*0
rw*1
WDTIFG
rw*(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG
Flag set on oscillator fault
NMIIFG
Set by the RST/NMI pin
7
Address
03h
6
5
UTXIFG1
BTIFG
rw*1
rw*0
4
URXIFG1
3
UCB0TXIFG
rw*0
rw*0
2
UCB0RXIFG
1
UCA0TXIFG
rw*0
rw*0
0
UCA0RXIFG
rw*0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG
USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG
USCI_B0 transmit-interrupt flag
URXIFG0
USART1: UART and SPI receive flag
UTXIFG0
USART1: UART and SPI transmit flag
BTIFG
Basic timer flag
6.5.3
Module Enable Registers 1 and 2
7
Address
6
5
4
3
2
1
0
2
1
0
04h
URXE1
USART1: UART mode receive enable
UTXE1
USART1: UART mode transmit enable
USPIE1
USART1: SPI mode transmit and receive enable
7
Address
6
5
UTXE1
05h
rw*0
4
3
URXE1
USPIE1
rw*0
URXE1
USART1: UART mode receive enable
UTXE1
USART1: UART mode transmit enable
USPIE1
USART1: SPI mode transmit and receive enable
Detailed Description
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.6
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Memory Organization
Table 6-4 summarizes the memory organization for the FG461x devices, and Table 6-5 summarizes the
memory organization for the CG461x devices.
Table 6-4. MSP430FG461x Memory Organization
MSP430FG4616
MSP430FG4617
MSP430FG4618
MSP430FG4619
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
92KB
0FFFFh-0FFC0h
018FFFh-002100h
92KB
0FFFFh-0FFC0h
019FFFh-003100h
116KB
0FFFFh-0FFC0h
01FFFFh-003100h
120KB
0FFFFh-0FFC0h
01FFFFh-002100h
RAM
Total
Size
4KB
020FFh-01100h
8KB
030FFh-01100h
8KB
030FFh-01100h
4KB
020FFh-01100h
Extended
Size
2KB
020FFh-01900h
6KB
030FFh-01900h
6KB
030FFh-01900h
2KB
020FFh-01900h
Mirrored
Size
2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
Information memory
Size
Flash
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Boot memory
Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
RAM
(Mirrored at 018FFh01100h)
Size
2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
16 bit
8 bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
Peripherals
Table 6-5. MSP430CG461x Memory Organization
MSP430CG4616
MSP430CG4617
MSP430CG4618
MSP430CG4619
Memory
Main: interrupt vector
Main: code memory
Size
ROM
ROM
92KB
0FFFFh-0FFC0h
018FFFh-002100h
92KB
0FFFFh-0FFC0h
019FFFh-003100h
116KB
0FFFFh-0FFC0h
01FFFFh-003100h
120KB
0FFFFh-0FFC0h
01FFFFh-002100h
RAM
Total
Size
4KB
020FFh-01100h
8KB
030FFh-01100h
8KB
030FFh-01100h
4KB
020FFh-01100h
Extended
Size
2KB
020FFh-01900h
6KB
030FFh-01900h
6KB
030FFh-01900h
2KB
020FFh-01900h
Mirrored
Size
2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
2KB
018FFh-01100h
Information memory
Size
ROM
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Boot memory
(Optional on CG)
Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
RAM
(Mirrored at 018FFh01100h)
Size
2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
2KB
09FFh-0200h
16 bit
8 bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
Peripherals
54
Detailed Description
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6.7
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Bootstrap Loader (BSL)
The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU
memory through the BSL is protected by user-defined password. A bootstrap loader security key is
provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an
invalid password is supplied. The BSL is optional for ROM-based devices. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader (SLAA089).
6.8
BSLKEY
DESCRIPTION
00000h
Erasure of flash disabled if an invalid password
is supplied
0AA55h
BSL disabled
any other value
BSL enabled
BSL FUNCTION
PZ/ZQW PACKAGE PINS
Data Transmit
87/A7 – P1.0
Data Receiver
86/E7 – P1.1
Flash Memory
The flash memory can be programmed by the JTAG port, the bootstrap loader, or in system by the CPU.
The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash
memory include:
• Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A and B can be erased individually, or as a group with segments 0-n. Segments A and B
are also called information memory.
• New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory before the first use.
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s
Guide.
6.9.1
DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12 conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode without
having to awaken to move data to or from a peripheral.
Detailed Description
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6.9.2
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Oscillator and System Clock
The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which
includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO),
and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of
both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable
multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and
stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
• Main clock (MCLK), the system clock used by the CPU
• Submain clock (SMCLK), the subsystem clock used by the peripheral modules
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
6.9.3
Brownout, Supply Voltage Supervisor (SVS)
The brownout circuit provides the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both
supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is
not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may
not have ramped to VCC(min) at that time. The user must make sure the default FLL+ settings are not
changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC
reaches VCC(min).
6.9.4
Digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions
• Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB, respectively.
6.9.5
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter.
Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated realtime clock (RTC). An internal calendar compensates for months with less than 31 days and includes leapyear correction.
6.9.6
LCD_A Drive With Regulated Charge Pump
The LCD_A driver generates the segment and common signals required to drive a segment LCD display.
The LCD_A controller has dedicated data memory to hold segment drive information. Common and
segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are
supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage
with its integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and,
thus, contrast by software.
6.9.7
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
56
Detailed Description
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6.9.8
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols like
UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3-pin or 4-pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3-pin or 4-pin) and I2C.
6.9.9
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used
for serial data communication. The USART supports synchronous SPI (3-pin or 4-pin) and asynchronous
UART communication protocols, using double-buffered transmit and receive channels.
6.9.10 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles
are required.
6.9.11 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-6. Timer_A3 Signal Connections
INPUT PIN NUMBER
PZ/ZQW
82/B9 - P1.5
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
82/B9 - P1.5
TACLK
INCLK
87/A7 - P1.0
TA0
CCI0A
86/E7 - P1.1
85/D7 - P1.2
79/A10 - P2.0
TA0
CCI0B
DVSS
GND
DVCC
VCC
MODULE BLOCK
Timer
MODULE OUT
SIGNAL
OUTPUT PIN
NUMBER
PZ/ZQW
NA
87/A7 - P1.0
CCR0
TA0
TA1
CCI1A
85/D7 - P1.2
CAOUT (internal)
CCI1B
ADC12 (internal)
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR1
TA1
79/A10 - P2.0
CCR2
TA2
Detailed Description
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6.9.12 Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-7. Timer_B7 Signal Connections
INPUT PIN NUMBER
PZ/ZQW
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TBCLK
TBCLK
83/B8 - P1.4
ACLK
SMCLK
SMCLK
Timer
MODULE OUT
SIGNAL
OUTPUT PIN
NUMBER
PZ/ZQW
NA
83/B8 - P1.4
TBCLK
INCLK
78/D8 - P2.1
TB0
CCI0A
78/D8 - P2.1
78/D8 - P2.1
TB0
CCI0B
ADC12 (internal)
DVSS
GND
CCR0CCR0
TB0TB0
DVCC
VCC
77/E8 - P2.2
TB1
CCI1A
77/E8 - P2.2
77/E8 - P2.2
TB1
CCI1B
ADC12 (internal)
DVSS
GND
76/A11 - P2.3
76/A11 - P2.3
67/E12 - P3.4
67/E12 - P3.4
DVCC
VCC
TB2
CCI2A
TB2
CCI2B
DVSS
GND
DVCC
VCC
TB3
CCI3A
TB3
CCI3B
DVSS
GND
DVCC
VCC
66/G9 - P3.5
TB4
CCI4A
66/G9 - P3.5
TB4
CCI4B
DVSS
GND
DVCC
VCC
65/F11 - P3.6
TB5
CCI5A
65/F11 - P3.6
TB5
CCI5B
DVSS
GND
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
64/F12 - P3.7
58
ACLK
MODULE BLOCK
Detailed Description
CCR1
TB1
76/A11 - P2.3
CCR2
TB2
67/E12 - P3.4
CCR3
TB3
66/G9 - P3.5
CCR4
TB4
65/F11 - P3.6
CCR5
TB5
64/F12 - P3.7
CCR6
TB6
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.9.13 Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital
conversions, battery-voltage supervision, and monitoring of external analog signals.
6.9.14 ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
6.9.15 DAC12
The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 can be used in 8-bit or 12-bit
mode and can be used in conjunction with the DMA controller. When multiple DAC12 modules are
present, they may be grouped together for synchronous operation.
6.9.16 OA
The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA
input and output terminal is software-selectable and offer a flexible choice of connections for various
applications. The OA op amps primarily support front-end analog signal conditioning before analog-todigital conversion.
Table 6-8. OA Signal Connections
INPUT PIN
NUMBER
PZ
95 - P6.0
97 - P6.2
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
OA0I0
OA0I0
OA0I1
OA0I1
MODULE BLOCK
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
OUTPUT PIN
NUMBER
PZ
OA0O
96 - P6.1
OA0O
ADC12 (internal)
DAC12_0OUT
(internal)
DAC12_0OUT
DAC12_1OUT
(internal)
DAC12_1OUT
3- P6.4
OA1I0
OA1I0
OA1O
2- P6.3
13 - P5.0
OA1I1
OA1I1
OA1O
13- P5.0
DAC12_0OUT
(internal)
DAC12_0OUT
OA1O
ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT
5- P6.6
OA2I0
OA2I0
OA2O
4- P6.5
14 - P10.7
OA2I1
OA2I1
OA2O
14 - P10.7
DAC12_0OUT
(internal)
DAC12_0OUT
OA2O
ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT
OA0
OA1
OA2
OA0OUT
OA1OUT
OA2OUT
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6.9.17 Peripheral File Map
Table 6-9 lists the registers and addresses for peripherals with word access. Table 6-10 lists the registers
and addresses for peripherals with byte access.
Table 6-9. Peripherals With Word Access
MODULE
REGISTER NAME
ACRONYM
ADDRESS
Watchdog+
Watchdog timer control
WDTCTL
0120h
Timer_B7
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
Timer_B interrupt vector
TBCCR6
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
TBIV
019Eh
019Ch
019Ah
0198h
0196h
0194h
0192h
0190h
018Eh
018Ch
018Ah
0188h
0186h
0184h
0182h
0180h
011Eh
Timer_A3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
Timer_A interrupt vector
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
Hardware Multiplier
Sum extend
Result high word
Result low word
Second operand
Multiply signed + accumulate/operand1
Multiply + accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
SUMEXT
RESHI
RESLO
OP2
MACS
MAC
MPYS
MPY
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
Flash
(FG devices only)
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
DMA
DMA module control 0
DMA module control 1
DMA interrupt vector
DMACTL0
DMACTL1
DMAIV
0122h
0124h
0126h
DMA Channel 0
DMA
DMA
DMA
DMA
channel
channel
channel
channel
0
0
0
0
control
source address
destination address
transfer size
DMA0CTL
DMA0SA
DMA0DA
DMA0SZ
01D0h
01D2h
01D6h
01DAh
DMA Channel 1
DMA
DMA
DMA
DMA
channel
channel
channel
channel
1
1
1
1
control
source address
destination address
transfer size
DMA1CTL
DMA1SA
DMA1DA
DMA1SZ
01DCh
01DEh
01E2h
01E6h
DMA Channel 2
DMA
DMA
DMA
DMA
channel
channel
channel
channel
2
2
2
2
control
source address
destination address
transfer size
DMA2CTL
DMA2SA
DMA2DA
DMA2SZ
01E8h
01EAh
01EEh
01F2h
60
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 6-9. Peripherals With Word Access (continued)
MODULE
REGISTER NAME
ACRONYM
ADDRESS
ADC12
See also Table 6-10
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
Control register 1
Control register 0
ADC12MEM15
ADC12MEM14
ADC12MEM13
ADC12MEM12
ADC12MEM11
ADC12MEM10
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
ADC12IV
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
015Eh
015Ch
015Ah
0158h
0156h
0154h
0152h
0150h
014Eh
014Ch
014Ah
0148h
0146h
0144h
0142h
0140h
01A8h
01A6h
01A4h
01A2h
01A0h
DAC12
DAC12_1 data
DAC12_1 control
DAC12_0 data
DAC12_0 control
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
01CAh
01C2h
01C8h
01C0h
Port PA
Port
Port
Port
Port
PA
PA
PA
PA
selection
direction
output
input
PASEL
PADIR
PAOUT
PAIN
03Eh
03Ch
03Ah
038h
Port PB
Port
Port
Port
Port
PB
PB
PB
PB
selection
direction
output
input
PBSEL
PBDIR
PBOUT
PBIN
00Eh
00Ch
00Ah
008h
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
61
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Table 6-10. Peripherals With Byte Access
MODULE
REGISTER NAME
ACRONYM
ADDRESS
OA2
Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA2CTL1
OA2CTL0
0C5h
0C4h
OA1
Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0
Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
ADC12
(Memory control registers
require byte access)
ADC memory-control register 15
ADC memory-control register 14
ADC memory-control register 13
ADC memory-control register 12
ADC memory-control register 11
ADC memory-control register 10
ADC memory-control register 9
ADC memory-control register 8
ADC memory-control register 7
ADC memory-control register 6
ADC memory-control register 5
ADC memory-control register 4
ADC memory-control register 3
ADC memory-control register 2
ADC memory-control register 1
ADC memory-control register 0
ADC12MCTL15
ADC12MCTL14
ADC12MCTL13
ADC12MCTL12
ADC12MCTL11
ADC12MCTL10
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
08Fh
08Eh
08Dh
08Ch
08Bh
08Ah
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
USART1
Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
U1TXBUF
U1RXBUF
U1BR1
U1BR0
U1MCTL
U1RCTL
U1TCTL
U1CTL
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
078h
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
USCI
UCBI2CSA
UCBI2COA
UCBTXBUF
UCBRXBUF
UCBSTAT
UCBI2CIE
UCBBR1
UCBBR0
UCBCTL1
UCBCTL0
UCATXBUF
UCARXBUF
UCASTAT
UCAMCTL
UCABR1
UCABR0
UCACTL1
UCACTL0
UCAIRRCTL
UCAIRTCTL
UCAABCTL
011Ah
0118h
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
Comparator_A
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
62
Detailed Description
I2C Slave Address
I2C Own Address
Synchronous Transmit Buffer
Synchronous Receive Buffer
Synchronous Status
I2C Interrupt Enable
Synchronous Bit Rate 1
Synchronous Bit Rate 0
Synchronous Control 1
Synchronous Control 0
Transmit Buffer
Receive Buffer
Status
Modulation Control
Baud Rate 1
Baud Rate 0
Control 1
Control 0
IrDA Receive Control
IrDA Transmit Control
LIN Control
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 6-10. Peripherals With Byte Access (continued)
MODULE
REGISTER NAME
ACRONYM
ADDRESS
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
FLL+Clock
FLL+ Control 1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0
054h
053h
052h
051h
050h
RTC
(Basic Timer 1)
Real Time Clock Year High Byte
Real Time Clock Year Low Byte
Real Time Clock Month
Real Time Clock Day of Month
Basic Timer1 Counter 2
Basic Timer1 Counter 1
Real Time Counter 4
(Real Time Clock Day of Week)
Real Time Counter 3
(Real Time Clock Hour)
Real Time Counter 2
(Real Time Clock Minute)
Real Time Counter 1
(Real Time Clock Second)
Real Time Clock Control
Basic Timer1 Control
RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(RTCMIN)
RTCNT1
(RTCSEC)
RTCCTL
BTCTL
04Fh
04Eh
04Dh
04Ch
047h
046h
045h
044h
043h
042h
041h
040h
Port P10
Port
Port
Port
Port
P10 selection
P10 direction
P10 output
P10 input
P10SEL
P10DIR
P10OUT
P10IN
00Fh
00Dh
00Bh
009h
Port P9
Port
Port
Port
Port
P9
P9
P9
P9
selection
direction
output
input
P9SEL
P9DIR
P9OUT
P9IN
00Eh
00Ch
00Ah
008h
Port P8
Port
Port
Port
Port
P8
P8
P8
P8
selection
direction
output
input
P8SEL
P8DIR
P8OUT
P8IN
03Fh
03Dh
03Bh
039h
Port P7
Port
Port
Port
Port
P7
P7
P7
P7
selection
direction
output
input
P7SEL
P7DIR
P7OUT
P7IN
03Eh
03Ch
03Ah
038h
Port P6
Port
Port
Port
Port
P6
P6
P6
P6
selection
direction
output
input
P6SEL
P6DIR
P6OUT
P6IN
037h
036h
035h
034h
Port P5
Port
Port
Port
Port
P5
P5
P5
P5
selection
direction
output
input
P5SEL
P5DIR
P5OUT
P5IN
033h
032h
031h
030h
Port P4
Port
Port
Port
Port
P4
P4
P4
P4
selection
direction
output
input
P4SEL
P4DIR
P4OUT
P4IN
01Fh
01Eh
01Dh
01Ch
Port P3
Port
Port
Port
Port
P3
P3
P3
P3
selection
direction
output
input
P3SEL
P3DIR
P3OUT
P3IN
01Bh
01Ah
019h
018h
Port P2
Port
Port
Port
Port
Port
Port
Port
P2
P2
P2
P2
P2
P2
P2
selection
interrupt enable
interrupt-edge select
interrupt flag
direction
output
input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
63
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
Table 6-10. Peripherals With Byte Access (continued)
MODULE
REGISTER NAME
ACRONYM
ADDRESS
Port P1
Port
Port
Port
Port
Port
Port
Port
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ME2
ME1
IFG2
IFG1
IE2
IE1
005h
004h
003h
002h
001h
000h
64
Detailed Description
P1
P1
P1
P1
P1
P1
P1
selection
interrupt enable
interrupt-edge select
interrupt flag
direction
output
input
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10 Input/Output Schematics
6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
DVSS
P1DIR .x
0
Direction
0: Input
1: Output
1
P1OUT .x
Module X OUT
0
1
Bus
Keeper
P 1SEL.x
EN
P1.0/TA 0
P1.1/TA 0/MCLK
P1.2/TA 1
P1.3/TBOUTH /SVSOUT
P1.4/TBCLK /SMCLK
P1.5/TACLK /ACLK
P1IN.x
EN
Module X IN
D
P 1IE.x
P1IRQ .x
EN
Q
P1IFG .x
P1SEL.x
P 1IES .x
Set
Interrupt
Edge
Select
Note : x = 0,1, 2,3,4,5
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
65
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Table 6-11. Port P1 (P1.0 to P1.5) Pin Functions
PIN NAME (P1.x)
P1.0/TA0
x
0
FUNCTION
P1.0 (I/O)
Timer_A3.CCI0A
Timer_A3.TA0
P1.1/TA0/MCLK
1
P1.1 (I/O)
Timer_A3.CCI0B
MCLK
P1.2/TA1
2
P1.2 (I/O)
Timer_A3.CCI1A
Timer_A3.TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
66
Detailed Description
3
4
5
CONTROL BITS OR SIGNALS
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_B7.TBOUTH
0
1
SVSOUT
1
1
P1.4 (I/O)
P1.3 (I/O)
I: 0; O: 1
0
Timer_B7.TBCLK
0
1
SMCLK
1
1
P1.5 (I/O)
I: 0; O: 1
0
Timer_A3.TACLK
0
1
ACLK
1
1
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.2 Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
CAPD .x
P1DIR .x
0
Direction
0: Input
1: Output
1
P1OUT .x
Module X OUT
0
1
P1.6/CA 0
P1.7/CA 1
Bus
Keeper
P 1SEL.x
EN
P1IN.x
EN
Module X IN
D
P2CA0
P 1IE .x
P1IRQ .x
EN
Comp _A
Q
P1IFG .x
Set
1
P1IES .x
CA 0
+
Interrupt
Edge
Select
P1SEL.x
0
-
0
1
Note : x = 6,7
CA 1
P2CA1
Table 6-12. Port P1 (P1.6 and P1.7) Pin Functions
PIN NAME (P1.x)
x
P1.6/CA0
6
P1.7/CA1
7
(1)
FUNCTION
CONTROL BITS OR SIGNALS (1)
CAPD.x
P1DIR.x
P1SEL.x
P1.6 (I/O)
0
I: 0; O: 1
0
CA0
1
X
X
P1.7 (I/O)
0
I: 0; O: 1
0
CA1
1
X
X
X = don't care
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
67
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.3
www.ti.com
Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
TBOUTH
P2DIR .x
0
Direction
0: Input
1: Output
1
P2OUT .x
Module X OUT
0
1
Bus
Keeper
P 2SEL.x
EN
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.6/CAOUT
P2.7/ADC12CLK /DMAE 0
P2IN.x
EN
Module X IN
D
P 2IE .x
P2IRQ .x
EN
Q
P2IFG .x
P2SEL.x
P 2IES .x
Set
Interrupt
Edge
Select
Note : x = 0,1,2,3,6,7
68
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 6-13. Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA2
x
0
FUNCTION
P2.0 (I/O)
Timer_A3.CCI2A
Timer_A3.TA2
P2.1/TB0
1
P2.1 (I/O)
Timer_B7.CCI0A and Timer_B7.CCI0B
Timer_B7.TB0
P2.2/TB1
2
(1)
P2.2 (I/O)
Timer_B7.CCI1A and Timer_B7.CCI1B
Timer_B7.TB1
P2.3/TB3
3
P2.6/CAOUT
6
(1)
(1)
7
P2DIR.x
P2SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB3 (1)
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
ADC12CLK
1
1
DMAE0
0
1
P2.3 (I/O)
P2.6 (I/O)
CAOUT
P2.7/ADC12CLK/DMAE0
CONTROL BITS OR SIGNALS
P2.7 (I/O)
Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
69
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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6.10.4 Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
Pad Logic
DV SS
DV SS
DV SS
P 2DIR .x
0
Direction control
from Module X
1
P2OUT .x
0
Module X OUT
Direction
0: Input
1: Output
1
P2.4/UCA 0TXD
P2.5/UCA 0RXD
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ .x
EN
Q
Set
P2IFG .x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Note: x = 4,5
Table 6-14. Port P2 (P2.4 and P2.5) Pin Functions
PIN NAME (P2.x)
P2.4/UCA0TXD
P2.5/UCA0RXD
(1)
(2)
70
x
4
5
FUNCTION
P2.4 (I/O)
USCI_A0.UCA0TXD
(2)
P2.5 (I/O)
USCI_A0.UCA0RXD
(2)
CONTROL BITS OR
SIGNALS (1)
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = don't care
When in USCI mode, P2.4 is set to output, P2.5 is set to input.
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.5 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
Pad Logic
DV SS
DV SS
DV SS
P3DIR .x
0
Direction
0: Input
1: Output
1
P3OUT .x
Module X OUT
0
1
Bus
Keeper
P 3SEL.x
P 3.0/UCB 0STE
P 3.1/UCB 0SIMO /UCB 0SDA
P 3.2/UCB 0SOMI /UCB 0SCL
P 3.3/UCB 0CLK
EN
P3IN.x
EN
Module X IN
D
Note: x = 0,1,2,3
Table 6-15. Port P3 (P3.0 to P3.3) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0STE
x
0
FUNCTION
P3.0 (I/O)
UCB0STE
P3.1/UCB0SIMO/UCB0SDA
1
(2)
P3.1 (I/O)
UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
2
P3.2 (I/O)
UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
3
(2) (3)
P3.3 (I/O)
UCB0CLK
(1)
(2)
(3)
(2) (3)
(2)
CONTROL BITS OR
SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected the output drives only the logical 0 to VSS level.
Detailed Description
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
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6.10.6 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
DV SS
DV SS
TBOUTH
P3DIR .x
0
Direction
0: Input
1: Output
1
P3OUT .x
Module X OUT
0
1
P3.4/TB 3
P3.5/TB 4
P3.6/TB 5
P3.7/TB 6
Bus
Keeper
P 3SEL.x
EN
P3IN.x
EN
Module X IN
D
Note: x = 4,5,6,7
Table 6-16. Port P3 (P3.4 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.4/TB3
x
4
P3.5/TB4
5
FUNCTION
P3DIR.x
P3SEL.x
I: 0; O: 1
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3 (1)
1
1
I: 0; O: 1
0
0
1
1
1
P3.4 (I/O)
P3.5 (I/O)
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4
P3.6/TB5
6
P3.7/TB6
(1)
72
7
CONTROL BITS OR SIGNALS
(1)
P3.6 (I/O)
I: 0; O: 1
0
Timer_B7.CCI5A and Timer_B7.CCI5B
0
1
Timer_B7.TB5 (1)
1
1
P3.7 (I/O)
I: 0; O: 1
0
Timer_B7.CCI6A and Timer_B7.CCI6B
0
1
Timer_B7.TB6 (1)
1
1
Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
Detailed Description
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.7 Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
DVSS
P4DIR.x
0
Direction control
from Module X
1
P4OUT.x
0
Module X OUT
Direction
0: Input
1: Output
1
P4.1/URXD 1
P4.0/UTXD 1
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Note: x = 0,1
Table 6-17. Port P4 (P4.0 to P4.1) Pin Functions
PIN NAME (P4.x)
P4.0/UTXD1
x
0
FUNCTION
P4.0 (I/O)
USART1.UTXD1
P4.1/URXD1
1
P4.1 (I/O)
USART1.URXD1
(1)
(2)
(2)
(2)
CONTROL BITS OR
SIGNALS (1)
P4DIR.x
P4SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = don't care
When in USART1 mode, P4.0 is set to output, P4.1 is set to input.
Detailed Description
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73
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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6.10.8 Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
LCDS 32/36
Segment Sy
DV SS
P4DIR.x
0
Direction control
from Module X
1
P4OUT.x
0
Module X OUT
Direction
0: Input
1: Output
1
P4.7/UCA0RXD /S34
P4.6/UCA0TXD/S35
P4.5/UCLK 1/S36
P4.4/SOMI 1/S37
P4.3/SIMO 1/S38
P4.2/STE1/S39
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Note : x = 2,3,4,5,6,7
y = 34,35,36,37,38,39
Table 6-18. Port P4 (P4.2 to P4.5) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS36
I: 0; O: 1
0
0
USART1.STE1
X
1
0
S39
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
P4.2 (I/O)
P4.2/STE1/S39
2
P4.3 (I/O)
P4.3/SIMO/S38
3
USART1.SIMO1
(2)
S38
P4.4 (I/O)
P4.4/SOMI/S37
4
USART1.SOMI1
(2)
S37
P4.5 (I/O)
P4.5/SOMI/S36
5
USART1.UCLK1
(2)
S36
(1)
(2)
74
CONTROL BITS OR SIGNALS (1)
X = don't care
The pin direction is controlled by the USART1 module.
Detailed Description
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 6-19. Port P4 (P4.6 and P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.6 (I/O)
P4.6/UCA0TXD/S35
6
USCI_A0.UCA0TXD
(2)
S35
P4.7 (I/O)
P4.7/UCA0RXD/S34
7
USCI_A0.UCA0RXD
(2)
S34
(1)
(2)
CONTROL BITS OR SIGNALS (1)
P4DIR.x
P4SEL.x
LCDS32
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
X = don't care
When in USCI mode, P4.6 is set to output, P4.7 is set to input.
Detailed Description
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75
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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6.10.9 Port P5, P5.0, Input/Output With Schmitt Trigger
INCH =13 #
Pad Logic
A13 #
LCDS 0
Segment Sy
P5DIR.x
0
Direction
0: Input
1: Output
1
0
P5OUT.x
DV SS
1
P 5.0/S1/A13/OA 1I1
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 0
y=1
+
OA1
-
Table 6-20. Port P5 (P5.0) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
P5.0/S1/A13/OA1I1
x
0
FUNCTION
P5SEL.x
INCHx
OAPx (OA1)
OANx (OA1)
LCDS0
I: 0; O: 1
0
X
X
0
0
X
X
1
0
(2)
X
1
13
X
X
S1 enabled
X
0
X
X
1
S1 disabled
X
1
X
X
1
P5.0 (I/O)
OAI11
A13
(1)
(2)
76
P5DIR.x
X = don't care
Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger
INCH =12 #
Pad Logic
A12 #
LCDS 0
Segment Sy
DAC 12.1OPS
P5DIR.x
0
1
P5OUT.x
DV SS
Direction
0: Input
1: Output
0
1
P5.1/S0/A12/DAC 1
Bus
Keeper
P5SEL.x
EN
P 5IN.x
Note: x = 1
y=0
DVSS
DAC1
0
1
2
0 if DAC12.1AMPx = 0 and DAC 12.1OPS = 1
1 if DAC12.1AMPx = 1 and DAC 12.1OPS = 1
2 if DAC12.1AMPx > 1 and DAC 12.1OPS = 1
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
77
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Table 6-21. Port P5 (P5.1) Pin Functions
PIN NAME (P5.x)
P5.1/S0/A12/DAC1
x
1
FUNCTION
P5SEL.x
INCHx
DAC12.1OPS
DAC12.1AMPx
I: 0; O: 1
0
X
0
X
0
DAC1 high impedance
X
X
X
1
0
X
DVSS
X
X
X
1
1
X
DAC1 output
P5.1 (I/O)
78
LCDS0
X
X
X
1
>1
X
(2)
X
1
12
0
X
0
S0 enabled
X
0
X
0
X
1
S0 disabled
X
1
X
0
X
1
A12
(1)
(2)
CONTROL BITS OR SIGNALS (1)
P5DIR.x
X = don't care
Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
Pad Logic
LCD Signal
DV SS
P5DIR.x
0
Direction
0: Input
1: Output
1
P5OUT.x
DV SS
0
1
P5.2/COM1
P5.3/COM2
P5.4/COM3
Bus
Keeper
P5SEL.x
EN
P 5IN.x
Note : x = 2,3,4
Table 6-22. Port P5 (P5.2 to P5.4) Pin Functions
PIN NAME (P5.x)
P5.2/COM1
x
2
FUNCTION
P5.2 (I/O)
COM1
P5.3/COM2
3
P5.3 (I/O)
COM2
P5.4/COM3
4
P5.4 (I/O)
COM3
(1)
CONTROL BITS OR
SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = don't care
Detailed Description
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MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
79
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
Pad Logic
LCD Signal
DV SS
P5DIR.x
0
Direction
0: Input
1: Output
1
0
P5OUT.x
DV SS
1
P5.5/R03
P5.6/LCDREF /R13
P5.7/R03
Bus
Keeper
P5SEL.x
EN
P 5IN.x
Note : x = 5,6,7
Table 6-23. Port P5 (P5.5 to P5.7) Pin Functions
PIN NAME (P5.x)
P5.5/R03
x
5
FUNCTION
P5.5 (I/O)
CONTROL BITS OR
SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
R03
P5.6/LCDREF/R13
6
P5.6 (I/O)
R13 or LCDREF
P5.7/R03
7
P5.7 (I/O)
(2)
R03
(1)
(2)
80
X = don't care
External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
Detailed Description
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
INCH =0/2/4#
Pad Logic
Ay #
P6DIR.x
0
Direction
0: Input
1: Output
1
P 6OUT.x
DV SS
P6.0/A0/OA 0I0
P6.2/A2/OA 0I1
P6.4/A4/OA 1I0
0
1
Bus
Keeper
P6SEL.x
EN
P6IN.x
Note: x = 0, 2, 4
y = 0, 1
# = Signal from or to ADC12
+
OA0/1
-
Table 6-24. Port P6 (P6.0, P6.2, and P6.4) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x)
P6.0/A0/OA0I0
x
0
FUNCTION
P6SEL.x
OAPx (OA0)
OANx (OA0)
OAPx (OA1)
OANx (OA1)
INCHx
I: 0; O: 1
0
X
X
X
0
X
0
X
X
(2)
X
1
X
X
0
P6.2 (I/O)
I: 0; O: 1
0
X
X
X
0
X
1
X
X
(2)
X
1
X
X
2
P6.4 (I/O)
I: 0; O: 1
0
X
X
X
0
X
X
0
X
X
1
X
X
4
P6.0 (I/O)
OA0I0
A0
P6.2/A2/OA0I1
2
OA0I1
A2
P6.4/A4/OA1I0
4
OA1I0
A4
(1)
(2)
(2)
P6DIR.x
X = don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Detailed Description
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger
INCH =1/3/5#
Pad Logic
Ay #
P6DIR.x
0
Direction
0: Input
1: Output
1
P 6OUT.x
DV SS
P6.1/A1/OA0O
P6.3/A3/OA1O
P6.5/A5/OA2O
0
1
Bus
Keeper
P6SEL.x
EN
P6IN.x
OAPMx > 0
OAADC 1
+
OAy
-
Note: x = 1, 3, 5
y = 0, 1, 2
# = Signal from or to ADC12
Table 6-25. Port P6 (P6.1, P6.3, and P6.5) Pin Functions
PIN NAME (P6.x)
P6.1/A1/OA0O
x
1
FUNCTION
P6.1 (I/O)
OA0O
3
82
INCHx
0
X
X
1
>0
1
X
0
1
P6.3 (I/O)
I: 0; O: 1
0
X
0
X
X
(2)
X
X
1
>0
(3)
X
1
X
0
3
P6.5 (I/O)
I: 0; O: 1
0
X
0
X
X
X
1
>0
X
X
1
X
0
5
A5
(3)
OAPMx
X
X
OA2O
(1)
(2)
OAADC1
0
X
A3
5
P6SEL.x
X
OA1O
P6.5/A5/OA2O
P6DIR.x
I: 0; O: 1
(3)
A1
P6.3/A3/OA1O
(2)
CONTROL BITS OR SIGNALS (1)
(3)
(2)
X = don't care
Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally
connected to the corresponding ADC12 input.
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Detailed Description
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger
INCH =6 #
Pad Logic
A6 #
P6DIR .x
0
1
P6OUT .x
DV SS
Direction
0: Input
1: Output
P6.6/A6/DAC0/OA 2I0
0
1
Bus
Keeper
P 6SEL .x
DAC 12.0AMP > 0
DAC12.0OPS
EN
P6IN.x
Note: x = 6
# = Signal from or to ADC12
+
OA 2
-
DV SS
DAC 0
0
1
2
0 if DAC 12.0AMPx = 0 and DAC 12.0OPS = 0
1 if DAC 12.0AMPx = 1 and DAC 12.0OPS = 0
2 if DAC 12.0AMPx > 1 and DAC 12.0OPS = 0
Detailed Description
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MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
83
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Table 6-26. Port P6 (P6.6) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x)
x
P6.6/A6/DAC0/OA2I0
6
FUNCTION
P6.6 (I/O)
INCHx
DAC12.0OPS
DAC12.0AMPx
OAPx (OA2)
OANx (OA2)
I: 0; O: 1
0
X
1
X
X
X
X
X
0
0
X
DVSS
X
X
X
0
1
X
DAC0 output
X
X
X
0
>1
X
X
1
6
X
X
X
0
X
0
X
X
0
(2)
OA2I0
84
P6SEL.x
DAC0 high impedance
A6
(1)
(2)
P6DIR.x
X = don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Detailed Description
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger
To SVS Mux
INCH =7
#
Pad Logic
A7 #
P6DIR .x
0
1
P6OUT .x
DV SS
Direction
0: Input
1: Output
0
1
P 6SEL .x
Bus
Keeper
VLD =15
EN
P6.7/A7/DAC 1/SVSIN
DAC 12.1AMP > 0
DAC12.1OPS
P6IN.x
Note: x = 7
# = Signal from or to ADC12
DV SS
DAC 1
0
1
2
0 if DAC 12.1AMPx = 0 and DAC 12.1OPS = 0
1 if DAC 12.1AMPx = 1 and DAC 12.1OPS = 0
2 if DAC 12.1AMPx > 1 and DAC 12.1OPS = 0
Detailed Description
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Table 6-27. Port P6 (P6.7) Pin Functions
PIN NAME (P6.x)
P6.7/A7/DAC1/SVSIN
x
7
FUNCTION
P6SEL.x
INCHx
DAC12.1OPS
DAC12.1AMPx
I: 0; O: 1
0
X
1
X
DAC1 high impedance
X
X
X
0
0
DVSS
X
X
X
0
1
DAC1 output
X
X
X
0
>1
X
1
7
X
X
0
1
0
1
X
P6.7 (I/O)
A7
(2)
SVSIN
(1)
(2)
86
CONTROL BITS OR SIGNALS (1)
P6DIR.x
(2)
X = don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals.
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
Pad Logic
LCDS 28/32
Segment Sy
DV SS
P7DIR.x
Direction control
from Module X
P 7OUT .x
Module X OUT
0
Direction
0: Input
1: Output
1
0
1
Bus
Keeper
P7SEL.x
P7.3/UCA0CLK /S30
P7.2/UCA0SOMI /S 31
P7.1/UCA0SIMO /S 32
P7.0/UCA0STE /S33
EN
P7IN.x
EN
Module X IN
D
Note: x = 0, 1, 2, 3
y = 30, 31, 32, 33
Detailed Description
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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Table 6-28. Port P7 (P7.0 and P7.1) Pin Functions
PIN NAME (P7.x)
P7.0/UCA0STE/S33
x
0
FUNCTION
P7DIR.x
P7SEL.x
LCDS32
I: 0; O: 1
0
0
X
1
0
(1)
X
X
1
P7.1 (I/O)
I: 0; O: 1
0
0
X
1
0
X
X
1
P7.0 (I/O)
USCI_A0.UCA0STE
S33
P7.1/UCA0SIMO/S32
1
(2)
USCI_A0.UCA0SIMO
(2)
S32
(1)
(2)
CONTROL BITS OR SIGNALS (1)
X = don't care
The pin direction is controlled by the USCI module.
Table 6-29. Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P7.x)
P7.2/UCA0SOMI/S31
x
2
FUNCTION
P7.2 (I/O)
USCI_A0.UCA0SOMI
(2)
S31
P7.3/UCA0CLK/S30
3
P7.3 (I/O)
USCI_A0.UCA0CLK
S30
(1)
(2)
88
(2)
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.x
LCDS28
I: 0; O: 1
0
0
X
1
0
X
X
1
I: 0; O: 1
0
0
X
1
0
X
X
1
X = don't care
The pin direction is controlled by the USCI module.
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Pad Logic
LCDS 24/28
Segment Sy
DV SS
P7DIR.x
0
Direction
0: Input
1: Output
1
P7OUT.x
DV SS
0
1
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
Bus
Keeper
P7SEL.x
EN
P7IN.x
Note: x = 4, 5, 6, 7
y = 26, 27, 28, 29
Table 6-30. Port P7 (P7.4 and P7.5) Pin Functions
PIN NAME (P7.x)
x
P7.4/S29
4
P7.5/S28
5
FUNCTION
P7.4 (I/O)
S29
P7.5 (I/O)
S28
(1)
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.x
LCDS28
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Table 6-31. Port P7 (P7.6 and P7.7) Pin Functions
PIN NAME (P7.x)
x
P7.6/S27
6
P7.7/S26
7
FUNCTION
P7.6 (I/O)
S27
P7.7 (I/O)
S26
(1)
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL.x
LCDS24
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Detailed Description
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6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
Pad Logic
LCDS 16/20/24
Segment Sy
DV SS
P8DIR.x
0
Direction
0: Input
1: Output
1
P8OUT.x
DV SS
0
1
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
P8.2/S23
P8.1/S24
P8.0/S25
Bus
Keeper
P8SEL.x
EN
P 8IN.x
Note : x = 0,1,2,3,4,5,6,7
y = 25,24,23,22,21,20,19,18
Table 6-32. Port P8 (P8.0 and P8.1) Pin Functions
PIN NAME (P8.x)
x
P8.0/S18
0
P8.1/S19
0
FUNCTION
P8.0 (I/O)
S18
P8.0 (I/O)
S19
(1)
CONTROL BITS OR SIGNALS (1)
P8DIR.x
P8SEL.x
LCDS16
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Table 6-33. Port P8 (P8.2 to P8.5) Pin Functions
PIN NAME (P8.x)
x
P8.2/S20
2
P8.3/S21
3
FUNCTION
P8.2 (I/O)
S20
P8.3 (I/O)
S21
P8.4/S22
4
P8.4 (I/O)
S22
P8.5/S23
5
P8.5 (I/O)
S23
(1)
90
CONTROL BITS OR SIGNALS (1)
P8DIR.x
P8SEL.x
LCDS20
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Detailed Description
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 6-34. Port P8 (P8.6 and P8.7) Pin Functions
PIN NAME (P8.x)
P8.6/S24
X
6
FUNCTION
P8.6 (I/O)
S24
P8.7/S25
7
P8.7 (I/O)
S25
(1)
CONTROL BITS OR SIGNALS (1)
P8DIR.x
P8SEL.x
LCDS24
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Detailed Description
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91
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
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6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Pad Logic
LCDS 8/12/16
Segment Sy
DV SS
P9DIR.x
0
Direction
0: Input
1: Output
1
P9OUT.x
DV SS
0
1
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
Bus
Keeper
P9SEL.x
EN
P 9IN.x
Note : x = 0,1,2,3,4,5,6,7
y = 17,16,15,14,13,12,11 ,10
Table 6-35. Port P9 (P9.0 and P9.1) Pin Functions
PIN NAME (P9.x)
x
P9.0/S17
0
P9.1/S16
1
FUNCTION
P9.0 (I/O)
S17
P9.1 (I/O)
S16
(1)
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
LCDS16
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Table 6-36. Port P9 (P9.2 to P9.5) Pin Functions
PIN NAME (P9.x)
x
P9.2/S15
2
P9.3/S14
3
FUNCTION
P9.2 (I/O)
S15
P9.3 (I/O)
S14
P9.4/S13
4
P9.4 (I/O)
S13
P9.5/S12
5
P9.5 (I/O)
S12
(1)
92
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
LCDS12
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
Table 6-37. Port P9 (P9.6 and P9.7) Pin Functions
PIN NAME (P9.x
P9.6/S11
x
6
FUNCTION
P9.6 (I/O)
S11
P9.7/S10
7
P9.7 (I/O)
S10
(1)
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
LCDS8
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Detailed Description
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93
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger
Pad Logic
LCDS 4/8
Segment Sy
DV SS
P10DIR.x
0
Direction
0: Input
1: Output
1
P10OUT.x
DV SS
0
1
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note : x = 0,1,2,3,4,5
y = 9,8,7,6,5,4
Table 6-38. Port P10 (P10.0 and P10.1) Pin Functions
PIN NAME (P10.x)
P10.0/S9
x
0
FUNCTION
P10.0 (I/O)
S9
P10.1/S8
1
P10.1 (I/O)
S8
(1)
CONTROL BITS OR SIGNALS (1)
P10DIR.x
P10SEL.x
LCDS8
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Table 6-39. Port P10 (P10.2 to P10.5) Pin Functions
PIN NAME (P10.x)
P10.2/S7
x
2
FUNCTION
P10.2 (I/O)
S7
P10.3/S6
3
P10.3 (I/O)
S6
P10.4/S5
4
P10.4 (I/O)
S5
P10.5/S4
5
P10.5 (I/O)
S4
(1)
94
CONTROL BITS OR SIGNALS (1)
P10DIR.x
P10SEL.x
LCDS4
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = don't care
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger
INCH =15 #
Pad Logic
A15 #
LCDS 0
Segment Sy
P10DIR.x
0
Direction
0: Input
1: Output
1
P10OUT.x
DV SS
0
1
P10.6/S 3/A15
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note : x = 6
y =3
Table 6-40. Port P10 (P10.6) Pin Functions
PIN NAME (P10.x)
x
P10.6/S3/A15
CONTROL BITS OR SIGNALS (1)
P10DIR.x
P10SEL.x
INCHx
LCDS0
I: 0; O: 1
0
X
0
(2)
X
1
15
0
S3 enabled
X
0
X
1
S3 disabled
X
1
X
1
P5.0 (I/O)
6
(1)
(2)
FUNCTION
A15
X = don't care
Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
Detailed Description
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
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6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger
INCH =14 #
Pad Logic
A14 #
LCDS 0
Segment Sy
P10DIR.x
0
Direction
0: Input
1: Output
1
0
P10OUT.x
1
DV SS
P10.7/S2/A14/OA 2I1
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note : x = 7
y =2
+
OA2
-
Table 6-41. Port P10 (P10.7) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P10.x)
P10.7/S2/A14/OA2I1
x
7
FUNCTION
P10.7(I/O)
A14
(2)
OA2I1
(1)
(2)
96
(2)
INCHx
OAPx (OA1)
OANx (OA1)
LCDS0
0
X
X
0
1
14
X
0
P10DIR.x
P10SEL.x
I: 0; O: 1
X
0
X
X
1
0
S2 enabled
X
0
X
X
1
S2 disabled
X
1
X
X
1
X = don't care
Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.24 VeREF+/DAC0
DAC12.0OPS
0
DAC0_2_OA
P6.6/A6/DAC0/OA2I0
1
Reference Voltage to DAC1
Reference Voltage to ADC12
Reference Voltage to DAC0
#
Ve REF+ /DAC0
'0', if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
+
-
1
0
'1', if DAC12AMPx>1
'1', if DAC12AMPx=1
DAC12OPS
#
If the reference of DAC0 is taken from pin Ve
/DAC0 , unpredictable voltage levels will be on pin.
REF+
In this situation, the DAC0 output is fed back to its own reference input.
Detailed Description
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Copyright © 2006–2015, Texas Instruments Incorporated
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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
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6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DV CC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
DV CC
and
Emulation
TMS
Module
TMS
DV CC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
98
Detailed Description
G
D
U
S
G
D
U
S
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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.10.26 JTAG Fuse Check Mode
Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse
check current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system
power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if
the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the
fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs.
After each POR the fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state
(see Figure 6-1). Therefore, the additional current flow can be prevented by holding the TMS pin high
(default condition). The JTAG pins are terminated internally and therefore do not require external
termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 6-1. Fuse Check Mode Current
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
99
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
7 Device and Documentation Support
7.1
Device Support
7.1.1
Getting Started and Next Steps
For more information on the MSP430F4x family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.1.2
Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
7.1.2.1
Hardware Features
See the Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock
Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430
Yes
No
2
No
Yes
No
No
No
7.1.2.2
Recommended Hardware Options
7.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
Package
Target Board and Programmer Bundle
Target Board Only
100-pin LQFP (PZ)
MSP-FET430U100
MSP-TS430PZ100
7.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
7.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
7.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
7.1.2.3
Features
Provider
Program up to eight devices at a time. Works with PC or standalone.
Texas Instruments
Recommended Software Options
7.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
100
Device and Documentation Support
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
7.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a standalone package.
7.1.2.3.3 Command-Line Programmer
MSP430 Flasher is an open-source shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the
need for an IDE.
7.1.3
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend
for reading the complete device name for any family member.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
101
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
MSP 430 F 5 438 A I ZQW T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
430 MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
TI’s Low-Power Microcontroller Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz with LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
102
Device and Documentation Support
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
7.2
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Documentation Support
The following documents describe the MSP430FG461x and MSP430CG461x devices. Copies of these
documents are available on the Internet at www.ti.com.
7.3
SLAU056
MSP430F4xx Family User's Guide. Detailed information on the modules and peripherals
available in this device family.
SLAZ369
MSP430FG4619 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ368
MSP430FG4618 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ367
MSP430FG4617 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ366
MSP430FG4616 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ123
MSP430CG4619 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ122
MSP430CG4618 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ121
MSP430CG4617 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ120
MSP430CG4616 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
Related Links
Table 7-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FG4619
Click here
Click here
Click here
Click here
Click here
MSP430FG4618
Click here
Click here
Click here
Click here
Click here
MSP430FG4617
Click here
Click here
Click here
Click here
Click here
MSP430FG4616
Click here
Click here
Click here
Click here
Click here
MSP430CG4619
Click here
Click here
Click here
Click here
Click here
MSP430CG4618
Click here
Click here
Click here
Click here
Click here
MSP430CG4617
Click here
Click here
Click here
Click here
Click here
MSP430CG4616
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
103
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
7.4
www.ti.com
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.5
Trademarks
MSP430, MicroStar Junior, Code Composer Studio, E2E are trademarks of Texas Instruments.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.8
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
104
Device and Documentation Support
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Copyright © 2006–2015, Texas Instruments Incorporated
105
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430A139IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4618
MSP430FG4616IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4616
MSP430FG4616IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4616
MSP430FG4616IZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4616
MSP430FG4616IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4616
MSP430FG4617IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4617
MSP430FG4617IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4617
MSP430FG4617IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4617
MSP430FG4618IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4618
MSP430FG4618IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4618
MSP430FG4618IZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4618
MSP430FG4618IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4618
MSP430FG4618IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430FG4619IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Addendum-Page 1
M430FG4618
-40 to 85
M430FG4619
REV #
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FG4619IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG4619
MSP430FG4619IZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4619
MSP430FG4619IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4619
MSP430FG4619IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG4619
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430FG4616IPZR
MSP430FG4616IZQWR
MSP430FG4617IPZR
MSP430FG4617IZQWR
MSP430FG4618IPZR
Package Package Pins
Type Drawing
LQFP
BGA MI
CROSTA
R JUNI
OR
LQFP
BGA MI
CROSTA
R JUNI
OR
LQFP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
MSP430FG4618IZQWR
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG4618IZQWT
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
PZ
100
1000
330.0
24.4
17.0
17.0
2.1
20.0
24.0
Q2
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG4619IPZR
MSP430FG4619IZQWR
LQFP
BGA MI
CROSTA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.5
12.0
16.0
R JUNI
OR
MSP430FG4619IZQWT
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
180.0
16.4
7.3
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FG4616IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG4616IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG4617IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG4617IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG4618IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG4618IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG4618IZQWT
BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430FG4619IPZR
LQFP
PZ
100
1000
367.0
367.0
45.0
MSP430FG4619IZQWR
BGA MICROSTAR
ZQW
113
2500
336.6
336.6
28.6
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ZQW
113
250
213.0
191.0
55.0
JUNIOR
MSP430FG4619IZQWT
BGA MICROSTAR
JUNIOR
Pack Materials-Page 3
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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