TI1 CSD87352Q5D Synchronous buck nexfet power block Datasheet

CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
Synchronous Buck NexFET™ Power Block
FEATURES
DESCRIPTION
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The CSD87352Q5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high current, high efficiency, and high
frequency capability in a small 5-mm × 6-mm outline.
Optimized for 5V gate drive applications, this product
offers a flexible solution capable of offering a high
density power supply when paired with any 5V gate
drive from an external controller/driver.
1
2
Half-Bridge Power Block
91% system Efficiency at 15A
High Frequency Operation (Up To 1.5MHz)
High Density – SON 5-mm × 6-mm Footprint
Optimized for 5V Gate Drive
Low Switching Losses
Ultra Low Inductance Package
RoHS Compliant
Halogen Free
Pb-Free Terminal Plating
TEXT ADDED FOR SPACING
Top View
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
APPLICATIONS
VIN
2
•
TG
TGR
•
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Synchronous Buck Converters
– High Frequency Applications
– High Current, Low Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
PGND
(Pin 9)
BG
P0116-01
TEXT ADDED FOR SPACING
ORDERING INFORMATION
Device
Package
Media
CSD87352Q5D
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TYPICAL POWER BLOCK EFFICIENCY
and POWER LOSS
TYPICAL CIRCUIT
95
6
5
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
83
77
4
3
71
2
65
1
59
0
5
10
15
Output Current (A)
20
25
Power Loss (W)
Efficiency (%)
89
0
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C (unless otherwise noted)
(1)
Parameter
Voltage Range
Conditions
VALUE
UNIT
VIN to PGND
30
V
VSW to PGND
30
V
VSW to PGND (10ns)
32
V
TG to TGR
-8 to 10
V
BG to PGND
-8 to 10
V
60
A
8.5
W
Pulsed Current Rating, IDM
Power Dissipation, PD
Avalanche Energy EAS
Sync FET, ID = 65A, L = 0.1mH
211
Control FET, ID = 37A, L = 0.1mH
68
Operating Junction and Storage Temperature Range, TJ, TSTG
(1)
mJ
°C
-55 to 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Conditions
Gate Drive Voltage, VGS
MIN
MAX
4.5
8
V
27
V
Input Supply Voltage, VIN
Switching Frequency, fSW
CBST = 0.1μF (min)
UNIT
1500
Operating Current
Operating Temperature, TJ
kHz
25
A
125
°C
MAX
UNIT
POWER BLOCK PERFORMANCE
TA = 25° (unless otherwise noted)
Parameter
Power Loss, PLOSS
(1)
VIN Quiescent Current, IQVIN
(1)
Conditions
MIN
TYP
VIN = 12V, VGS = 5V,
VOUT = 1.3V, IOUT = 15A,
fSW = 500kHz, LOUT = 0.3µH, TJ = 25ºC
1.8
W
TG to TGR = 0V
BG to PGND = 0V
10
µA
Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5V driver IC.
THERMAL INFORMATION
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
2
Junction to ambient thermal resistance (Min Cu)
Junction to ambient thermal resistance (Max Cu)
2
(2)
TYP
MAX
UNIT
150
(1) (2)
Junction to case thermal resistance (Top of package)
Junction to case thermal resistance (PGND Pin)
MIN
(1) (2)
82
(2)
33
°C/W
2.8
(6.45-cm2)
2
Device mounted on FR4 material with 1-inch
Cu.
RθJC is determined with the device mounted on a 1-inch (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise stated)
PARAMETER
Q1 Control FET
TEST CONDITIONS
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250μA
IDSS
Drain to Source Leakage
Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage
Current
VDS = 0V, VGS = +10 / -8
VGS(th)
Gate to Source Threshold
Voltage
VDS = VGS, IDS = 250μA
ZDS(on) (1)
Effective AC
On-Impedance
VIN = 12V, VGS = 5V,
VOUT = 1.3V, IOUT = 15A,
fSW = 500kHz,
LOUT = 0.3µH, TJ = 25ºC
gfs
Transconductance
VDS = 15V, IDS = 15A
30
30
1
1
μA
100
100
nA
1.15
V
3.6
mΩ
1
2.1
9
V
0.75
10.8
2.8
51
87
S
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
740
890
1500
1800
pF
315
380
645
775
CRSS
Reverse Transfer
Capacitance
pF
12
14
38
46
pF
RG
Qg
Series Gate Resistance
1.2
2.4
0.6
1.2
Ω
Gate Charge Total (4.5V)
4.6
5.5
10.4
12.5
nC
Qgd
Gate Charge - Gate to
Drain
Qgs
Gate Charge - Gate to
Source
Qg(th)
Gate Charge at Vth
QOSS
Output Charge
td(on)
VGS = 0V, VDS = 15V,
f = 1MHz
0.9
1.9
nC
1.5
2.2
nC
0.9
1.2
nC
6.6
13
nC
Turn On Delay Time
5.4
6.1
ns
tr
Rise Time
11
7
ns
td(off)
Turn Off Delay Time
9.5
16
ns
tf
Fall Time
2
2.7
ns
VDS = 15V,
IDS = 15A
VDS = 9.8V, VGS = 0V
VDS = 15V, VGS = 4.5V,
IDS = 15A, RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
IDS = 15A, VGS = 0V
0.8
0.8
V
Qrr
Reverse Recovery Charge
11.3
16.3
nC
trr
Reverse Recovery Time
Vdd = 9.8V, IF = 15A,
di/dt = 300A/μs
16
20
ns
(1)
Equivalent System Performance based on application testing. See page 9 for details.
HD
LD
HD
LG
HG
5x6 QFN TTA MIN Rev1
5x6 QFN TTA MIN Rev1
Max RθJA = 82°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm
thick) Cu.
LD
Max RθJA = 150°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
HS
LG
LS
M0189-01
HG
HS
LS
M0190-01
Copyright © 2011, Texas Instruments Incorporated
3
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS
TJ = 125°C, unless stated otherwise.
6
1.6
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
4
Power Loss, Normalized
Power Loss (W)
5
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
1.5
3
2
1.4
1.3
1.2
1.1
1
0.9
0.8
1
0.7
0
0
5
10
15
Output Current (A)
20
0.6
−50
25
30
30
25
25
20
15
10
5
0
400LFM
200LFM
100LFM
Nat Conv
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
0
10
20
70
80
25
50
75
100
Junction Temperature (ºC)
125
150
20
15
10
90
Figure 3. Safe Operating Area – PCB Vertical Mount(1)
0
400LFM
200LFM
100LFM
Nat Conv
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
5
30
40
50
60
Ambient Temperature (ºC)
0
Figure 2. Normalized Power Loss vs Temperature
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
−25
0
10
20
30
40
50
60
Ambient Temperature (ºC)
70
80
90
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
40
35
Output Current (A)
30
25
20
15
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
10
5
0
0
20
40
60
80
100
Board Temperature (ºC)
120
140
Figure 5. Typical Safe Operating Area(1)
(1)
4
The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)
TJ = 125°C, unless stated otherwise.
TEXT ADDED FOR SPACING
1.5
10.6
8.5
1.4
8.5
1.3
6.3
1.2
4.2
1.1
2.1
6.4
1.2
4.2
1.1
2.1
1
0.0
1
0.9
−2.1
0.8
−4.2
0.7
−6.4
0.7
−8.5
500 650 800 950 1100 1250 1400 1550
Switching Frequency (kHz)
0.6
0.6
200
350
0.0
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
IOUT = 25A
0.9
0.8
Figure 6. Normalized Power Loss vs Switching Frequency
3
5
7
1.6
10.6
1.5
8.5
1.4
6.4
1.2
4.3
1.1
2.1
1
0
0.9
−2.1
0.8
−4.3
0.7
0.6
0.5
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
9
11
13
15
Input Voltage (V)
17
19
21
23
−8.5
12.7
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
IOUT = 25A
1.3
10.6
8.5
6.4
1.2
4.2
1.1
2.1
1
0
0.9
−2.1
0.8
−4.2
−6.4
0.7
−6.4
−8.5
0.6
Figure 8. Normalized Power Loss vs. Output Voltage
Copyright © 2011, Texas Instruments Incorporated
Power Loss, Normalized
12.8
SOA Temperature Adj (ºC)
Power Loss, Normalized
1.3
−6.3
TEXT ADDED FOR SPACING
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 0.3µH
IOUT = 25A
1.4
−4.2
Figure 7. Normalized Power Loss vs Input Voltage
TEXT ADDED FOR SPACING
1.6
1.5
−2.1
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (µH)
0.9
1
SOA Temperature Adj (ºC)
1.3
12.7
10.6
Power Loss, Normalized
Power Loss, Normalized
1.4
1.6
SOA Temperature Adj (ºC)
VIN = 12V
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
IOUT = 25A
1.5
12.7
SOA Temperature Adj (ºC)
TEXT ADDED FOR SPACING
1.6
−8.5
1.1
Figure 9. Normalized Power Loss vs. Output Inductance
5
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
40
35
35
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
TEXT ADDED FOR SPACING
40
30
25
20
15
10
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
5
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
30
25
20
15
10
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
5
0
0.4
0
0.04
VDS - Drain-to-Source Voltage - V
Figure 10. Control MOSFET Saturation
TEXT ADDED FOR SPACING
VDS = 5V
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
0.2
TEXT ADDED FOR SPACING
10
1
0.1
0.01
TC = 125°C
TC = 25°C
TC = −55°C
0.001
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage - V
3
3.5
10
1
0.1
0.01
0.001
TC = 125°C
TC = 25°C
TC = −55°C
0
0.5
Figure 12. Control MOSFET Transfer
1
1.5
2
2.5
VGS - Gate-to-Source Voltage - V
3
Figure 13. Sync MOSFET Transfer
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
8
8
ID = 15A
VDD = 15V
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.16
100
VDS = 5V
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
Qg - Gate Charge - nC (nC)
Figure 14. Control MOSFET Gate Charge
6
0.12
Figure 11. Sync MOSFET Saturation
100
0
0.08
VDS - Drain-to-Source Voltage - V
9
ID = 15A
VDD = 15V
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
Qg - Gate Charge - nC (nC)
Figure 15. Sync MOSFET Gate Charge
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
10
1
1
C − Capacitance − nF
C − Capacitance − nF
TEXT ADDED FOR SPACING
10
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0.001
0
5
10
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
15
20
25
30
0.001
0
5
10
VDS - Drain-to-Source Voltage - V
TEXT ADDED FOR SPACING
25
30
TEXT ADDED FOR SPACING
1.6
ID = 250µA
ID = 250µA
VGS(th) - Threshold Voltage - V
1.8
VGS(th) - Threshold Voltage - V
20
Figure 17. Sync MOSFET Capacitance
2
1.6
1.4
1.2
1
0.8
0.6
0.4
1.4
1.2
1
0.8
0.6
0.4
0.2
0.2
0
−75
−25
25
75
125
0
−75
175
−25
TC - Case Temperature - ºC
25
75
125
175
TC - Case Temperature - ºC
Figure 18. Control MOSFET VGS(th)
Figure 19. Sync MOSFET VGS(th)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
20
14
ID = 15A
18
16
14
12
10
8
6
4
TC = 25°C
TC = 125ºC
2
0
1
2
3
4
5
6
7
8
9
VGS - Gate-to- Source Voltage - V
Figure 20. Control MOSFET RDS(on) vs VGS
Copyright © 2011, Texas Instruments Incorporated
10
ID = 15A
RDS(on) - On-State Resistance - mΩ
RDS(on) - On-State Resistance - mΩ
15
VDS - Drain-to-Source Voltage - V
Figure 16. Control MOSFET Capacitance
0
f = 1MHz
VGS = 0V
12
10
8
6
4
2
0
TC = 25°C
TC = 125ºC
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to- Source Voltage - V
Figure 21. Sync MOSFET RDS(on) vs VGS
7
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.8
1.8
Normalized On-State Resistance
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
−25
25
75
125
ID = 15A
VGS = 8V
1.6
Normalized On-State Resistance
ID = 15A
VGS = 8V
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
175
−25
TC - Case Temperature - ºC
Figure 22. Control MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING
0.1
0.01
0.001
TC = 25°C
TC = 125°C
0.4
0.6
0.8
1
1.2
ISD − Source-to-Drain Current - A
ISD − Source-to-Drain Current - A
1
10
1
0.1
0.01
0.001
0.0001
TC = 25°C
TC = 125°C
0
0.2
0.4
0.6
0.8
1
VSD − Source-to-Drain Voltage - V
Figure 24. Control MOSFET Body Diode
Figure 25. Sync MOSFET Body Diode
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
I(AV) - Peak Avalanche Current - A
1000
I(AV) - Peak Avalanche Current - A
175
TEXT ADDED FOR SPACING
VSD − Source-to-Drain Voltage - V
100
10
TC = 25°C
TC = 125°C
0.1
1
10
t(AV) - Time in Avalanche - ms
Figure 26. Control MOSFET Unclamped Inductive
Switching
8
125
100
10
1
0.01
75
Figure 23. Sync MOSFET Normalized RDS(on)
100
0.0001
0.2
25
TC - Case Temperature - ºC
100
10
TC = 25°C
TC = 125°C
1
0.01
0.1
1
10
t(AV) - Time in Avalanche - ms
Figure 27. Sync MOSFET Unclamped Inductive Switching
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
APPLICATION INFORMATION
Equivalent System Performance
Many of today’s high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to
go beyond simply reducing RDS(ON).
Figure 28.
The CSD87352Q5D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in TI’s Application Note SLPA – 009.
Figure 29.
Copyright © 2011, Texas Instruments Incorporated
9
CSD87352Q5D
SLPS286 – JUNE 2011
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The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figures 30 and 31 compare the efficiency and power loss performance of the
CSD87352Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87352Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
96
6
94
5
4.5
Power Loss (W)
Efficiency (%)
92
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
90
88
86
84
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
4
3.5
3
2.5
2
1.5
PowerBlock HS/LS RDS(ON) = 9mΩ/4mΩ
Discrete HS/LS RDS(ON) = 9mΩ/4mΩ
Discrete HS/LS RDS(ON) = 9mΩ/2.8mΩ
82
80
PowerBlock HS/LS RDS(ON) = 9mΩ/4mΩ
Discrete HS/LS RDS(ON) = 9mΩ/4mΩ
Discrete HS/LS RDS(ON) = 9mΩ/2.8mΩ
5.5
2
6
10
14
18
Output Current (A)
1
0.5
22
26
0
2
6
Figure 30.
10
14
18
Output Current (A)
22
26
Figure 31.
The chart below compares the traditional DC measured RDS(ON) of CSD87352Q5D versus its ZDS(ON). This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87352Q5D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Comparison of RDS(ON) vs. ZDS(ON)
Parameter
10
HS
LS
Typ
Max
Typ
Max
Effective AC On-Impedance ZDS(ON) (VGS = 5V)
9
10.8
2.8
3.6
DC Measured RDS(ON) (VGS = 4.5V)
9
10.8
4
4.8
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
The CSD87352Q5D NexFET™ power block is an optimized design for synchronous buck applications using 5V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87352Q5D as a function of load current. This curve
is measured by configuring and running the CSD87352Q5D as it would be in the final application (see
Figure 32).The measured power loss is the CSD87352Q5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD87352Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x
3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thickness
Normalized Curves
The normalized curves in the CSD87352Q5D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Figure 32. Typical Application
Copyright © 2011, Texas Instruments Incorporated
11
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
Design Example
Operating Conditions:
• Output Current = 15A
• Input Voltage = 7V
• Output Voltage = 1V
• Switching Frequency = 800kHz
• Inductor = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Power Loss at 15A = 2.5W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.05 (Figure 7)
Normalized Power Loss for output voltage ≈ 0.95 (Figure 8)
Normalized Power Loss for switching frequency ≈ 1.08 (Figure 6)
Normalized Power Loss for output inductor ≈ 1.07 (Figure 9)
Final calculated Power Loss = 2.5W x 1.05 x 0.95 x 1.08 x 1.07 ≈ 2.88W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 1.05ºC (Figure 7)
SOA adjustment for output voltage ≈ -1.05ºC (Figure 8)
SOA adjustment for switching frequency ≈ 1.8ºC (Figure 6)
SOA adjustment for output inductor ≈ 1.7ºC (Figure 9)
Final calculated SOA adjustment = 1.05 + (-1.05) + 1.8 + 1.7 ≈ 3.5ºC
In the design example above, the estimated power loss of the CSD87352Q5D would increase to 2.88W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.5ºC. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 3.5ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
40
VIN = 12v
VGS = 5V
Vout = 1.3V
fSW = 500kHz
LOUT = 0.3μH
35
Output Current (A)
30
25
20
1
15
2
10
5
3
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
Figure 33. Power Block SOA
12
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
• The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6x10µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
• The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. (1)
Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 34. Recommended PCB Layout (Top Down View)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
Copyright © 2011, Texas Instruments Incorporated
13
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
MECHANICAL DATA
Q5D Package Dimensions
E2
K
d2
c1
4
5
4
q
L
d1
L
5
E1
6
3
6
3
b
9
D2
2
7
7
D1
2
E
e
8
1
8
1
d
d3
f
Top View
Bottom View
Side View
Pinout
Position
Exposed Tie Bar May Vary
q
a
c
E1
Front View
Pin 1
Designation
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
M0187-01
DIM
MILLIMETERS
MIN
MIN
MAX
a
1.40
1.55
0.055
0.061
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
1.630
1.730
0.064
0.068
d1
0.280
0.380
0.011
0.015
d2
0.200
0.300
0.008
0.012
d3
0.291
0.391
0.012
0.015
D1
4.900
5.100
0.193
0.201
D2
4.269
4.369
0.168
0.172
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.106
3.206
0.122
e
1.27 TYP
0.126
0.050
f
0.396
0.496
0.016
0.020
L
0.510
0.710
0.020
0.028
θ
0.00
–
–
–
K
14
INCHES
MAX
0.812
0.032
Copyright © 2011, Texas Instruments Incorporated
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
Land Pattern Recommendation
3.480 (0.137)
0.530 (0.021)
0.415 (0.016)
0.345 (0.014)
0.650 (0.026)
5
4
0.650 (0.026)
4.460
(0.176)
0.620
(0.024)
0.620 (0.024)
4.460
(0.176)
1.270
(0.050)
1
1.920
(0.076)
8
0.850 (0.033)
0.400 (0.016)
0.850 (0.033)
6.240 (0.246)
M0188-01
NOTE: Dimensions are in mm (inches).
Text For Spacing
Stencil Recommendation
0.250 (0.010)
0.300 (0.012)
0.610 (0.024)
0.341 (0.013)
5
4
0.410 (0.016)
Stencil Opening
0.300 (0.012)
0.300 (0.012)
1.710
(0.067)
8
1
1.680
(0.066)
0.950 (0.037)
1.290 (0.051)
PCB Pattern
M0208-01
NOTE: Dimensions are in mm (inches).
Text
For
Spacing
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Copyright © 2011, Texas Instruments Incorporated
15
CSD87352Q5D
SLPS286 – JUNE 2011
www.ti.com
Q5D Tape and Reel Information
4.00 ±0.10 (See Note 1)
K0
0.30 ±0.05
+0.10
2.00 ±0.05
Ø 1.50 –0.00
1.75 ±0.10
5.50 ±0.05
12.00 ±0.30
B0
R 0.20 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 5.30 ±0.10
B0 = 6.50 ±0.10
K0 = 1.90 ±0.10
M0191-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
16
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2011
PACKAGING INFORMATION
Orderable Device
CSD87352Q5D
Status
(1)
PREVIEW
Package Type Package
Drawing
SON
DQY
Pins
Package Qty
8
2500
Eco Plan
TBD
(2)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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