Fairchild FIN24AGFX Low voltage 24-bit bi-directional serializer/deserializer with multiple frequency ranges (preliminary) Datasheet

Preliminary
Revised May 2005
FIN24A
PSerDes
Low Voltage 24-Bit Bi-Directional Serializer/Deserializer
with Multiple Frequency Ranges (Preliminary)
General Description
Features
The FIN24A allows for a pair of SerDes to interleave data
from two different data sources going opposite directions or
standard bi-directional interface operation. The bi-directional data flow is controlled through use of a direction
(DIRI) control pin. The devices can be configured to operate in a unidirectional mode only by hardwiring the DIRI
pin. An internal PLL generates the required bit clock frequency for transfer across the serial link. The FIN24A supports multiple input frequency ranges which are selected
by the S1 and S2 control pins. Options exist for dual or single PLL operation dependent upon system operational
parameters. The device has been designed for low power
operation and utilizes Fairchild Low Power LVDS interface.
The device also supports an ultra low power Power-Down
mode for conserving power in battery operated applications.
■ Low power consumption
■ Low power standards based LVDS differential interface
■ LVCMOS parallel I/O interface
• 2 mA source/sink current
• Over-voltage tolerant control signals
■ I/O Power Supply range between 1.65V and 3.6V
■ Analog Power Supply range of 2.775V r 5%
■ Multi-Mode operation allows for a single device to
operate as Serializer or Deserializer
■ Internal PLL with no external components
■ Standby Power-Down mode support
■ Small footprint 40-terminal MLP packaging
■ Built in differential termination
■ Supports external CKREF frequencies between 2MHz
and 30MHz
■ Serialized data rate up to 780Mb/s
Ordering Code:
Order Number
Package Number
Package Description
FIN24AGFX
(Preliminary)
BGA042A
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195,
3.5mm Wide
FIN24AMLX
MLP040A
Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm
Square
Pb-Free package per JEDEC J-STD-020B.
BGX and MLP packages available in Tape and Reel only.
PSerDes¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500888
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FIN24A PSerDes Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
(Preliminary)
April 2005
FIN24A
Preliminary
Functional Block Diagram
Connection Diagram
Terminal Assignments for MLP
(Top View)
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2
Preliminary
FIN24A
Terminal Description
Terminal Name
I/O Type
Number
of
Terminals
DP[1:20]
I/O
20
LVCMOS Parallel I/O. Direction controlled by DIRI pin
DP[21:22]
I
2
LVCMOS Parallel Unidirectional Inputs
Description of Signals
DP[23:24]
O
2
LVCMOS Unidirectional Parallel Outputs
CKREF
IN
1
LVCMOS Clock Input and PLL Reference
STROBE
IN
1
LVCMOS Strobe Signal for Latching Data into the Serializer
CKP
OUT
1
LVCMOS Word Clock Output
DSO / DSI
DSO / DSI
DIFF-I/O
2
LpLVDS Differential Serial I/O Data Signals (Note 1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I): Positive signal of DSO(I) pair
DSO(I): Negative signal of DSO(I) pair
CKSI, SKSI DIFF-IN
2
LpLVDS Differential Deserializer Input Bit Clock
CKSI: Refers to signal pair
CKSI: Positive signal of CKSI pair
CKSI: Negative signal of CKSI pair
2
LpLVDS Differential Serializer Output Bit Clock
CKSO: Refers to signal pair
CKSO: Positive signal of CKSO pair
CKSO: Negative signal of CKSO pair
CKSO, SKSO DIFF-OUT
S1
IN
1
LVCMOS Mode Selection terminals used to select
S2
IN
1
Frequency Range for the RefClock, CKREF
DIRI
IN
1
LVCMOS Control Input
Used to control direction of Data Flow:
DIRI “1” Serializer, DIRI “0” Deserializer
DIRO
OUT
1
LVCMOS Control Output
Inversion of DIRI
VDDP
Supply
1
Power Supply for Parallel I/O and Translation Circuitry
VDDS
Supply
1
Power Supply for Core and Serial I/O
VDDA
Supply
1
Power Supply for Analog PLL Circuitry
GND
Supply
0
Use Bottom Ground Plane for Ground Signals
Note 1: The DSO/DSI serial port pins have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial connections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross.
Control Logic Circuitry
bits of data are ever serialized or deserialized. Regardless
of the mode of operation the serializer is always sending 24
bits of data plus 2 boundary bits and the deserializer is
always receiving 24 bits of data and 2 word boundary bits.
Bits 23 and 24 of the serializer will always contain the value
of zero and will be discarded by the deserializer. DP[21:22]
input to the serializer will be deserialized to DP[23:24]
respectively.
The FIN24A has the ability to be used as a 24-bit Serializer
or a 24-bit Deserializer. Pins S1 and S2 must be set to
accommodate the clock reference input frequency range of
the serializer. The table below shows the pin programming
of these options based on the S1 and S2 control pins. The
DIRI pin controls whether the device is a serializer or a
deserializer. When DIRI is asserted LOW, the device is
configured as a deserializer. When the DIRI pin is asserted
HIGH, the device will be configured as a serializer. Changing the state on the DIRI signal will reverse the direction of
the I/O signals and generate the opposite state signal on
DIRO. For unidirectional operation the DIRI pin should be
hardwired to the HIGH or LOW state and the DIRO pin
should be left floating. For bi-directional operation the DIRI
of the master device will be driven by the system and the
DIRO signal of the master will be used to drive the DIRI of
the slave device.
Turn-Around Functionality
The device passes and inverts the DIRI signal through the
device asynchronously to the DIRO signal. Care must be
taken by the system designer to insure that no contention
occurs between the deserializer outputs and the other
devices on this port. Optimally the peripheral device driving
the serializer should be put into a HIGH Impedance state
prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer the dedicated outputs will remain
at the last logical value asserted. This value will only
change if the device is once again turned around into a
deserializer and the values are overwritten.
Serializer/Deserializer
with Dedicated I/O Variation
The serialization and deserialization circuitry is setup for 24
bits. Because of the dedicated inputs and outputs only 22
3
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FIN24A
Preliminary
Serializer Operation: (Figure 1)
Modes 1, 2, or 3
DIRI equals 1
CKREF equals STROBE
The PLL must receive a stable CKREF signal in order to
achieve lock prior to any valid data being sent. The CKREF
signal can be used as the data STROBE signal provided
that data can be ignored during the PLL lock phase.
TABLE 1. Control Logic Circuitry
Mode
S2 S1 DIRI
Number
Description
0
0
0
x
Power-Down Mode
1
0
1
1
24-Bit Serializer
2MHz to 5MHz CKREF
0
1
0
24-Bit Deserializer
1
0
1
24-Bit Serializer
5MHz to 15MHz CKREF
1
0
0
24-Bit Deserializer
1
1
1
24-Bit Serializer
10MHz to 30MHz CKREF
1
1
0
24-Bit Deserializer
2
3
Once the PLL is stable and locked the device can begin to
capture and serialize data. Data will be captured on the rising edge of the STROBE signal and then serialized. The
serialized data stream is synchronized and sent source
synchronously with a bit clock with an embedded word
boundary. When operating in this mode the internal deserializer circuitry is disabled including the serial clock, serial
data input buffers, the bi-directional parallel outputs and the
CKP word clock. The CKP word clock will be driven HIGH.
Serializer Operation: (Figure 2)
DIRI equals 1
CKREF does not equal STROBE
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state the PLL and references will be disabled, differential input buffers will be shut off, differential output buffers
will be placed into a HIGH impedance state, LVCMOS outputs will be placed into a HIGH impedance state and
LVCMOS inputs will be driven to a valid level internally.
Additionally all internal circuitry will be reset. The loss of
CKREF state is also enabled to insure that the PLL will only
power-up if there is a valid CKREF signal.
If the same signal is not used for CKREF and STROBE,
then the CKREF signal must be run at a higher frequency
than the STROBE rate in order to serialize the data correctly. The actual serial transfer rate will remain at 26 times
the CKREF frequency. A data bit value of zero will be sent
when no valid data is present in the serial bit stream. The
operation of the serializer will otherwise remain the same.
The exact frequency that the reference clock needs to run
at will be dependent upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal implements spread spectrum technology then the maximum frequency of this spread spectrum clock should be used in
calculating the ratio of STROBE frequency to the CKREF
frequency. Similarly if the STROBE signal has significant
cycle-to-cycle variation then the maximum cycle-to-cycle
time needs to be factored into the selection of the CKREF
frequency.
In a typical application mode signals of the device will typically not change states other than between the desired frequency range and the power-down mode. This allows for
system level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selection
signals that have their operating mode driven to a “logic 0”
should be hardwired to GND. The S1 and S2 signals that
have their operating mode driven to a “logic 1” should be
connected to a system level power-down signal.
Serializer Operation: (Figure 3)
DIRI equals 1
No CKREF
A third method of serialization can be done by providing a
free running bit clock on the CKSI signal. This mode is
enabled by grounding the CKREF signal and driving the
DIRI signal HIGH.
At power-up the device is configured to accept a serialization clock from CKSI. If a CKREF is received then this
device will enable the CKREF serialization mode. The
device will remain in this mode even if CKREF is stopped.
To re-enable this mode the device must be powered down
and then powered back up with a “logic 0” on CKREF.
Serializer Operation Mode
The serializer configurations are described in the following
sections. The basic serialization circuitry works essentially
identical in these modes but the actual data and clock
streams will differ dependent on if CKREF is the same as
the STROBE signal or not. When it is stated that
CKREF STROBE this means that the CKREF and
STROBE signals have an identical frequency of operation
but may or may not be phase aligned. When it is stated that
CKREF does not equal STROBE then each signal is distinct and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
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4
Preliminary
FIN24A
Serializer Operation Mode
(Continued)
FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)
FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)
FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
5
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FIN24A
Preliminary
Deserializer Operation Mode
of CKP will be generated approximately 13 bit times later.
When no embedded word boundary occurs then no pulse
on CKP will be generated and CKP will remain HIGH.
The operation of the deserializer is only dependent upon
the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the
operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE
signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals
that are inputs to the deserializer.
When operating in this mode the internal serializer circuitry
is disabled including the parallel data input buffers. If there
is a CKREF signal provided then the CKSO serial clock will
continue to transmit bit clocks.
Deserializer Operation:
DIRI equals 0
(Serializer Source: CKREF does not equal STROBE)
The logical operation of the deserializer remains the same
regardless of if the CKREF is equal in frequency to the
STOBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer will
however be different because it will have non-valid data
bits sent between words. The duty cycle of CKP will vary
based on the ratio of the frequency of the CKREF signal to
the STROBE signal. The frequency of the CKP signal will
be equal to the STROBE frequency. The falling edge of
CKP will occur 6 bit times after the data transition. The
LOW time of the CKP signal will be equal to ½ (13 bit
times) of the CKREF period. The CKP HIGH time will be
equal to STROBE period – ½ of the CKREF period. Figure
5 is representative of a waveform that could be seen when
CKREF is not equal to STROBE. If CKREF was significantly faster then additional non-valid data bits would occur
between data words.
Deserializer Operation:
DIRI equals 0
(Serializer Source: CKREF equals STROBE)
When the DIRI signal is asserted LOW the device will be
configured as a deserializer. Data will be captured on the
serial port and deserialized through use of the bit clock
sent with the data. The word boundary is defined in the
actual clock and data signal. Parallel data will be generated
at the time the word boundary is detected. The falling edge
of CKP will occur approximately 6 bit times after the falling
edge of CKSI. The rising edge of CKP will go high approximately 13 bit times after CKP goes LOW. The rising edge
FIGURE 4. Deserializer Timing Diagram
(Serializer Source: CKREF equals STROBE)
FIGURE 5. Deserializer Timing Diagram
(Serializer Source: CKREF does not equal STROBE)
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6
Preliminary
mission. Bit 25 and Bit 26 are defined with-respect-to Bit
24. Bit 25 will always be the inverse of Bit 24, and Bit 26
will always be the same as Bit 24. This insures that a
“0” o “1” and a “1” o “0” transition will always occur during
the embedded word phase where CKSO is HIGH.
The FIN24A sends and receives serial data source synchronously with a bit clock. The bit clock has been modified
to create a word boundary at the end of each data word.
The word boundary has been implemented by skipping a
low clock pulse. This appears in the serial clock stream as
3 consecutive bit times where signal CKSO remains HIGH.
In order to implement this sort of scheme two extra data
bits are required. During the word boundary phase the data
will toggle either HIGH-then-LOW or LOW-then-HIGH
dependent upon the last bit of the actual data word. Table 2
provides some examples showing the actual data word and
the data word with the word boundary bits added. Note that
a 24-bit word will be extended to 26-bits during serial trans-
The serializer generates the word boundary data bits and
the boundary clock condition and embeds them into the
serial data stream. The deserializer looks for the end of the
word boundary condition to capture and transfer the data to
the parallel port. The deserializer only uses the embedded
word boundary information to find and capture the data.
These boundary bits are then stripped prior to the word
being sent out of the parallel port.
TABLE 2. Word Boundary Data Bits
24-Bit Data Words
Hex
24-Bit Data Word with Word Boundary
Binary
3FFFFFh
Hex
Binary
0011 1111 1111 1111 1111 1111b
1FFFFFFh
01 1111 1111 1111 1111 1111 1111b
155555h
0101 0101 0101 0101 01010 0101b
1155555h
01 0101 0101 0101 0101 0101 0101b
xxxxxxh
0xxx xxxx xxxx xxxx xxxx xxxxb
1xxxxxxh
01 0xxx xxxx xxxx xxxx xxxx xxxxb
LVCMOS Data I/O
Differential I/O Circuitry
The LVCMOS input buffers have a nominal threshold value
equal to ½ of VDDP. The input buffers are only operational
when the device is operating as a serializer. When the
device is operating as a deserializer the inputs are gated
off to conserve power.
The differential I/O circuitry is a low power variant of LVDS.
The differential outputs operate in the same fashion as
LVDS by sourcing and sinking a balanced current through
the output pair. Like LVDS an input source termination
resistor is required to develop a voltage at the differential
input pair. The FIN24A device incorporates an internal termination resistor on the CKSI receiver and a gated internal
termination resistor on the DS input receiver. The gated termination resistor insures proper termination regardless of
direction of data flow.
During power-down mode the differential inputs will be disabled and powered down and the differential outputs will be
placed in a HIGH-Z state.
The LVCMOS 3-STATE output buffers are rated for a
source/sink current of 2 mAs at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH the bi-directional LVCMOS
I/Os will be in a HIGH-Z state. Under purely capacitive load
conditions the output will swing between GND and VDDP.
The LVCMOS I/O buffers incorporate bushold functionality
to allow for pins to maintain state when they are not driven.
The bushold circuitry only consumes power during signal
transitions.
FIGURE 7. Bi-directional Differential I/O Circuitry
FIGURE 6. LVCMOS I/O
7
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FIN24A
Embedded Word Clock Operation
FIN24A
Preliminary
PLL Circuitry
viding a CKREF signal the PLL will power-up and goes
through a lock sequence. One must wait the specified number of clock cycles prior to capturing valid data into the parallel port.
An alternate way of powering down the PLL is by stopping
the CKREF signal either HIGH or LOW. Internal circuitry
detects the lack of transitions and shuts the PLL and serial
I/O down. Internal references will not however be disabled
allowing for the PLL to power-up and re-lock in a lesser
number of clock cycles than when exiting Mode 0. When a
transition is seen on the CKREF signal the PLL will once
again be reactivated.
The CKREF input signal is used to provide a reference to
the PLL. The PLL will generate internal timing signals
capable of transferring data at 26 times the incoming
CKREF signal. The output of the PLL is a Bit Clock that is
used to serialize the data. The bit clock is also sent source
synchronously with the serial data stream.
There are two ways to disable the PLL. The PLL can be
disabled by entering the Mode 0 state (S1 S2 0). The
PLL will disable immediately upon detecting a LOW on
both the S1 and S2 signals. When any of the other modes
are entered by asserting either S1 or S2 HIGH and by pro-
Application Mode Diagrams
Unidirectional Data Transfer
FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer
Slave Operation: The device will...
Figure 8 shows the basic operation diagram when a pair of
SerDes is configured in an unidirectional operation mode.
1. Be configured as a deserializer at power-up based on
the value of the DIRI signal.
2. Accept an embedded word boundary bit clock on CKSI.
Master Operation: The device will...
(Please refer to Figure 8)
1. During power-up the device will be configured as a
serializer based on the value of the DIRI signal.
3. Deserialize the DS Data stream using the CKSI input
clock.
4. Write parallel data onto the DP_S port and generate
the CKP_S. CKP_S will only be generated when a valid
data word occurs.
2. Accept CKREF_M word clock and generate a bit clock
with embedded word boundary. This bit clock will be
sent to the slave device through the CKSO port.
3. Receive parallel data on the rising edge of
STROBE_M.
4. Generate and transmit serialized data on the DS signals which is source synchronous with CKSO.
5. Generate an embedded word clock for each strobe signal.
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8
Preliminary
FIN24A
Application Mode Diagrams
(Continued)
FIGURE 9. Unidirectional Serializer and Deserializer
FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction
the Camera interface at the base. When DIRI, on the righthand FIN24A goes LOW data will be sent from the baseband process to the LCD. The direction is then changed at
DIRO on the right-hand FIN24A indicating to the left-hand
FIN24A to change direction. Data will be sent from the
Base LCD Unit to the LCD. The DIRO pin on the left-hand
FIN24A is used to indicate to the base control unit that the
signals are changing direction and the LCD is now available to be sent data. DIRI on the right-hand FIN24A could
typically use a timing reference signal such as VSYNC
from the camera interface to indicate direction change. A
derivative of this signal may be required in order to make
sure that no data is lost on the final data transfer.
Figure 10 shows a half duplex connectivity diagram. This
connectivity allows for two unidirectional data streams to
be sent across a single pair of SerDes devices. Data will be
sent on a frame by frame basis. For this mode of operation
to work there needs to be some synchronization between
when the Camera sends its data frame and when the LCD
sends its data. One option for this is to have the LCD send
data during the camera blanking period. External logic may
need to be provided in order for this mode of operation to
work.
Devices will alternate frames of data controlled by a direction control and a direction sense. When DIRI, on the righthand FIN24A is HIGH, data will be sent from the Camera to
9
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FIN24A
Preliminary
Absolute Maximum Ratings(Note 2)
0.5V to 4.6V
0.5V to 4.6V
Supply Voltage (VDD)
ALL Input/Output Voltage
LVDS Output Short Circuit Duration
Continuous
Storage Temperature Range (TSTG)
65qC to 150qC
150qC
Maximum Junction Temperature (TJ)
Recommended Operating
Conditions
2.775V r 5.0%V
Supply Voltage (VDDA, VDDS)
Supply Voltage (VDDP)
1.65V to 3.6V
Operating Temperature (TA) (Note 2)
10qC to 70qC
Supply Noise Voltage (VDDA-PP)
100 mVP-P
Lead Temperature (TL)
260qC
(Soldering, 4 seconds)
ESD Rating
Human Body Model, 1.5K:, 100pF
!2kV
!200V
Machine Model, 0:, 200pF
Note 2: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Min
Test Conditions
Typ
Max
(Note 3)
Unit
LVCMOS I/O
VIH
Input High Voltage
0.65 x VDDP
VDDP
VIL
Input Low Voltage
GND
0.35 x VDDP
VOH
Output High Voltage
2.0 mA
IOH
VOL
Output Low Voltage
IOL
2.0 mA
VDDP
3.3 r 0.3
VDDP
2.5 r 0.2
VDDP
1.8 r 0.15
VDDP
3.3 r 0.3
VDDP
2.5 r 0.2
VDDP
1.8 r 0.15
0.75 x VDDP
Input Current
VIN
Minimum Bushold Currents
VDDP
3.0, VIN
1.95 or 1.05
r35.0
VDDP
2.3, VIN
1.495 or 0.805
r25.0
VDDP
1.65, VIN
1.07 or 0.58
r10.0
Minimum Required Bushold
VDDP
3.6, VIN
2.34 or 1.26
Overdrive Current
VDDP
2.7, VIN
1.76 or 0.945
VDDP
1.95, VIN
1.268 or 0.682
Input/Output Power-Off
VDDP
0V, VDDS
0, VDDA
Leakage Current
ALL LVCMOS Inputs/ Outputs 0V to 3.6V
II(OD)
IOFF
V
5.0
IIN
II(Hold)
0V to 3.6V
V
0.25 x VDDP
V
5.0
PA
uA
r200
r150
uA
r75.0
0
r5.0
PA
350
mV
15.0
mV
DIFFERENTIAL I/O
VOD
Output Differential Voltage
'VOD
VOD Magnitude Change from
Differential LOW-to-HIGH
VOS
Offset Voltage
'VOS
Offset Magnitude Change from
RL
100 :, See Figure
RL
100 :, See Figure
RL
100 :, See Figure
150
VDD
2.775 r 5%
225
925
Differential LOW-to-HIGH
IOS
Short Circuit Output Current
VOUT
0V
Driver Disabled
IOZ
Disabled Output Leakage Current DP
VTH
Differential Input Threshold HIGH See Figure 12 and Table 2
0V to VDDP, DIRI
VTL
Differential Input Threshold LOW
See Figure 12 and Table 2
Input Common Mode Range
VDD
2.775 r 5%
RTRM0
CKSI Internal Receiver
VID
225 mV, VIC
Termination Resistor
|CKSI CKSI|
DS I/O Termination Resistor
VID
|DS
225 mV, VIC
DSI|
r1.0
V DDP
VICM
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2.5
Driver Enabled
(Note 4)
925 mV, DIRI
VID
10
mV
5.0
mA
r5.0
PA
r10.0
100
0
VID
925 mV, DIRI
mV
15.0
0
PA
mV
100
mV
300
925
1550
mV
80.0
100
120
80.0
100
120
:
Preliminary
Symbol
IIN
(Continued)
Parameter
Input Current
Min
Test Conditions
VIN
Typ
Max
(Note 3)
VDD 0.3V or 0V
VDD
FIN24A
DC Electrical Characteristics
r20.0
0V or VDD
Unit
PA
Note 3: Typical Values are given for VDD 2.5V and TA 25qC. Positive current values refer to the current flowing into device and negative values means
current flowing out of pins. Voltage are referenced to GROUND unless otherwise specified (except 'VOD and VOD).
Note 4: The definition of short-circuit includes all the possible situations. For example, the short of differential pairs to Ground, the short of differential pairs
(No Grounding) and either line of differential pairs tied to Ground.
Power Supply Currents
Symbol
IDDA1
IDDA2
IDDS1
IDDS2
IDDS
IDD_PD
Parameter
Supply Current
NOCKREF, S2
0, S1
1, DIR
All DP and Control Inputs at 0V or VDD
Supply Current
NOCKREF, S2
0, S1
1, DIR
0
VDDS Serializer Static
All DP and Control Inputs at 0V or VDD
Supply Current
NOCKREF, S2
0, S1
1, DIR
1
VDDS Deserializer Static
All DP and Control Inputs at 0V or VDD
Supply Current
NOCKREF, S2
VDDA Static
All DP and Control Inputs at 0V or VDD
Supply Current
S1
S2
0
VDD Power-Down Supply Current
S1
S2
0,
IDDA IDDS IDDP
0, S1
1, DIR
IDDA IDDS IDDP
CKREF
DIRI
STROBE
H
See Figure 13
1:26 Dynamic Deserializer
Power Supply Current
IDD_DES1
IDDA IDDS IDDP
0
Typ
Max
Units
TBD
TBD
PA
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
TBD
TBD
mA
5.0
PA
All Inputs at GND or VDD
26:1 Dynamic Serializer
IDD_SER1
IDD_SER2
1
VDDA Deserializer Static
Power Supply Current
IDD_DES1
Min
All DP and Control Inputs at 0V or VDD
IDD_PD
IDD_SER1
Test Conditions
VDDA Serializer Static
CKREF
L
2 MHz
TBD
TBD
H
5 MHz
TBD
TBD
S2
H
5 MHz
TBD
TBD
S1
L
15 MHz
TBD
TBD
S2
H
10 MHz
TBD
TBD
S1
H
30 MHz
TBD
TBD
S2
L
2 MHz
TBD
TBD
S1
H
5 MHz
TBD
TBD
L
S2
H
5 MHz
TBD
TBD
See Figure 13
S1
L
15 MHz
TBD
TBD
S2
H
10 MHz
TBD
TBD
S1
H
30 MHz
TBD
TBD
DIRI
STROBE
S2
S1
26:1 Dynamic Serializer Power
NO CKREF
2 MHz
TBD
TBD
Supply Current
STROBE o Active
5 MHz
TBD
TBD
IDD_SER2
IDDA IDDS IDDP
CKSI
DIRI
15X Strobe
H
See Figure 13
11
10 MHz
TBD
TBD
15 MHz
TBD
TBD
30 MHz
TBD
TBD
mA
mA
mA
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FIN24A
Preliminary
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Serializer Electrical Characteristics
tTCP
fREF
CKREF Clock Period
See Figure 17
S2
0 S1
1
200
(2 MHz - 30 MHz)
CKREF
STROBE
S2
1 S1
0
66.0
S2
1 S1
1
33.0
100
1.1 *fST
15.0
CKREF Frequency Relative
CKREF
S2
0 S1
1
to Strobe Frequency
does not equal
S2
1 S1
0
STROBE
S2
1 S1
1
500
T
200
ns
5.0
MHz
30.0
tCPWH
CKREF Clock High Time
TBD
0.5
TBD
T
tCPWL
CKREF Clock Low Time
TBD
0.5
TBD
T
tCLKT
LVCMOS Input Transition Time
See Figure 17
tSPWH
STROBE Pulse Width HIGH
See Figure 17
tSPWL
STROBE Pulse Width LOW
See Figure 17
fMAX
Maximum Serial Data Rate
CKREF x 26
TBD
5.0
ns
ns
5.0
ns
S2
0 S1
1
52.0
130
S2
1 S1
0
130
390
S2
1 S1
1
260
780
Mb/s
Serializer AC Electrical Characteristics
tTLH
Differential Output Rise Time (20% to 80%)
tTHL
Differential Output Fall Time (80% to 20%)
See Figure 14
tSTC
DP[n] Setup to STROBE
DIRI
tHTC
DP[n] Hold to STROBE
See Figure 16 (f 10 MHz)
tTCCD
Transmitter Clock Input to
See Figure 20, DIRI
Clock Output Delay
CKREF
tSPOS
CKSO Position Relative to DS
1
1,
STROBE
See Figure 23, (Note 5)
CKREF Serialization Mode
See Figure 23, (Note 5)
No CKREF Serialization Mode
0.6
0.9
ns
0.6
0.9
ns
2.5
ns
0
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
PLL AC Electrical Characteristics Specifications
tJCC
CKSO Clock Out Jitter (Cycle-to-Cycle)
(Note 6)
tTPLLS0
Serializer Phase Lock Loop Stabilization
Time
See Figure 19
TBD
tTPLLD0
PLL Disable Time Loss of Clock
See Figure 24, (Note 7)
tTPLLD1
PLL Power-Down Time
See Figure 25
3.0
ns
1000
Cycles
10.0
us
20.0
ns
Deserializer AC Electrical Characteristics
tS_DS
Serial Port Setup Time, DS-to-CKSI
Figure 22, (Note 8)
500
ps
tH_DS
Serial Port Hold Time, DS-to-CKS
Figure 22, (Note 8)
500
ps
tRCOP
Deserializer Clock Output (CKP OUT) Period Figure 18
tRCOL
CKP OUT Low Time
tRCOH
CKP OUT High Time
tPDV
Data Valid to CKP LOW
33.0
Figure 18 (Rising Edge Strobe)
Serializer Source STROBE CKREF
Where a (1/f)/26 (Note 9)
Figure 18 (Rising Edge Strobe)
Where a
500
ns
13a-3
13a3
ns
13a-3
13a3
ns
6a3
ns
6a-3
T
6a
(1/f)/26 (Note 9)
tROLH
Output Rise Time (20% to 80%)
CL
8 pF
2.5
5.0
ns
tROHL
Output Fall time (80% to 20%)
Figure 15
2.5
5.0
ns
Note 5: Skew is measured from either the rising or falling edge of the clock (CKSO) relative to the center of the data bit (DSO). Both outputs should have
identical load conditions for this to be valid.
Note 6: This jitter specification is based on the assumption that PLL has a REF Clock with cycle-to-cycle input jitter less than 2ns.
Note 7: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The
specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Note 8: Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state.
Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew
from the serializer, load variations and ISI and jitter effects.
Note 9: Rising edge of CKP will appear approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP will occur approximately 6 bit
times after a data transition. Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to
STROBE for the serializer the CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain 13 bit times.
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12
Preliminary
Symbol
Parameter
tPHL_DIR,
Propagation Delay
tPLH_DIR
DIRI-to-DIRO
tPLZ,
Propagation Delay
tPHZ
DIRI-to-DP
tPZL,
Propagation Delay
tPZH
DIRI-to-DP
Test Conditions
Min
Typ
Max
Units
TBD
TBD
7.0
ns
DIRI LOW-to-HIGH
7.0
ns
DIRI HIGH-to-LOW
10.0
ns
7.0
ns
10.0
ns
7.0
ns
10.0
ns
Max
Units
DIRI LOW-to-HIGH or HIGH-to-LOW
tPLZ,
Deserializer Disable Time:
DIRI
tPHZ
S0 or S1 to DP
S1(2)
0,
0 and S2(1)
tPZL,
Deserializer Enable Time:
DIRI
tPZH
S0 or S1 to DP
S1(2)
tPLZ,
Serializer Disable Time:
DIRI
tPHZ
S0 or S1 to CKSO, DS
S1(2)
tPZL,
Serializer Enable Time:
DIRI
tPZH
S0 or S1 to CKSO, DS
S1(2) and S2(1)
LOW-to-HIGH
Figure 26
LOW-to-HIGH
Figure 26
0,
0 and S2(1)
1,
0 and S2(1)
HIGH-to-LOW Figure 25
1,
LOW-to-HIGH
Figure 25
Capacitance
Symbol
CIN
CIO
CIO-DIFF
Parameter
Test Conditions
Capacitance of Input Only Signals,
DIRI
1, S1
CKREF, STROBE, S1, S2, DIRI
VDD
2.5V
Capacitance of Parallel Port Pins
DIRI
1, S1
DP1:12
VDD
2.5V
Capacitance of Differential I/O Signals DIRI
S1
0,
0,
0, PwnDwn
0, VDD
0;
2.5V
13
Min
Typ
TBD
pF
TBD
pF
TBD
pF
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FIN24A
Control Logic Timing Controls
FIN24A
Preliminary
AC Loading and Waveforms
Note A: For All input pulses, t R or tF 1 ns
FIGURE 12. Differential Receiver Voltage Definitions
FIGURE 11. Differential LpLVDS Output DC Test Circuit
Note: The Worst Case test pattern produces a maximum toggling of internal digital circuits, LpLVDS I/O and LVCMOS I/O with the PLL operating at the reference frequency unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD
values. Typical values are measured at VDD 2.5V.
FIGURE 13. “Worst Case” Serializer Test Pattern
FIGURE 14. LpLVDS Output Load
and Transition Times
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FIGURE 15. LVCMOS Output Load
and Transition Times
14
Preliminary
Setup: MODE0
“0” or “1”, MODE1
“1”, SER/DES
FIN24A
AC Loading and Waveforms
(Continued)
“1”
FIGURE 17. LVCMOS Clock Parameters
FIGURE 16. Serial Setup and Hold Time
Setup: EN_DES
“1”, CKSI and DSI are valid signals
Note: CKREF Signal is free running.
FIGURE 18. Deserializer Data Valid Window Time
and Clock Output Parameters
Note: STROBE
FIGURE 19. Serializer PLL Lock Time
CKREF
FIGURE 20. Serializer Clock Propagation Delay
FIGURE 21. Deserializer Clock Propagation Delay
15
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FIN24A
Preliminary
AC Loading and Waveforms
(Continued)
FIGURE 23. Differential Output Signal Skew
FIGURE 22. Differential Input Setup and Hold Times
Note: CKREF Signal can be stopped either HIGH or LOW
FIGURE 24. PLL Loss of Clock Disable Time
FIGURE 25. PLL Power-Down Time
Note: If S1(2) transitioning then S2(1) must
Note: CKREF must be active and PLL must be stable
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0 for test to be valid
FIGURE 27. Deserializer Enable and Disable Times
FIGURE 26. Serializer Enable and Disable Time
16
Preliminary
FIN24A
Tape and Reel Specification
TAPE FORMAT for USS-BGA
Dimensions are in millimeters
Package
3.5 x 4.5
A0
B0
D
D1
E
F
K0
P1
P0
P2
T
TC
W
WC
r0.10
r0.10
r0.05
min
r0.1
r0.1
r0.1
TYP
TYP
r0/05
TYP
r0.005
r0.3
TYP
TBD
TBD
1.55
1.5
1.75
5.5
1.1
8.0
4.0
2.0
0.3
0.07
12.0
9.3
Note: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements
(see sketches A, B, and C).
Dimensions are in millimeters
Tape Width
Dia A
Dim B
Dia C
Dia D
Dim N
Dim W1
Dim W2
Dim W3
max
min
0.5/0.2
min
min
2.0/0
max
(LSL - USL)
8
330
1.5
13.0
20.2
178
8.4
14.4
7.9 a 10.4
12
330
1.5
13.0
20.2
178
12.4
18.4
11.9 a 15.4
16
330
1.5
13.0
20.2
178
16.4
22.4
15.9 a 19.4
17
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FIN24A
Preliminary
Tape and Reel Specification
TAPE FORMAT for MLP
Package
Designator
(Continued)
Tape
Number
Cavity
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
MLX
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
MLP Embossed Tape Dimension
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Cover Tape
18
Preliminary
FIN24A
Physical Dimensions inches (millimeters) unless otherwise noted
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
Package Number BGA042A
19
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FIN24A PSerDes Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
(Preliminary)
Preliminary
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
Package Number MLP040A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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20