PRELIMINARY DATA SHEET 4GB Fully Buffered DIMM EBE41FE4ABHT EBE41FE4ABHL Specifications Features • Density: 4GB • Organization 512M words × 72 bits, 2 ranks • Mounting 36 pieces of 1G bits DDR2 SDRAM with sFBGA • Package 240-pin fully buffered, socket type dual in line memory module (FB-DIMM) PCB height: 30.35mm Lead pitch: 1.00mm Advanced Memory Buffer (AMB): 655-ball FCBGA Lead-free (RoHS compliant) • Power supply DDR2 SDRAM: VDD = 1.8V ± 0.1V AMB: VCC = 1.5V + 0.075V/−0.045 • Data rate: 667Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C • JEDEC standard Raw Card D Design • Industry Standard Advanced Memory Buffer (AMB) • High-speed differential point-to-point link interface at 1.5V (JEDEC draft spec) 14 north-bound (NB) high speed serial lanes 10 south-bound (SB) high speed serial lanes • Various features/modes: MemBIST and IBIST test functions Transparent mode and direct access mode for DRAM testing Interface for a thermal sensor and status indicator • Channel error detection and reporting • Automatic DDR2 SDRAM bus and channel calibration • SPD (serial presence detect) with 1piece of 256 byte serial EEPROM Note: Warranty void if removed DIMM heat spreader. Performance FB-DIMM System clock frequency 167MHz DDR2 SDRAM Speed grade Peak channel throughput FB-DIMM link data rate Speed Grade DDR data rate PC2-5300F 8.0GByte/s 4.0Gbps DDR2-667 (5-5-5) 667Mbps Document No. E1010E20 (Ver. 2.0) Date Published January 2007 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2006-2007 EBE41FE4ABHT, EBE41FE4ABHL Ordering Information Part number DIMM speed grade Component JEDEC speed bin (CL-tRCD-tRP) Mounted devices* EBE41FE4ABHT-6E-E PC2-5300F DDR2-667 (5-5-5) 1G bits DDR2 SDRAM IDT Rev. C1 EBE41FE4ABHL-6E-E PC2-5300F DDR2-667 (5-5-5) 1G bits DDR2 SDRAM INTEL Rev. D1 1 Mounted AMB* 2 Notes: 1. Please refer to 1Gb DDR2 datasheet (E0852E) for detailed operation part and timing waveforms. 2. Please refer to the following documents for detailed operation part and timing waveforms. Advanced Memory Buffer (AMB) specification FB-DIMM Architecture and Protocol specification Part Number E B E 41 F E 4 A B H T - 6E - E Environment code E: Lead Free (RoHS compliant) Elpida Memory Type B: Module DRAM Speed Grade 6E: DDR2-667 (5-5-5) Product Family E: DDR2 Density / Rank 41: 4GB/2-rank AMB Device Information T: IDT, Rev.C1 L: Intel, Rev.D1 Module Type F: Fully Buffered Module Outline H: 240-pin DIMM (Stacked FBGA) Mono Density E: 1Gbit Die Rev. (Mono) Mono Organization 4: x4 Power Supply, Interface A: 1.8V, SSTL_1.8 Preliminary Data Sheet E1010E20 (Ver. 2.0) 2 EBE41FE4ABHT, EBE41FE4ABHL Advanced Memory Buffer Overview The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the FB-DIMM channel. The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit density. The AMB is the buffer that isolates the DRAMs from the channel. Advanced Memory Buffer Functionality The AMB will perform the following FB-DIMM channel functions. • Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. • Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. • If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. • Detects errors on the channel and reports them to the host memory controller. • Support the FB-DIMM configuration register set as defined in the register chapters. • Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. • Provides a read buffer FIFO and a write buffer FIFO. • Supports an SMBus protocol interface for access to the AMB configuration registers. • Provides logic to support MemBIST and IBIST design for test functions. • Provides a register interface for the thermal sensor and status indicator. • Functions as a repeater to extend the maximum length of FB-DIMM links. Preliminary Data Sheet E1010E20 (Ver. 2.0) 3 EBE41FE4ABHT, EBE41FE4ABHL Advanced Memory Buffer Block Diagram Southbound 10×2 Data in Reference clock Southbound Data out 10×2 Data merge PLL RE-time 1×2 Re-synch PISO Demux /RESET Reset control 10×12 10×12 Link init SM and control and CSRs Thermal sensor Init patterns Mux 4 IBIST-RX failover Command decoder & CRC check DRAM clock IBIST-TX 4 DRAM clock LAI logic DRAM Command Mux Command out DRAM interface DDR state controller and CSRs Core controller and CSRs Write data FIFO Mux DRAM address and command copy1 29 DRAM address and command copy2 72+18×2 External MemBIST DDR calibration IBIST-TX LAI controller Data in Sync & idle pattern generator Data CRC generator and Read FIFO SMBus Data out 29 Mux IBIST-RX Link init SM and control and CSRs failover 14×6×2 SMBus controller NB LAI Buffer 14×12 PISO Demux Re-synch RE-time Data merge Northbound 14×2 Data Out 14×2 Northbound Data In Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains. Preliminary Data Sheet E1010E20 (Ver. 2.0) 4 DRAM data and strobes EBE41FE4ABHT, EBE41FE4ABHL Interfaces Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a FB-DIMM. NB FBD in Link NB FBD out Link SB FBD in Link AMB SB FBD out Link Secondary or to optional next FBD Primary or Host Direction Memory Interface SMB Block Diagram AMB Interfaces Interface Topology The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives the data to the next DIMM until the host is reached. Host Nourthbound Southbound AMB AMB AMB AMB n/c n/c Block Diagram FB-DIMM Channel Southbound and Northbound Paths Preliminary Data Sheet E1010E20 (Ver. 2.0) 5 EBE41FE4ABHT, EBE41FE4ABHL High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces The AMB supports one FB-DIMM channel consisting of two bidirectional link interfaces using high-speed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs. Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound on 14 secondary differential pairs. DDR2 Channel The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. There are two copies of address and command signals to support DIMM routing and electrical requirements. Four transfer bursts are driven on the data and check-bit lines at 800MHz. Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The AMB provides four copies of the command clock phase references (CLK [3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble. SMBus Slave interface The AMB supports an SMBus interface to allow system access to configuration register independent of the FB-DIMM link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100kHz. SMBus access to the AMB may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the unique ID. Preliminary Data Sheet E1010E20 (Ver. 2.0) 6 EBE41FE4ABHT, EBE41FE4ABHL Block Diagram VSS /CS1 /CS0 DQS9 DQS0 /DQS0 /DQS9 DM /CS 4 DQ0 to DQ3 DQ0 to DQ3 DQS /DQS D0 DM /CS DQ0 to DQ3 DQS /DQS DM 4 D18 DQ4 to /DQ7 4 DQ0 to DQ3 DQS /DQS D1 DM /CS DQ0 to DQ3 DQS /DQS DM DQ12 to DQ15 D19 DQS2 DQS11 /DQS2 /DQS11 DM /CS 4 DQ0 to DQ3 DQS /DQS D2 DM /CS DQ0 to DQ3 DQS12 /DQS12 DM /CS DQ0 to DQ3 DQS /DQS D3 DM /CS DQ0 to DQ3 DQS /DQS DQS4 DQS13 /DQS13 DM /CS 4 DQ0 to DQ3 DQS /DQS D4 DM /CS DQ0 to DQ3 DQS /DQS D22 DQS5 DQS14 /DQS5 /DQS14 DM /CS DQ40 to DQ43 4 DQ0 to DQ3 DQS /DQS D5 DM /CS DQ0 to DQ3 DQS /DQS D23 D27 D13 /CS DQS /DQS DQ0 to DQ3 D14 DM /CS DQS /DQS DQ0 to DQ3 DM D28 /CS DQS /DQS DQ0 to DQ3 DM CS DQS /DQS DQ0 to DQ3 DM D29 D30 /CS DQS /DQS DQ0 to DQ3 DM D31 /CS DQS /DQS DQ0 to DQ3 D32 DQS15 4 DQ0 to DQ3 DQS /DQS D6 DM /CS DQ0 to DQ3 DQS /DQS DM DQ52 to DQ55 D24 DQS7 DQS16 /DQS7 /DQS16 DM /CS 4 DQ0 to DQ3 DQS /DQS D7 DM /CS DQ0 to DQ3 D25 DQS17 /DQS17 DM /CS DQ0 to DQ3 PN0 to PN13 /PN0 to /PN13 PS0 to PS9 /PS0 to /PS9 DQ0 to DQ63 CB0 to CB7 DQS0 to DQS17 /DQS0 to /DQS17 SCL SDA SA1 to SA2 SA0 /RESET SCK/ /SCK DQS /DQS D8 DM /CS DQ0 to DQ3 D26 4 /CS DQS /DQS DQ0 to DQ3 DM CB4 to CB7 SCL /CS0 -> /CS (D0 to D17) CKE0 -> CKE (D0 to D17) /CS1 -> /CS (D18 to D35) CKE1 -> CKE (D18 to D35) ODT -> ODT (all SDRAMs) BA0 to BA2 (all SDRAMs) A0 to A13 (all SDRAMs) /RAS (all SDRAMs) /CAS (all SDRAMs) /WE (all SDRAMs) CK/ /CK All address/command/control/clock DQS /DQS D15 D16 /CS DQS /DQS DQ0 to DQ3 D17 DM /CS DQS /DQS DQ0 to DQ3 DM /CS DQS /DQS DQ0 to DQ3 DM D33 D34 /CS DQS /DQS DQ0 to DQ3 D35 Serial PD SN0 to SN13 /SN0 to /SN13 SS0 to SS9 /SS0 to /SS9 A M B 4 /CS DQS /DQS DQ0 to DQ3 DM DQ60 to DQ63 DQS8 4 4 DQS /DQS /DQS8 CB0 to CB3 /CS DQS /DQS /DQS15 DM /CS DQ56 to DQ59 4 D12 /CS DQS /DQS DQ0 to DQ3 DM DQ44 to DQ47 DQS6 /DQS6 DQ48 to DQ51 4 D11 /CS DQS /DQS DQ0 to DQ3 DM DQ36 to DQ39 D10 /CS DQS /DQS DQ0 to DQ3 DM 4 DQ28 to DQ31 D21 /DQS4 DQ32 to DQ35 4 /CS DQS /DQS DQ0 to DQ3 DM DQ20 to DQ23 DQS3 4 4 DQS /DQS D20 /DQS3 DQ24 to DQ27 DM DQ0 to DQ3 /DQS10 DM /CS DQ16 to DQ19 D9 DQS10 DQS1 /DQS1 DQ8 to DQ11 /CS DQS /DQS DQ0 to DQ3 U0 WP A0 A1 SDA A2 SA0 SA1 SA2 VTT Teminators VCC AMB VDDSPD VDD VREF * D0 to D35 : 1G bits DDR2 SDRAM U0 : 256 bytes EEPROM VSS Notes: 1. DQ wiring may be changed within a nibble. 2. There are two physical copies of each address/command/control/clock 3. There are four physical copies of each clock. VTT Preliminary Data Sheet E1010E20 (Ver. 2.0) 7 SPD, AMB D0 to D35, AMB D0 to D35 D0 to D35, SPD, AMB EBE41FE4ABHT, EBE41FE4ABHL Pin Configurations Front side 1 pin 121 pin 68 pin 69 pin 120 pin 188 pin 189 pin 240 pin Back side Front side Back side No. Name No. Name No. Name No. Name No. Name No. Name No. Name No. Name 1 VDD 36 VSS 71 /PS0 106 NC 121 VDD 156 VSS 191 /SS0 226 NC 2 VDD 37 PN5 72 VSS 107 VSS 122 VDD 157 SN5 192 VSS 227 VSS 3 VDD 38 /PN5 73 PS1 108 VDD 123 VDD 158 /SN5 193 SS1 228 SCK 4 VSS 39 VSS 74 /PS1 109 VDD 124 VSS 159 VSS 194 /SS1 229 /SCK 5 VDD 40 PN13 75 VSS 110 VSS 125 VDD 160 SN13 195 VSS 230 VSS 6 VDD 41 /PN13 76 PS2 111 VDD 126 VDD 161 /SN13 196 SS2 231 VDD 7 VDD 42 VSS 77 /PS2 112 VDD 127 VDD 162 VSS 197 /SS2 232 VDD 8 VSS 43 VSS 78 VSS 113 VDD 128 VSS 163 VSS 198 VSS 233 VDD 9 VCC 44 NC 79 PS3 114 VSS 129 VCC 164 NC 199 SS3 234 VSS 10 VCC 45 NC 80 /PS3 115 VDD 130 VCC 165 NC 200 /SS3 235 VDD 11 VSS 46 VSS 81 VSS 116 VDD 131 VSS 166 VSS 201 VSS 236 VDD 12 VCC 47 VSS 82 PS4 117 VTT 132 VCC 167 VSS 202 SS4 237 VTT 13 VCC 48 PN12 83 /PS4 118 SA2 133 VCC 168 SN12 203 /SS4 238 VDDSPD 14 VSS 49 /PN12 84 VSS 119 SDA 134 VSS 169 /SN12 204 VSS 239 SA0 15 VTT 50 VSS 85 VSS 120 SCL 135 VTT 170 VSS 205 VSS 240 SA1 16 VID1 51 PN6 86 NC 136 VID0 171 SN6 206 NC 17 /RESET 52 /PN6 87 NC 137 M_TEST 172 /SN6 207 NC 18 VSS 53 VSS 88 VSS 138 VSS 173 VSS 208 VSS 19 NC 54 PN7 89 VSS 139 NC 174 SN7 209 VSS 20 NC 55 /PN7 90 PS9 140 NC 175 /SN7 210 SS9 21 VSS 56 VSS 91 /PS9 141 VSS 176 VSS 211 /SS9 22 PN0 57 PN8 92 VSS 142 SN0 177 SN8 212 VSS 23 /PN0 58 /PN8 93 PS5 143 /SN0 178 /SN8 213 SS5 24 VSS 59 VSS 94 /PS5 144 VSS 179 VSS 214 /SS5 25 PN1 60 PN9 95 VSS 145 SN1 180 SN9 215 VSS 26 /PN1 61 /PN9 96 PS6 146 /SN1 181 /SN9 216 SS6 27 VSS 62 VSS 97 /PS6 147 VSS 182 VSS 217 /SS6 28 PN2 63 PN10 98 VSS 148 SN2 183 SN10 218 VSS 29 /PN2 64 /PN10 99 PS7 149 /SN2 184 /SN10 219 SS7 30 VSS 65 VSS 100 /PS7 150 VSS 185 VSS 220 /SS7 31 PN3 66 PN11 101 VSS 151 SN3 186 SN11 221 VSS 32 /PN3 67 /PN11 102 PS8 152 /SN3 187 /SN11 222 SS8 33 VSS 68 VSS 103 /PS8 153 VSS 188 VSS 223 /SS8 34 PN4 69 VSS 104 VSS 154 SN4 189 VSS 224 VSS 35 /PN4 70 PS0 105 NC 155 /SN4 190 SS0 225 NC Preliminary Data Sheet E1010E20 (Ver. 2.0) 8 EBE41FE4ABHT, EBE41FE4ABHL Pin Description Pin name Pin Type Function SCK, /SCK Input System clock input PN0 to PN13, /PN0 to /PN13 Output Primary northbound data PS0 to PS9, /PS0 to /PS9 Input Primary southbound data SN0 to SN13, /SN0 to /SN13 Input Secondary northbound data SS0 to SS9, /SS0 to /SS9 Output Secondary southbound data SCL Input Serial presence detect (SPD) clock input Input / Output SPD data and AMB SMBus address/data Input SPD address inputs Input Voltage ID SDA SA0 to SA2* 1 VID0 to VID1* /RESET M_TEST* NC 3 2 Input AMB reset signal Input VREF margin test input No connection VCC Power supply AMB core power and AMB channel interface power (1.5V) VDD Power supply DRAM power and AMB DRAM I/O power (1.8V) VTT Power supply DRAM address, Command and clock termination voltage (VDD/2) VDDSPD Power supply SPD power (3.3V) VSS Ground Notes: 1. They are also used to select the DIMM number in the AMB. 2. These pins must be unconnected. 3. Don’t connect in a system. Preliminary Data Sheet E1010E20 (Ver. 2.0) 9 EBE41FE4ABHT, EBE41FE4ABHL Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN/VOUT –0.3 to +1.75 V AMB core power voltage relative to VSS VCC –0.3 to +1.75 V DRAM interface power voltage relative to VSS VDD –0.5 to +2.30 V Termination voltage relative to VSS VTT –0.5 to +2.30 V Storage temperature Tstg –55 to +100 °C Note Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Conditions Parameter Symbol Value Unit Note SDRAM component case temperature TC_DRAM 0 to +95 °C 1 AMB component case temperature TC_AMB 110 °C Note: 1. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. DC Operating Conditions Parameter Symbol min. typ. max. Unit Note AMB supply voltage VCC 1.455 1.50 1.575 V DDR2 SDRAM supply voltage VDD 1.7 1.8 1.9 V Input termination voltage VTT 0.48 × VDD 0.50 × VDD 0.52 × VDD V EEPROM supply voltage VDDSPD 3.0 3.3 3.6 V SPD input high voltage VIH (DC) 2.1 — VDDSPD V 1 SPD input low voltage VIL (DC) — — 0.8 V 1 RESET input high voltage VIH (DC) 1.0 — — V 2 RESET input low voltage VIL (DC) — — 0.5 V 2 Leakage current (RESET) IL –90 — 90 µA 2 Leakage current (link) IL –5 — 5 µA 3 Notes: 1. Applies for SMB and SPD bus signals. 2. Applies for AMB CMOS signal /RESET. 3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification. Preliminary Data Sheet E1010E20 (Ver. 2.0) 10 EBE41FE4ABHT, EBE41FE4ABHL AMB Component Timing For purposes of IDD testing, the following parameters are to be utilized. Parameter Symbol min. typ. max. Units EI Assertion pass-thru timing tEI propagate — — 4 clks EI deassertion pass-thru timing tEID — — bit lock clks EI assertion duration tEI 100 — — clks Resample pass-thru time — TBD — ns Resynch pass-thru Time — TBD — ns Bit lock Interval tBitLock — — 119 frames Frame lock Interval tFrameLock — — 154 frames Note Note: 1. The EI stands for ″Electrical Idle″. Power Specification Parameter and Test Conditions -6E Frequency (Mbps) Parameter 667 Symbol Idle Current, single Idd_Idle_0 or last DIMM Idle Current, first DIMM Active Power Idd_Idle_1 Idd_Active_1 Active Power, data Idd_Active_2 pass through Training Idd_Training (for AMB spec. Not in SPD) Power Supply max. Unit @1.5V 2.60 A @1.8V 3.10 A Total 9.14 W @1.5V 3.40 A @1.8V 3.10 A Total 10.39 W @1.5V 3.90 A @1.8V 5.95 A Total 16.60 W @1.5V 3.70 A @1.8V 2.59 A Total 9.89 W @1.5V 4.00 A @1.8V 2.81 A Total 10.79 W Preliminary Data Sheet E1010E20 (Ver. 2.0) 11 Conditions L0 state, idle (0 BW) Primary channel enabled, Secondary channel disabled CKE high. Command and address lines stable. DRAM clock active. L0 state, idle (0 BW) Primary and secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. L0 state 50% DRAM BW, 67% read, 33% write. Primary and secondary channels enabled. DRAM clock active, CKE high. L0 state 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active. Primary and secondary channels enabled. 100% toggle on all channel lanes DRAMs idle. 0 BW. CKE high, Command and address lines stable. DRAM clock active. Note EBE41FE4ABHT, EBE41FE4ABHL Reference Clock Input Specifications*1 Parameter Reference clock frequency@ 3.2Gb/s (nominal 133.33MHz) Reference clock frequency@ 4.0 Gb/s (nominal 166.67MHz) Single-ended maximum voltage Symbol min. max. Units Notes fRefclk-3.2 126.67 133.40 MHz 2, 3, 4 fRefclk-4.0 158.33 166.75 MHz 2, 3, 4 Vmax 1.15 V 5, 7 Single-ended minimum voltage Vmin −0.3 V 5, 8 Differential voltage high VRefclk-diff-ih 150 mV 6 Differential voltage low VRefclk-diff-il −150 mV 6 Absolute crossing point VCross 250 550 mV 5, 9, 10 VCross variation VCross-delta 140 mV 5, 9, 11 AC common mode VSCK-cm-acp-p 225 mV 12 Rising and falling edge rates ERRefclk-diff-Rise, ERRefclk-diff-Fall 0.6 4.0 V/ns 6, 13 % Mismatch between rise and fall edge rates ERRefclk-Match 20 % 6, 14 Duty cycle of reference clock TRefclk-Dutycycle 40 60 % 6 Ringback voltage threshold VRB-diff −100 100 mV 6, 15 Allowed time before ringback TStable 500 ps 6, 15 Clock leakage current II_CK −10 10 µA 16, 17 Clock input capacitance CI_CK 0.5 2.0 pF 17 Clock input capacitance delta CI_CK (∆) −0.25 0.25 pF Difference between RefClk and RefClk# input capacitance Transport delay TD NSAMPLE 10 Reference clock jitter (rms), filtered 5 ns 18, 19 periods 20 3.0 ps 21, 22 30 ps TBD ps 12 TREF-JITTER-RMS Reference clock jitter (peak-to-peak) due TREF-SSCp-p to spectrum clocking effects Reference clock jitter difference between TREF-JITTERadjacent AMB DELTA Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”. 2. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times the fixed PLL multiplication factor for the FB-DIMM channel (6:1). fdata = 2000MHz for a 4.0Gbps FBDIMM channel and so on. 3. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency. 4. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only required for those data rates that are supported by the device under test. 5. Measurement taken from single-ended waveform. 6. Measurement taken from differential waveform. 7. Defined as the maximum instantaneous voltage including overshoot. 8. Defined as the minimum instantaneous voltage including undershoot. 9. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 11. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in for any particular system. 12. The majority of the reference clock AC common mode occurs at high frequency (i.e., the reference clock frequency). Preliminary Data Sheet E1010E20 (Ver. 2.0) 12 EBE41FE4ABHT, EBE41FE4ABHL 13. Measured from −150mV to + 150mV on the differential waveform. The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential 0V crossing. 14. Edge rate matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ± 75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. The rising edge rate of REFCLK+ should be compared to the falling edge rate of REFCLK-. The maximum allowed difference should not exceed 20% of the slowest edge 15. Tstable is the time the differential clock must maintain a minimum ±150mV differential voltage after rising /falling edges before it is allowed to droop back into the ±100mV differential range. 16.Measured with a single-ended input voltage of 1V. 17. Applies to RefClk and RefClk#. 18. This parameter is not a direct clock output parameter but it indirectly determines the clock output parameter TREF-JITTER. 19. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock source, through the TX, to data arrival at the data sampling point in the RX. The clock path is defined from the reference clock source to clock arrival at the same sampling point. The path delays are caused by copper trace routes, on-chip routing, on-chip buffering, etc. They include the time-of-flight of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these delays are modeled by the PLL transfer functions. 20. Direct measurement of phase jitter records over NSAMPLE periods may be impractical. It is expected that the jitter will be measured over a smaller, yet statistically significant, sample size and the total jitter at NSAMPLE samples extrapolated from an estimate of the sigma of the random jitter components. 21. Measured with SSC enabled on reference clock generator. 22. As “measured” after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRX-Total-MIN parameters. Preliminary Data Sheet E1010E20 (Ver. 2.0) 13 EBE41FE4ABHT, EBE41FE4ABHL Differential Transmitter Output Specifications*1 Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to-peak output voltage for regular voltage swing Differential peak-to-peak output voltage for small voltage swing Symbol min. max. Unit Comments VTX-DIFFp-p_L 900 1300 mV VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- | Measured as note 2 VTX-DIFFp-p_R 800 mV VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- | Measured as note 2 VTX-DIFFp-p_S 520 mV VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- | Measured as note 2 Defined as: VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2 Measured as note 2 Defined as: VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 3 DC common code output voltage for large voltage swing VTX-CM_L 375 mV DC common code output voltage for small voltage swing VTX-CM_S 135 280 mV VTX-DE-3.5-Ratio −3.0 −4.0 dB 2, 4, 5 VTX-DE-6.0-Ratio −5.0 −7.0 dB 2, 4, 5 De-emphasized differential output voltage ratio for -3.5dB de-emphasis De-emphasized differential output voltage ratio for -6dB de-emphasis VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 AC peak-to-peak common mode output voltage for large VTX-CM-ACp-p L swing 90 mV AC peak-to-peak common mode output voltage for regular swing VTX-CM-ACp-p R 80 mV AC peak-to-peak common mode output voltage for small VTX-CM-ACp-p S swing 70 mV VTX-IDLE-SE 50 mV 7, 8 VTX-IDLE-SE-DC 20 mV 7, 8, 9 VTX-IDLE-DIFFp-p 40 mV 8 VTX-SE −75 750 mV 2, 10 Minimum TX eye width TTX-Eye-MIN 0.7 UI 2, 11, 12 Maximum TX deterministic jitter TTX-DJ-DD 0.2 UI 2, 11, 12, 13 Instantaneous pulse width TTX-PULSE 0.85 UI 14 30 90 ps Given by 20%-80% voltage levels. Measured as note 2 20 ps Maximum single-ended voltage in EI condition, DC + AC Maximum single-ended voltage in EI condition, DC only Maximum peak-to-peak differential voltage in EI condition Single-ended voltage (w.r.t.VSS) on D+/D- Differential TX output rise/fall TTX-RISE, time TTX-FALL Mismatch between rise and TTX-RF-MISMATCH fall times Differential return loss RLTX-DIFF 8 dB Common mode return loss RLTX-CM 6 dB Preliminary Data Sheet E1010E20 (Ver. 2.0) 14 Measured over 0.1GHz to 2.4GHz. See also note 15 Measured over 0.1GHz to 2.4GHz. See also note 15 EBE41FE4ABHT, EBE41FE4ABHL Parameter Symbol min. max. Unit Comments Transmitter termination resistance RTX 41 55 Ω 16 % RTX-Match-DC = 2×|RTX-D+ − RTX-D-| / (RTX-D+ + RTX-D-) Bounds are applied separately to high and low output voltage states D+/D- TX resistance difference RTX-Match-DC 4 Lane-to-lane skew at TX LTX-SKEW 1 100 + 3UI ps 17, 19 Lane-to-lane skew at TX LTX-SKEW 2 100 + 2UI ps 18, 19 Maximum TX Drift (resync mode) Maximum TX Drift (resample mode only) TTX-DRIFT-RESYNC 240 ps 20 TTX-DRIFTRESAMPLE 120 ps 20 Bit Error Ratio BER 10 -12 21 Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”. 2. Specified at the package pins into a timing and voltage compliance test load. Common-mode measurements to be performed using a 101010 pattern. 3. The transmitter designer should not artificially elevate the common mode in order to meet this specification. 4. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. 5. De-emphasis shall be disabled in the calibration state. 6. Includes all sources of AC common mode noise. 7. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle condition. 8. Specified at the package pins into a voltage compliance test load. Transmitters must meet both singleended and differential output EI specifications. 9. This specification, considered with VRX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered. 10. The maximum value is specified to be at least (VTX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2) 11. This number does not include the effects of SSC or reference clock jitter. 12. These timing specifications apply to resync mode only. 13. Defined as the dual-dirac deterministic jitter. 14. Pulse width measured at 0 V differential. 15. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed. 16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin. 17. Lane to Lane skew at the Transmitter pins for an end component. 18. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT). 19. This is a static skew. An FB-DIMM component is not allowed to change its lane to lane phase relationship after initialization. 20. Measured from the reference clock edge to the center of the output eye. This specification must be met across specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver. 21. BER per differential lane. Preliminary Data Sheet E1010E20 (Ver. 2.0) 15 EBE41FE4ABHT, EBE41FE4ABHL Differential Receiver Input Specifications*1 Parameter Symbol min. max. Unit Comments VRX-DIFFp-p 170 1300 mV VRX-DIFFp-p = 2×|VRX-D+ -VRX-D-| Measured as note 2 VRX-IDLE-SE 65 mV 3, 4, 5, 6 VRX-IDLE-SE-DC 35 mV 3, 4, 5, 6, 7 VRX-IDLE-DIFFp-p 65 mV 4, 5, 6 VRX-SE −300 900 mV 5 VRX-DIFF-PULSE 85 mV 5, 8 VRX-DIFF-ADJ RATIO- HI 3.0 5, 9 VRX-DIFF-ADJ RATIO 4.0 5, 9 Maximum RX inherent timing error TRX-TJ-MAX 0.4 UI 5, 10, 11 Maximum RX inherent deterministic timing error Single-pulse width at zero-voltage crossing Single-pulse width at minimumlevel crossing TRX-DJ-DD 0.3 UI 5, 10, 11, 12 TRX-PW-ZC 0.55 UI 5, 8 TRX-PW-ML 0.2 UI 5, 8 TRX-RISE, TRX-FALL 50 ps Given by 20%-80% voltage levels. Differential peak-to-peak input voltage Maximum single-ended voltage for EI condition (AC + DC) Maximum single-ended voltage for EI condition (DC only) Maximum peak-to-peak differential voltage for EI condition Single-ended voltage (w.r.t. VSS) on D+/DSingle-pulse peak differential input voltage Amplitude ratio between adjacent symbols, 1100mV < VRX-DIFFp-p <= 1300mV Amplitude ratio between adjacent symbols, VRX-DIFFp-p <= 1100mV Differential RX input rise/fall time Defined as: VRX-CM = DC (avg) of |VRX-D+ + VRX-D-|/2 Measured as note 2. See also note 13 VRX-CM-AC = Max |VRX-D+ + VRX-D-|/2 – Min |VRX-D+ + VRX-D-|/2 Measured as note 2 Common mode of the input voltage VRX-CM 120 400 mV AC peak-to-peak common mode of VRX-CM-ACp-p input voltage 270 mV Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p VRX-CM-EH-Ratio 45 % Differential return loss RLRX-DIFF 9 dB Common mode return loss RLRX-CM 6 dB RX termination resistance RRX 41 55 Ω D+/D- RX resistance difference RRX-Match-DC 4 % Lane-to-lane PCB skew at Rx LRX-PCB-SKEW 6 UI Minimum RX Drift Tolerance TRX-DRIFT 400 ps 18 Minimum data tracking 3dB bandwidth FTRK 0.2 MHz 19 Electrical idle entry detect time TEI-ENTRY DETECT 60 ns 20 Electrical idle exit detect time TEI-EXIT -DETECT 30 BER Bit Error Ratio 10 Preliminary Data Sheet E1010E20 (Ver. 2.0) 16 14 Measured over 0.1GHz to 2.4GHz. See also note 15 Measured over 0.1GHz to 2.4GHz. See also note 15 16 RRX-Match-DC = 2×|RRX-D+ − RRX-D-| / (RRX-D+ + RRX-D-) Lane-to-lane PCB skew at the receiver that must be tolerated. See also note 17 ns -12 21 EBE41FE4ABHT, EBE41FE4ABHL Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”. 2. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the pin. 3. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle condition. Worst-case margins are determined by comparing EI levels with common mode levels during normal operation for the case with transmitter using small voltage swing. 4. Multiple lanes need to detect the EI condition before the device can act upon the EI detection. 5. Specified at the package pins into a timing and voltage compliance test setup. 6. Receiver designers may implement either single-ended or differential EI detection. Receivers must meet the specification that corresponds to the implemented detection circuit. 7. This specification, considered with VTX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered. 8. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse mask and the cumulative eye mask. 9. The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference in the Rx. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols. 10. This number does not include the effects of SSC or reference clock jitter. 11. This number includes setup and hold of the RX sampling flop. 12. Defined as the dual-dirac deterministic timing error. 13. Allows for 15mV DC offset between transmit and receive devices. 14. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-topeak common mode specification. For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-topeak common mode is the lesser of (200mV × 0.45 = 90mV) and VRX-CM-ACp-p. 15. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed. 16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin. 17. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver. This is one component of the end-to-end channel skew in the AMB specification. 18. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver. 19. This bandwidth number assumes the specified minimum data transition density. Maximum jitter at 0.2MHz is 0.05UI. 20. The specified time includes the time required to forward the EI entry condition. 21. BER per differential lane. Preliminary Data Sheet E1010E20 (Ver. 2.0) 17 EBE41FE4ABHT, EBE41FE4ABHL Serial PD Matrix for FB-DIMM Byte No. Function described Byte value Hex value 0 Number of serial PD bytes written / SPD device size / CRC coverage 116 92H 1 SPD revision Revision 1.1 11H 2 Key byte / DRAM device type DDR2 SDRAM FB-DIMM 09H 3 Voltage levels of this assembly VDD = 1.8V, VCC = 1.5V 12H 4 SDRAM addressing 14-row, 11-column, 8-bank 49H 5 Module physical attributes 8.2mm 24H 6 Module Type / Thickness FB-DIMM 07H 7 Module organization 2 ranks / 4bits 10H 8 Fine timebase (FTB) dividend / divisor 9 Medium timebase dividend 1 01H 10 Medium timebase divisor 4 04H 11 SDRAM minimum cycle time (tCK (min.)) 3.00ns 0CH 12 SDRAM maximum cycle time (tCK (max.)) 8ns 20H 13 SDRAM /CAS latencies supported CL = 3, 4, 5 33H 14 SDRAM minimum /CAS latencies time (tCAS) 15ns 3CH 15 SDRAM write recovery times supported WR = 2 to 5 42H 16 SDRAM write recovery time (tWR) 15ns 3CH 17 SDRAM write latencies supported WL = 2 to 5 42H 18 SDRAM additive latencies supported AL = 0 to 3 40H 19 SDRAM minimum /RAS to /CAS delay (tRCD) 15ns 3CH 20 SDRAM minimum row active to row active delay (tRRD) 7.5ns 1EH 21 SDRAM minimum row precharge time (tRP) 15ns 3CH 22 SDRAM upper nibbles for tRAS and tRC 00H 00H 23 SDRAM minimum active to precharge time (tRAS) 45ns B4H 24 SDRAM minimum auto-refresh to active /auto-refresh time (tRC) 60ns F0H 25 SDRAM minimum refresh recovery time delay (tRFC), LSB 127.5ns FEH 26 SDRAM minimum refresh recovery time delay (tRFC), MSB 127.5ns 01H 27 SDRAM Internal write to read command delay (tWTR) 7.5ns 1EH 28 SDRAM Internal read to precharge command delay (tRTP) 7.5ns 1EH 29 SDRAM burst lengths supported BL = 4, 8 03H 30 SDRAM terminations supported ODT = 50, 75, 150Ω 07H 31 SDRAM drivers supported Supported 01H 32 SDRAM average refresh interval (tREFI) / double refresh mode bit / high temperature self-refresh rate support indication 7.8µs Double/HT refresh C2H 33 Tcasemax (TC (max.)) delta / DT4R4W delta 95°C/ 0.00°C 51H ×× 34 Psi T-A SDRAM at still air * 3 35 SDRAM DT0 * 3 ×× SDRAM DT2Q * 3 ×× 37 SDRAM DT2P * 3 ×× 38 SDRAM DT3N * 3 ×× SDRAM DT4R / mode bit * 3 ×× 40 SDRAM DT5B * 3 ×× 41 SDRAM DT7 * 3 ×× 36 39 Preliminary Data Sheet E1010E20 (Ver. 2.0) 18 EBE41FE4ABHT, EBE41FE4ABHL Byte No. Function described Byte value Hex value 42 to 78 Reserved 79 FB-DIMM ODT values 80 Reserved 00H 81 to 93 AMB personality bytes ×× 94 to 97 Reserved 00H 98 AMB junction temperature maximum (TJ (max.)) ×× 99 Category byte 100 Reserved 00H 150/75Ω Stack/FDHS 12H 1AH 00H ×× 101 to 116 AMB personality bytes 117 Module ID: manufacturer’s JEDEC ID code Elpida Memory 02H 118 Module ID: manufacturer’s JEDEC ID code Elpida Memory FEH 119 Module ID: manufacturing location 120 Module ID: manufacturing date Year code (BCD) ×× 121 Module ID: manufacturing date Date code (BCD) ×× ×× 122 to 125 Module ID: module serial number ×× 126 to 127 Cyclical redundancy code ×× 128 to 145 Module part number EBE41FE4ABHT/L ×× 146 Module revision code Initial 30H 147 Module revision code (Space) 20H 148 SDRAM manufacturer’s JEDEC ID code Elpida Memory 02H 149 SDRAM manufacturer’s JEDEC ID code Elpida Memory FEH 150 Informal AMB content revision tag (MSB) 151 Informal AMB content revision tag (LSB) ×× ×× 152 to 175 Manufacturer's specific data 00H 176 to 255 Open for customer use 00H Remark IDD: DRAM current, ICC: AMB current Notes: 1. Based on DDR2 SDRAM component specification. 2. Refer to JESD51-3 “Low effective thermal conductivity Test board for leaded surface mount packages” under JESD51-2 standard. 3. DT parameter is derived as following: DTx = IDDx × VDD × Psi T-A, where IDDx definition is based on JEDEC DDR2 SDRAM component specification and at VDD=1.9V, it is the datasheet (worst case) value, and Psi T-A is the programmed value of Psi T-A (value in SPD Byte 33). Preliminary Data Sheet E1010E20 (Ver. 2.0) 19 EBE41FE4ABHT, EBE41FE4ABHL Physical Outline Unit: mm SDRAM location Upper Lower 8.20 max. Front side D19 D1 D20 D2 AMB D21 D3 D22 D4 5.20 max. D23 D5 D24 D6 3.00 max. D25 D7 3.90 . D18 D0 (DATUM -A-) 4.00 min. 74.675 Full DIMM heat spreader 1 120 R0.75 1.25 1.27 ± 0.10 A B 67.00 51.00 5.175 133.35 Back side D28 D10 D29 D11 D30 D12 D26 D8 D35 D17 D31 D13 D32 D14 D33 D15 D34 D16 3.00 D27 D9 30.35 240 17.30 121 9.50 120 FULL R 2.50 Detail B (DATUM -A-) 1.00 0.20 ± 0.15 2.50 ± 0.20 Detail A 2.50 3.80 0.40 min. 0.80 ± 0.05 FULL R 5.00 1.50 ± 0.10 Tie bar keep out zone ECA-TS2-0185-01 Preliminary Data Sheet E1010E20 (Ver. 2.0) 20 EBE41FE4ABHT, EBE41FE4ABHL CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E1010E20 (Ver. 2.0) 21 EBE41FE4ABHT, EBE41FE4ABHL The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 Preliminary Data Sheet E1010E20 (Ver. 2.0) 22