Fairchild NM27C210 1,048,576-bit (64k x 16) high performance cmos eprom Datasheet

NM27C210
1,048,576-Bit (64K x 16) High Performance
CMOS EPROM
General Description
Features
The NM27C210 is a high performance Electrically Programmable
UV erasable ROM (EPROM). It contains 1,048,576 bits configured as 64K x 16 bit. It is offered in both erasable versions for
prototyping and early production applications as well as nonerasable, plastic packaged versions that are ideal for high volume
and automated assembly applications.
■ High performance CMOS
— 90 ns access time
■ Fast turn-off for microprocessor compatibility
■ Simplified upgrade path
—VPP and PGM are “Don’t Care” during normal read
operation
The NM27C210 operates from a single 5 volt ±10% supply in the
read mode.
■ Compatible with 27210 and 27C210 EPROMs
■ Manufacturer’s identification code
The NM27C210 is offered in both DIP and surface mount packages. The DIP package is a 40-pin dual-in-line ceramic with a
quartz window to allow erasing. The surface mount package is a
44-pin PLCC that is offered in OTP.
■ Fast programming
■ JEDEC standard pin configuration
— 40-pin CDIP package
— 40-pin PDIP package
— 44-pin PLCC package
This EPROM is manufactured using Fairchild’s proprietary AMG™
EPROM technology for an excellent combination of speed and
economy while providing excellent reliability.
Block Diagram
Vcc
Data Outputs O0 - O15
GND
Vpp
OE
PGM
Output Enable
Chip Enable, and
Program Logic
Output
Buffers
CE
Y
Decoder
A0 - A15
Address
Inputs
4,194,304-Bit
Cell Matrix
X
Decoder
DS011093-1
AMG™ is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
1
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
July 1998
DIP PIN CONFIGURATIONS
DIP
NM27C210
27C280 27C240 27C220
A18
CE/PGM
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE/VPP
XXVPP
CE/PGM
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
XXVPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
XX/VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
27C220 27C240 27C280
VCC
PGM
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
XX/PGM
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
DS011093-7
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C210 pins.
Commercial Temperature Range
(0°C to +70°C) VCC = 5V ±10%
Pin Names
A0–A15
Addresses
Access Time (ns)
CE
Chip Enable
NM27C210 Q, V, N 90
90
OE
Output Enable
NM27C210 Q, V, N 120
120
O0–O15
Outputs
NM27C210 Q, V, N 150
150
PGM
Program
Parameter/Order Number
Industrial Temperature Range
(-40°C to +85°C) VCC = 5V ±10%
Access Time (ns)
NM27C210 QE, VE, NE 120
120
NM27C210 QE, VE, NE 150
150
Don’t Care (During Read)
NC
No Connect
PLCC Pin Configuration
O13
O14
O15
CE
XX/VPP
NC
VCC
XX/PGM
NC
A15
A14
Parameter/Order Number
XX
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
Package Types: NM27C210 Q, V, N XXX
Q = Quartz-Windowed Ceramic DIP package
N = Plastic DIP package
V = PLCC package
• All packages conform to JEDEC standard.
O3
O2
O1
O0
OE
NC
A1
A2
A2
A3
A4
• All versions are guaranteed to function in slower
applications.
39
7 6 5 4 3 2
4443424140
A13
1
A12
8
38
9
37
A11
10
36
A10
11
35
A9
12
34
GND
13
33
NC
14
32
A8
15
31
A7
16
30
A6
A5
181920212223242526 2728
29
17
Top View
2
DS011093-3
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Connection Diagrams
Storage Temperature
All Output Voltages with
Respect to Ground (Note 10)
-65°C to +150°C
VCC + 1.0V to GND - 0.6V
Operating Range
All Input Voltages except A9 with
Respect to Ground (Note 10)
-0.6V to +7V
VPP and A9 with Respect to Ground
Range
-0.6V to +14V
VCC Supply Voltage with
Respect to Ground
-0.6V to +7V
ESD Protection
VCC
Tolerance
Commercial
Temperature
0°C to +70°C
+5V
±10%
Industrial
-40°C to +85°C
+5V
±10%
>2000V
DC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
Test Conditions
Min
Max
Units
VIL
Input Low Level
-0.5
0.8
V
VIH
Input High Level
2.0
VCC +1
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage
IOH = -2.5 mA
ISB1
VCC Standby Current
(CMOS)
CE = VCC ± 0.3V
100
µA
ISB2
VCC Standby Current
CE = VIH
1
mA
ICC
VCC Active Current
CE = OE = VIL
I/O = 0 mA
40
mA
IPP
VPP Supply Current
VPP = VCC
10
µA
ILI
Input Load Current
VIN = 5.5 or GND
-1
1
µA
ILO
Output Leakage Current
VOUT = 5.5V or GND
-10
10
µA
IOL = 2.1 mA
3.5
V
f = 5 MHz
AC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
90
Min
Max
Min
120
Max
Min
150
Max
tACC
Address to Output Delay
90
120
150
tCE
CE to Output Delay
90
120
150
tOE
OE to Output Delay
50
50
50
tDF
(Note 2)
Output Disable to Output Float
30
35
45
tOH
(Note 2)
Output Hold from Addresses,
CE or OE , Whichever
Occurred First
0
0
Units
ns
0
Capacitance (Note 2) TA = +25°C, f = 1 MHz
Symbol
CIN
COUT
Parameter
Conditions
Typ
Max
Units
Input Capacitance
VIN = 0V
12
20
pF
Output Capacitance
VOUT = 0V
13
20
pF
3
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
≤5 ns
Input Rise and Fall Times
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs
Outputs
0.8V and 2V
0.8V and 2V
AC Waveforms (Note 6) , (Note 7) , (Note 9)
Adresses
2.0V
0.8V
CE
2.0V
0.8V
Addresses Valid
tCE
tCF
Notes 4, 5
OE
Output
2.0V
0.8V
2.0V
0.8V
tOE
tDF
Note 3
Notes 4, 5
High Z
High Z
tACC
tOH
DS011093-4
Note 3
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
4
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
AC Test Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
Address Setup Time
1
µs
tOES
OE Setup Time
1
µs
tCES
CE Setup Time
1
µs
tDS
Data Setup Time
1
µs
tVPS
VPP Setup Time
1
µs
tVCS
VCC Setup Time
1
µs
OE = VIH
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
1
µs
tDF
Output Enable to Output Float Delay
tPW
Program Pulse Width
tOE
Data Valid from OE
IPP
VPP Supply Current during
Programming Pulse
ICC
VCC Supply Current
TA
Temperature Ambient
20
VCC
Power Supply Voltage
6.25
6.5
6.75
V
VPP
Programming Supply Voltage
12.5
12.75
13.0
V
tFR
Input Rise, Fall Time
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
tIN
Input Timing Reference Voltage
0.8
2.0
V
Output Timing Reference Voltage
0.8
2.0
V
tOUT
CE = VIL
0
60
ns
105
µs
CE = VIL
100
ns
CE = VIL
PGM = VIL
40
mA
50
mA
30
°C
45
50
25
5
ns
0.0
0.45
4.0
V
V
Programming Waveforms (Note 13)
Program
Adresses
2.0V
0.8V
Program Verify
Address N
tAH
tAS
Data
Data In Stable
Add N
2.0V
0.8V
tDS
VCC
VPP
CE/PGM
Data Out Valid
Add N
tDF
tDH
6.25V
tVCS
12.75V
tVPS
2.0V
0.8V
tPW
OE
High Z
tOES
tOE
2.0V
0.8V
DS011093-5
Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: Programming and program verify are tested with the turbo Program Algorithm, at typical power supply voltages and timings.
Note 15: During power up the PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.
5
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Programming Characteristics (Note 11), (Note 12), (Note 13), (Note 14), and (Note 15)
NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION
PROGRAM ONE 50µs PULSE
INCREMENT n
NO
DEVICE
FAILED
YES
n = 10?
FAIL
VERIFY
BYTE
PASS
LAST
ADDRESS
?
NO
INCREMENT
ADDRESS
n=0
YES
ADDRESS = FIRST LOCATION
VERIFY
BYTE
FAIL
PASS
INCREMENT
ADDRESS
NO
PROGRAM ONE
50 µs
PULSE
LAST
ADDRESS
?
YES
CHECK ALL BYTES
1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.3V
DS011093-6
Note:
The standard National Semiconductor algorithm may also be used but it will have longer programming time.
FIGURE 1.
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The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 16 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and VPP. The VPP power
supply must be at 12.75V during the three programming modes,
and must be at 5V in the other three modes. The VCC power supply
must be at 6.5V during the three programming modes, and at 5V
in the other three modes.
When the address and data are stable, an active low, TTL program
pulse is applied to the PGM input. A program pulse must be
applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Figure 1. Each Address is programmed with a series of 50 µs
pulses until it verifies good, up to a maximum of 10 pulses. Most
memory cells will program with a single 50 µs pulse. (The standard
National Semiconductor Algorithm may also be used but it will
have longer programming time).
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for device selection.
Output Enable (OE) is the output control and should be used to
gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data is available
at the outputs tOE after the falling edge of OE, assuming that CE
has been low and addresses have been stable for at least tACC –
tOE.
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 200 mW to 0.5 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
the CE input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
Program Inhibit
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
VIL and VPP at 12.75V will program that EPROM. A TTL high level
CE input inhibits the other EPROM’s from being programmed.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with VPP at 12.75V. VPP must be at VCC, except during
programming and program verify.
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control
function allows for:
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
prevent temporary functional failure due to the generation of photo
currents.
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid in
programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
Programming
The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the
NM27C210 is “8FD6”, where “8F” designates that it is made by
Fairchild Semiconductor, and “D6” designates a 1 Megabit (64K
x 16) part.
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
The code is accessed by applying 12V ±0.5V to address pin A9 .
Addresses A1 –A8, A10 –A 15 , and all control pins are held at VIL.
Address pin A0 is held at VIL for the manufacturer’s code, and held
7
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Functional Description
Lamps lose intensity as they age. When a lamp is changed, the
distance has changed, or the lamp has aged, the system should
be checked to make certain full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
at VIH for the device code. The code is read on the lower eight data
pins, O0 –07 . Proper code access is only guaranteed at 25°C ±
5°C.
ERASURE CHARACTERISTICS
SYSTEM CONSIDERATION
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths
in the 3000Å – 4000Å range.
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated VCC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of
2537Å. The integrated dose (i.e., UV intensity x exposure time) for
erasure should be a minimum of 15W-sec/cm2 .
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
An erasure system should be calibrated periodically. The distance
from lamp to device should be maintained at one inch. The erasure
time increases as the square of the distance from the lamp (if
distance is doubled the erasure time increases by factor of 4).
MODE SELECTION
The modes of operation of the NM27C210 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are
TTL levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins
CE
OE
PGM
VPP
VCC
Outputs
Read
VIL
VIL
X
(Note 16)
X
5.0V
DOUT
Output Disable
X
VIH
X
X
5.0V
High Z
Standby
VIH
X
X
X
5.0V
High Z
Programming
VIL
VIH
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
VIH
12.75V
6.25V
DOUT
Program Inhibit
VIH
X
X
12.75V
6.25V
High Z
Mode
Note 16: X can be VIL or VIH.
TABLE 2. Manufacturer’s Identification Code
Pins
A0
(21)
A9
(31)
O7
(12)
O6
(13)
O5
(14)
O4
(15)
O3
(16)
O2
(17)
O1
(18)
O0
(19)
Hex
Data
Manufacturer Code
VIL
12V
1
0
0
0
1
1
1
1
8F
Device Code
VIH
12V
1
1
0
1
0
1
1
0
D6
8
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Functional Description (Continued)
2.080
(52.03)
MAX
40
21
0.530
(13.46)
Max Ceramic
0.025 RAD
(0.036)
0.550
(13.97)
Max Glass
0.030-0.055
(0.762-1.397)
RAD TYP
1
0.590-0.620
(14.985-15.748)
20
0.280±0.04
(7.112±0.102)
UV Window
Glass
Sealant
0.005 MIN
(0.127)
0.180
(4.572)
MAX
0.225
(5.715)
MAX
0.020-0.070
(0.508-1.778)
0.685
(
86°-94° TYP
0.08-0.012
(0.203-0.305)
95° ±5°
0.125-0.200 0.150
(3.175-5.080)
(3.810)
MIN
+0.025
-0.060
+0.635
17.40
-1.524
0.018±0.003
(.457±0.076)
TYP
0.055-0.005
(1.397±0.127)
TYP
(
0.100±0.010
(2.540±0.254)
TYP
0.090
(2.489)
MAX
(Both Ends)
40-Lead EPROM Ceramic Dual-In-Line Package (Q)
Order Number NM27C210QXXX
Package Number J40BQ
2.043-2.070
(51.89-52.58)
MAX
40
21
0.062 RAD
(1.575)
0.550 ±0.005
(13.970±0.127)
PIN No. 1 IDENT
1
0.580
(14.73)
MIN
20
0.030
(0.762)
MAX
0.600-0.620
(15.240-15.748)
0.050
(1.270)
TYP
0.125-0.165
(3.175-4.191)
0.225
(5.715)
95° ± 5°
0.009-0.015
(0.229-0.381)
0.625
(
86°-94°
TYP
+0.025
-0.015
+0.635
15.875
-0.381
(
0.075±0.015
(1.905±0.381)
0.100±0.010
(2.540±0.254)
0.018±0.003
(0.457±0.076)
0.020
(0.508)
MIN
0.125-0.140
(3.175-3.556)
40-Lead Molded Dual-In-Line Package (N)
Order Number NM27C210NXXX
Package Number N40A
9
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
+0.006
0.650 –0.000
+0.15
16.51 0
45°X 0.045
[1.14]
PIN 1 IDENT
6
1 44
17
0.017 ±0.021
TYP
[0.43 ±0.10]
0.045
45°X [1.14]
40
39
0.026–0.032
[0.66–0.81]
TYP
0.610 ±0.020
[15.49 ±0.51]
TYP
Seating
plane
17
29
18
0.500
TYP
[12.70]
28
0.050
TYP
[1.27]
0.020 MIN TYP
[0.51]
0.690 ± 0.005 TYP
[17.53 –0.13]
0.105 ±0.015 TYP
[2.67 ±0.38]
0.165–0.180 TYP
[4.19–4.57]
0.004 [0.10]
44-Lead Plastic Chip Carrier (V)
Order Number NM27C210VXXX
Package Number V44A
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Fax:
+44 (0) 1793-856858
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Tel: 81-3-3818-8840
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
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NM27C210 1,048,576-Bit (64K x 16) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
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