Hynix HY57V641620ESTP-H 64mb synchronous dram based on 1m x 4bank x16 i/o Datasheet

64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No.
History
Draft Date
Remark
First Version Release
1.0
1. Changed tOH: 2.0 --> 2.5
[tCK = 7 & 7.5 (CL3) Product]
Nov. 2004
1.1
1. Changed Input High/Low Voltage (Page 08)
2. Changed DC characteristics (Page 09)
- IDD2NS: 18mA -> 15mA
- IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA
[Speed 200 / 166 / 143 / 133MHz]
3. Changed Clock High / Low pulse width Time (Page 11)
4. Changed tAC Time (Page11)
5. Changed tRRD Time (Page12)
1.2
1. Corrected Revision No.: 2.0 -> 1.1
2. Deleted Remark at Revision History
3. Corrected AC OPERATING CONDITION
- CL 50pF -> 30pF
4. Changed DC OPERATING CONDITION
- VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0
- VIL MIN VSSQ-2.0 -> -0.3
1.3
1. Modified note for Super Low Power in ORDERING INFORMATION
Jan. 2005
1.4
1. Corrected PIN ASSIGNMENT A12 to NC
Jan. 2005
1.5
1. Corrected comments for overshoot and undershoot
Feb. 2005
Dec. 2004
Dec. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.5 / Feb. 2005
1
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of
1,048,576x16.
HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
•
Voltage: VDD, VDDQ 3.3V supply voltage
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 Refresh cycles / 64ms
•
54 Pin TSOPII (Lead or Lead Free Package)
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
•
Data mask function by UDQM, LDQM
•
Internal four banks operation
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency; 2, 3 Clocks
•
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V641620E(L/S)T(P)-5
200MHz
HY57V641620E(L/S)T(P)-6
166MHz
HY57V641620E(L/S)T(P)-7
143MHz
HY57V641620E(L/S)T(P)-H
133MHz
Organization
Interface
Package
4Banks x 1Mbits x16
LVTTL
54 Pin TSOPII
Note: 1. HY57V641620ET Series: Normal power, Leaded.
2. HY57V641620ELT Series: Low power, Leaded.
3. HY57V641620EST Series: Super Low power, Leaded.
4. HY57V641620ETP Series: Normal power, Lead Free.
5. HY57V641620ELTP Series: Low power, Lead Free.
6. HY57V641620ESTP Series: Super Low Power, Lead Free
Rev. 1.5 / Feb. 2005
2
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
PIN ASSIGNMENTS
VDD
1
54
VSS
DQ0
2
53
DQ15
VDDQ
3
52
VSSQ
DQ1
4
51
DQ14
DQ2
5
50
DQ13
VSSQ
6
49
VDDQ
DQ3
7
48
DQ12
DQ4
8
47
DQ11
VDDQ
9
46
VSSQ
DQ5
10
45
DQ10
DQ6
11
44
DQ9
VSSQ
12
43
VDDQ
DQ7
13
42
DQ8
VDD
14
41
VSS
LDQM
15
40
NC
/WE
16
39
UDQM
/CAS
17
38
CLK
/RAS
18
37
CKE
/CS
19
36
NC
BA0
20
35
A11
BA1
21
34
A9
A10/AP
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VDD
27
28
VSS
Rev. 1.5 / Feb. 2005
54 Pin TSOPII
400mil x 875mil
0.8mm pin pitch
3
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
PIN DESCRIPTION
SYMBOL
TYPE
CLK
Clock
CKE
Clock Enable
CS
Chip Select
BA0, BA1
Bank Address
A0 ~ A11
Address
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write
mode
DQ0 ~ DQ15
Data Input / Output
VDD / VSS
Power Supply / Ground
VDDQ / VSSQ
Data Output Power /
Ground
NC
No Connection
Rev. 1.5 / Feb. 2005
DESCRIPTION
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
4
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Internal Row
Counter
Self refresh
logic & timer
1Mx16 BANK 3
CLK
CAS
Column Active
U/LDQM
A0
Address Buffers
BA1
DQ0
DQ15
Y-Decoder
Column Add
Counter
Bank Select
A11
Memory
Cell
Array
Column
Pre
Decoder
WE
A1
1Mx16 BANK 0
I/O Buffer & Logic
Refresh
1Mx16 BANK 1
Sense AMP & I/O Gate
State Machine
RAS
1Mx16 BANK 2
X-Decoder
X-Decoder
X-Decoder
X-Decoder
CKE
CS
Row
Pre
Decoder
Row Active
Address
Register
Mode Register
Burst
Counter
CAS Latency
Data Out Control
Pipe Line
Control
BA0
Rev. 1.5 / Feb. 2005
5
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1
BA0
A11
A10
A9
A8
A7
0
0
0
0
OP Code
0
0
A6
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
OP Code
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
CAS Latency
Burst Type
A3
Burst Type
0
Sequential
1
Interleave
Burst Length
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
0
1
0
1
1
0
1
0
Burst Length
A2
A1
A0
A3 = 0
A3=1
1
0
0
0
1
1
0
2
0
0
1
2
2
1
3
0
1
0
4
4
0
Reserved
0
1
1
8
8
1
Reserved
1
0
0
Reserved
Reserved
1
1
0
Reserved
1
0
1
Reserved
Reserved
1
1
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Rev. 1.5 / Feb. 2005
6
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
ABSOLUTE MAXIMUM RATING
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
oC
Storage Temperature
TSTG
-55 ~ 125
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
TSOLDER
260 / 10
Soldering Temperature / Time
o
oC
C
/ Sec
DC OPERATING CONDITION (TA= 0 to 70oC)
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD, VDDQ
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
3.0
V
1, 2
Input Low Voltage
VIL
-0.3
-
V
1, 3
Power Supply Voltage
VDDQ + 0.3
0.8
Note: 1. All voltages are referenced to VSS = 0V
2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
VIH / VIL
2.4 / 0.4
V
Vtrip
1.4
V
Input Rise/Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
CL
30
pF
AC Input High/Low Level Voltage
Input Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Note: 1.
Vtt=1.4V
RT=50 Ω
Output
Z0 = 50Ω
30pF
DC Output Load Circuit
Rev. 1.5 / Feb. 2005
1
Vtt=1.4V
RT=500 Ω
Output
Note
30pF
AC Output Load Circuit
7
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=3.3V)
Parameter
Input capacitance
Data input / output capacitance
Pin
Symbol
Min
Max
Unit
CLK
CI1
2.0
4.0
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE,
LDQM, UDQM
CI2
2.5
5.0
pF
DQ0 ~ DQ15
CI/O
3.0
5.5
pF
DC CHARACTERRISTICS I (TA= 0 to 70oC)
Parameter
Symbol
Min
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 3.6
Rev. 1.5 / Feb. 2005
8
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter
Operating Current
Symbol
IDD1
Speed
Test Condition
5
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
6
7
H
Unit Note
120 110 100 100
mA
CKE ≤ VIL(max), tCK = 15ns
2
mA
CKE ≤ VIL(max), tCK = ∞
2
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
18
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
15
IDD3P
CKE ≤ VIL(max), tCK = 15ns
3
IDD3PS
CKE ≤ VIL(max), tCK = ∞
3
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
40
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
35
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
120 110 100 100
mA
1
Auto Refresh Current
IDD5
tRC ≥ tRC(min), All banks active
170 160 150 150
mA
2
Normal
1
mA
Low power
400
uA
Super Low
power
300
uA
Precharge Standby Cur- IDD2P
rent
IDD2PS
in Power Down Mode
Precharge Standby Cur- IDD2N
rent
in Non Power Down
Mode
IDD2NS
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down
Mode
1
mA
mA
mA
3
Self Refresh Current
IDD6
CKE ≤ 0.2V
3, 4
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V641620ET(P) Series: Normal Power
HY57V641620ELT(P) Series: Low Power
HY57V641620EST(P) Series: Super Low Power
Rev. 1.5 / Feb. 2005
9
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
5
Min
6
Max
Min
Max
Min
Max
Min
Unit
Note
5.0
CL = 2
tCK2
10
Clock High Pulse Width
tCHW
1.75
-
2.0
-
2.0
-
2.5
-
ns
1
Clock Low Pulse Width
tCLW
1.75
-
2.0
-
2.0
-
2.5
-
ns
1
CL = 3
tAC3
-
4.5
-
5.4
-
5.4
-
5.4
ns
CL = 2
tAC2
-
6.0
-
6.0
-
6.0
-
6.0
ns
Data-out Hold Time
tOH
2.0
-
2.0
-
2.5
-
2.5
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
1.0
-
1.0
-
1.5
-
1.5
-
ns
Access Time From Clock
CLK to Data Output in Low-Z Time tOLZ
CLK to Data Output
in High-Z Time
10
1000
10
1000
7.5
Max
tCK3
1000
7.0
H
CL = 3
System Clock
Cycle Time
6.0
7
10
1000
ns
ns
CL = 3
tOHZ3
-
4.5
-
5.4
-
5.4
-
5.4
ns
CL = 2
tOHZ2
-
6.0
-
6.0
-
6.0
-
6.0
ns
2
Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev. 1.5 / Feb. 2005
10
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Symbol
5
6
7
H
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
55
-
60
-
63
-
63
-
ns
RAS Cycle Time
Operation
RAS Cycle Time
Auto Refresh tRRC
55
-
60
-
63
-
63
-
ns
RAS to CAS Delay
tRCD
15
-
18
-
20
-
20
-
ns
RAS Active Time
tRAS
38.7
100K
42
100K
42
100K
42
120K
ns
RAS Precharge Time
tRP
15
-
18
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
10
-
12
-
14
-
15
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
CLK
Write Command to Data-In DetWTL
lay
0
-
0
-
0
-
0
-
CLK
Data-in to Precharge Command tDPL
2
-
2
-
2
-
2
-
CLK
tRC
Data-In to Active Command
tDAL
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
2
-
CLK
Precharge to Data CL = 3
Output High-Z
CL = 2
tPROZ3
3
-
3
-
3
-
3
-
CLK
tPROZ2
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tDPE
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
-
64
ms
tDPL + tRP
1
Note: 1. A new command can be given tRRC after self refresh exit.
Rev. 1.5 / Feb. 2005
11
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
L
H
H
H
X
X
Bank Active
H
X
L
L
H
H
X
RA
Read
Read with
charge
BA
Autopre-
H
X
L
H
L
H
X
CA
V
H
V
L
Autopre-
H
X
L
H
L
L
X
CA
Precharge All Banks
V
H
X
L
V
X
L
L
H
L
X
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-Read-SingleWRITE
H
X
L
L
L
L
X
A9 ball High
(Other balls OP code)
Entry
H
L
L
L
L
H
X
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Self Refresh1
selected
X
Precharge
power down
Clock
Suspend
Exit
L
H
Entry
H
L
Exit
L
H
Rev. 1.5 / Feb. 2005
X
X
X
H
H
Precharge
Bank
Note
L
Write
Write with
charge
A10/AP
MRS
Mode
X
X
X
X
X
X
X
12
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
0.80(0.0315)BSC
Rev. 1.5 / Feb. 2005
0.400(0.016)
0.300(0.012)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
13
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