ETC BIT3193 High performance pwm controller Datasheet

BIT3193
Beyond Innovation Technology Co., Ltd.
BIT3193
High Performance PWM Controller
Preliminary
Version: 0.03
Notice
All information contained in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without
the prior written consent of Beyond Innovation Technology Co., Ltd.
04/11/08
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BIT3193
Beyond Innovation Technology Co., Ltd.
Features:
Pin Layout:
4.5V ~ 8V operation
Fixed High Frequency, Voltage Mode PWM Control
Topology
Latched Off Protection
Build-In Low Frequency PWM Generator
Build-In UVLO
Low Power CMOS Process
Totem Pole Output
16 Pin Package
Applications:
DC/DC Converters
LCD TV
LCD Monitor
Notebook Computer
Tablet PC
Personal Digital Assistants
Navigation Devices (GPS Equipment)
Video Phone/ Door Phone
Portable consumer product
INN
CMP
LOAD
CTOSC
TIMER
ONOFF
GND
NOUT2
1
16
8
9
MODSEL
ISEN
CLAMP
PWMDC
CTPWM
PWMOUT
VDD
NOUT1
General Description:
BIT3193 integrated circuit provides the essential
features for general purpose PWM controller in a small low
cost 16-pin package. BIT3193 has built-in a low frequency
PWM generator for any specified application. BIT3193
includes latched off protection feature may make the system
more reliable while compare to other similar products.
Recommended Operating Condition:
Supply Voltage…………………………….4.5 ~ 8V
Operating Ambient Temperature………...0 ~ 70 ℃
Operating Frequency………………….….50K ~ 400K Hz
Functional Block Diagram:
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BIT3193
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Pin Description:
04/11/08
Pin No.
1
2
Symbol
INN
CMP
3
LOAD
4
CTOSC
5
TIMER
6
ONOFF
7
8
9
10
GND
NOUT2
NOUT1
VDD
11
PWMOUT
12
CTPWM
13
PWMDC
14
CLAMP
15
ISEN
16
MODSEL
I/O
Descriptions
I The inverting input of the error amplifier.
O Output of the error amplifier.
A switch that connected to the high frequency triangle wave generator.
I/O This switch is open while ISEN pin <1.3V. An external resistor connected
here may change the operation frequency of CTOSC in open load situation.
An external capacitor connected here can set the frequency of high frequency
I/O
PWM controller.
With internal reference current and an external capacitor connected here can
set the required period of starting and the timing of initialization. The
controller is forced to reset mode while TIMER <0.3V. During reset mode, a ~
60uA current will flow into the INN pin to reduce the output level of the error
I/O amplifier CMP to turn off the controller. The latched off protection function will
be enabled after this node is charged to > 2.5V. System is latched off if any
abnormal operation is detected if pin TIMER > 2.5V.
The output current of this pin is 20uA when TIMER < 0.3V.
The output current becomes to 1uA when TIMER > 0.3V
The control pin of turning on or off the IC. 1V threshold with an internal 80K±
I
15% ohm pull-low resistor.
I/O The ground pin of the device.
O The number 2 output driver for driving the NMOSFET switch.
O The number 1 output driver for driving the NMOSFET switch.
I The power supplies pin of the device.
The output pin of low frequency PWM generator. A 2.5V or floating two state
O output is provided through this pin.
The internal circuit limits the max. Duty-cycle to ~ 92%.
With the internal reference current and an external capacitor connected here
I/O can set the operation frequency of low frequency PWM generator with 1.0V ~
2.5V triangle wave output.
Low frequency PWM controlling input. A PWM output comes out by
I comparing this DC input and the 1.0 ~ 2.5V triangle wave that is generated
by CTPWM.
Over voltage clamping. If a > 2.0 V voltage is detected. A ~ 60uA current will
I flow into the INN pin to reduce the output of the error amplifier pin CMP to
regulate the output voltage.
Load current detection pin, the open load situation is detected if a less than
I
1.3V input is sensed.
O To set the output polarity of the low frequency PWM controller.
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BIT3193
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Functional Description:
An internal trimmed
band-gap reference provides a high accuracy, supply
and temperature insensitive voltage reference. By
amplifying or dividing this voltage can generate the other
required references.
Trimmed Band Gap References:
To Set the Operation Frequency of High
Frequency PWM Controller: An external capacitor
CCTOSC pin CTOSC determines the frequency as
equation (1)
The frequency of the high frequency PWM controller is:
FHFPWM =
K HF
, K HF = 8.2e - 5 ............(1)
C CTOSC
or a 100KHz operation PWM control system if an 820pF
capacitor is connected to pin CTOSC. Equation (1) is
valid only when VDD=6V, temperature=30ºC and
frequency ≈ 80K ~ 120KHz.
Fig. 5 shows the
relationship between the frequency of the high frequency
PWM and CTOSC capacitance.
Table 2 BIT3193 initial state
Pin Number Pin Name Status
Force to VDD
1
INN
( With ~ 60uA current source)
4
CTOSC
Normally run
8
NOUT1
Forced to GND level
9
NOUT2
Forced to GND level
11
PWMOUT Floating
12
CTPWM
Normally run
The ISEN pin may be
used to detect if the operation is under well control during
normal operation. In most of the applications to define a
“ staring period”, in which period no signal feed back from
the load side, is necessary. BIT3193 disable the latched
off function when TIMER < 2.5V. If TIMER >2.5V and
ISEN < 1.3V for 32 cycles of low frequency PWM.
BIT3193 will shut the output pins NOUT1 and NOUT2
down until the system is powered on again.
The Latched Off Protection_1:
The CLAMP pin may
be used to detect if the PWM control system operates
normally too. A ~ 60uA current source will charge the INN
pin to reduce the output of CMP while CLAMP > 2.0V.
The latched off over voltage protection performs while
TIMER > 2.5V. If TIMER > 2.5V and CLAMP >2.0 V for
14 cycles of high frequency PWM. BIT3193 will shut the
output pins NOUT1 and NOUT2 down until the system is
powered on again.
The Latched Off Protection_2:
CTOSC VS. Frequency
250.00
Frequency(KHz)
200.00
150.00
100.00
To Set The Frequency Deviation of High Frequency
PWM During Different Loading Condition: The
50.00
LOAD pin may be used to change the frequency of
CTOSC when ISEN < 1.3V. In many cases, the resonance
frequency of the load is varied while the load is changed.
For obtaining the better performance, the operation
frequency of the PWM controller must fit to the resonance
frequency of the load. A connect to GND resistor may
increase the operation frequency of CTOSC.
The
following diagram shows how the load resistance changes
the 100KHz operation frequency of CTOSC pin. In
above case, CTOSC is connected by an 820pF capacitor.
The normal operation frequency of high frequency PWM is
100KHz. If a different frequency says Fn is the set for
normal operation.
0.00
300
500
700
900
1100
1300
1500
Fig.5
CTOSC(pF)
An internal current
source charges the external capacitor connected on
TIMER pin determines the initialization timing of BIT3193.
This current provides ~ 20uA when TIMER pin less than
0.3V, and ~ 1uA when TIMER pin > 0.3V. BIT3193 is in
an “initial state” when TIMER < 0.3V. Table 2 lists the
status of each key features during TIMER < 0.3V.
The Power On Initialization:
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BIT3193
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Setting the Frequency of Low Frequency PWM
Generator:
An internal trimmed low frequency
LOAD Resistor VS. CTOSC Frequency Deviation
oscillator generates a ± 3% accurate frequency on
CTPWM pin with external capacitors. The capacitor
values versus operation frequencies are as bellow:
200.00
CTOSC Frequency Deviation (KHz)
175.00
173.30
CTOSC=100KHz
FLFPWM =
151.10
150.00
126.50
125.00
108.70
100.00
Note: Above equation (3) is valid only when operating
frequency is between 150Hz ~ 1.5KHz
91.40
76.20
63.50
54.40
45.70
38.70
75.00
50.00
25.00
32.10
26.80
0.00
0
20
4512
.............(3)
[C CTPWM + 0.005]nF
40
60
80
LOAD Resisor (Kohm)
Fig.6
Then the frequency deviation can be calculated as
Equation (2)
∆F100 KHz × Fn
∆Fn =
.......... ...(2)
100KHz
100
The logic high output of pin PWMOUT is made by an 2.5V
DC voltage and the floating state makes the logic low
portion. MODSEL pin provides the polarity selection of
LF_PWM generator. If MODSEL pin is 0V, a 0% duty cycle
is obtained when PWMDC < 1.0V. If this pin is pulled to
IC VDD level, 0% duty cycle is obtained while PWMDC>
2.5V.
Note: BIT3193 limits the maximum duty cycle to ~ 92 %.
PWMOUT sends the pulses when ISEN >1.3V or TIMER
>2.5V.
UVLO: The under-voltage-lookout circuit turns the output
driver off when supply voltage drops too low. Whole
system includes the protection and timing circuits are reset
(pin TIMER =0) in low VDD state.
DC/AC Characteristics:
Absolute Ratings:
Table 3
Parameter
Supply Voltage
Ground
Input pin Voltage
Operating Ambit Temperature
Operating Junction Temperature
Storage Temperature
Symbol Ratings
VDD
-0.3~+ 9
GND
±0.3
-0.3~ VDD+0.3
Ta
0~ +70
+150
-55~+150
Unit
V
V
V
°C
°C
°C
Remarks
Ta=25°C
DC/AC Characteristics
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BIT3193
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Table 4
Parameter
Test Conditions
Supply Voltages
Pin VDD input
Typ.
4.0
8V Supply Voltage
Chip Consumed Current
Ta=25°C
Error Amplifier Reference Voltage
Non-Inverting input of the error
Measure INN
amplifier
Line regulation
VDD=4.0~13.2 V
Under Voltage Look Out
Max.
Unit
8
V
4
1.2875
V
2
20
mV
3.8
4.0
4.2
V
Hysteresis
0.1
High Frequency Ramp Wave Generator
Operating Frequency
50
Note1
Output peak(CTOSC)
Output valley(CTOSC)
Error Amplifier
Input voltage
0.1
Note2
Open loop gain
60
Unit gain band width
1
Power On Initialization and Latched Off Protection Enable
Pin TIMER Output current
Case1. TIMER <0.3V
Pin TIMER Output current
Case1. TIMER > 0.3V
VDD=12V, Ta=25°C
Power
On
Reset/Initialization Note 3
threshold on pin TIMER
Latched Off Protection enable
threshold on pin TIMER
Open Load Detection
Pin ISEN open load detection
VDD=12V, Ta=25°C
lower threshold
Hysterisis
Over Voltage Detection and Clamping
Pin CLAMP over voltage detection
lower threshold
VDD=12V, Ta=25°C
Hysterisis
INN pin pull-up current source
Low Frequency PWM Generator
Ramp Wave Peak(CTPWM)
Ramp Wave Valley(CTPWM)
PWM Frequency
10
Control voltage of 0 % Duty cycle
on pin PWMDC
Case 1. MODSEL = 0V
Control voltage of 0 % Duty cycle VDD=12V, Ta=25°C
on pin PWMDC
Case 1. MODSEL = ICVDD
Output voltage of Pin PWMOUT
for making the logic “high”.
Pin PWMOUT output for making
the logic “low”
Maximum Duty Cycle
Output
CMOS output impedance
(Note2, Note3)
Rising Time
VDD=12V,
2000pF(Note2,
Falling Time
Note3)
Delay Time
0.2
0.3
V
400
KHz
V
V
3
80
1.5
V
dB
MHz
20
uA
1
uA
0.3
V
2.5
V
1.3
V
20
mV
2.0
V
20
60
mV
uA
2.5
1.0
V
V
Hz
Ta=25°C
Note3
1.2125
mA
1.25
Positive Going Threshold
04/11/08
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2.25
0.5
100K
1.0
V
2.5
V
2.5
V
Floating
92
%
50
110
ohm
nS
100
nS
200
nS
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BIT3193
Beyond Innovation Technology Co., Ltd.
Note 1. The output driver frequency is the half of the ramp wave frequency.
Note 2. Only verified by simulation. Not 100% tested.
Note 3. The voltages of the output drivers are pulled to GND in each off states.
Timing Diagram
BIT3193 fixed frequency push pull driving methodology to drive the load. The power switches;
NMOSFETs are driven by fixed frequency PWM controlled signals. The detail timing relationship is shown as
bellow: The maximum duty cycle of NOUT1 and NOUT2 are < 50% with 180° phase shift.
Fig. 3
The timing of another low frequency PWM generator is as bellow: A 51Kohm pulled-low resistor is
connected on PWMOUT pin in this example.
CTPWM
PWMDC
1.3V(2.5V)
ISEN(TIMER)
PWMOUT ( MODE = " 0" )
PWMOUT ( MODE = " 1" )
Fig. 4
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BIT3193
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Order Information:
BIT3193-SO
SO: SOP
SS: SSOP
DP: DIP
Part number
Beyond Innovation Technology Co., Ltd.
Package Information :
SOP type :
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BIT3193
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SSOP type :
DIP type :
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BIT3193
Beyond Innovation Technology Co., Ltd.
Copyright © 2004 Beyond Innovation Technology Co., Ltd
All rights are reserved. Reproduction in whole or in parts is prohibited without the prior written
consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Life Support Applications
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in person injury. BiTEK customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify BiTEK for any damages resulting from
such improper use or sale.
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