NTGS4141N, NVGS4141N Power MOSFET 30 V, 7.0 A, Single N−Channel, TSOP−6 Features • Low RDS(on) • Low Gate Charge • NV Prefix for Automotive and Other Applications Requiring Unique • Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 21.5 mW @ 10 V Applications 30 V • Load Switch • Notebook PC • Desktop PC 7.0 A 30 mW @ 4.5 V N−Channel Drain 1 2 5 6 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±20 V ID 5.0 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C 3.6 t ≤ 10 s TA = 25°C 7.0 Steady State TA = 25°C PD t ≤ 10 s Continuous Drain Current (Note 2) Steady State Power Dissipation (Note 2) Gate 3 Source 4 1.0 W 2.0 TA = 25°C ID TA = 85°C 3.5 A 1 2.5 TA = 25°C PD 0.5 W Pulsed Drain Current tp = 10 ms, VGS=10V IDM 45 A Pulsed Drain Current tp = 30 ms, VGS=5V Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (VDD = 30 V, IL = 10.4 A, VGS = 10 V, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) ID 30 A TJ, TSTG −55 to 150 °C IS 2.0 A EAS 54 mJ TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE RATINGS Rating Symbol Max Unit Junction−to−Ambient – Steady State (Note 1) RθJA 125 °C/W Junction−to−Ambient – t ≤ 10 s (Note 1) RθJA 62.5 Junction−to−Ambient – Steady State (Note 2) RθJA 248 TSOP−6 CASE 318G STYLE 1 MARKING DIAGRAM XX MG G XX = Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT Drain Drain Source 6 5 4 1 2 3 Drain Drain Gate ORDERING INFORMATION See detailed ordering and shipping information ion page 5 of this data sheet. 1. Surface−mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0773 in sq). © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 6 1 Publication Order Number: NTGS4141N/D NTGS4141N, NVGS4141N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 18.4 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) gFS 1.0 3.0 5.7 V mV/°C VGS = 10 V, ID = 7.0 A 21.5 25 mW VGS = 4.5 V, ID = 6.0 A 30 35 VDS = 10 V, ID = 7.0 A 30 S 560 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 0 V, f = 1.0 MHz, VDS = 24 V Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge 115 75 nC 12 VGS = 10 V, VDS = 15 V, ID = 7.0 A 0.85 1.9 QGD 3.0 Total Gate Charge QG(TOT) 6.0 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 3.0 RG 2.8 W td(ON) 6.0 ns Gate Resistance VGS = 4.5 V, VDS = 15 V, ID = 7.0 A nC 0.8 1.85 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 10 V, VDS = 24 V, ID = 7.0 A, RG = 3.0 W tf 15 18 4.0 DRAIN − SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 2.0 A TJ = 25°C 0.78 TJ = 125°C 0.63 15 VGS = 0 V dIS/dt = 100 A/ms, IS = 2.0 A QRR 1.0 V ns 9.0 6.0 8.0 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTGS4141N, NVGS4141N TYPICAL PERFORMANCE CURVES 10 V 6V 15 TJ = 25°C VDS ≥ 10 V 3.5 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 15 4.5 V 10 3V 5 2.6 V 0 2 0 4 6 5 125°C 25°C TJ = −55°C 0 10 8 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.05 TJ = 25°C ID = 7 A 0.04 0.03 0.02 0.01 2 0 4 6 8 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.05 0.03 VGS = 4.5 V 0.02 0.01 0 0 0.5 0 25 50 75 100 125 10 5 15 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current and Gate Voltage IDSS, LEAKAGE CURRENT (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.0 −25 VGS = 10 V 10000 ID = 7 A VGS = 10 V 1.5 0 −50 TJ = 25°C 0.04 Figure 3. On−Resistance vs. Gate−to−Source Voltage 2.0 5 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 150 VGS = 0 V 1000 TJ = 150°C 100 TJ = 125°C 10 TJ, JUNCTION TEMPERATURE (°C) 15 25 20 5 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage 0 http://onsemi.com 3 30 NTGS4141N, NVGS4141N 1200 VDS = 0 V C, CAPACITANCE (pF) 1000 VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CURVES TJ = 25°C VGS = 0 V Ciss 800 Ciss 600 400 Crss 200 Coss 0 10 Crss 5 0 VGS 5 10 15 20 25 10 QT 8 VGS 6 4 QGS ID = 7 A VDD = 15 V TJ = 25°C 2 0 2 0 VDS Figure 7. Capacitance Variation 1000 IS, SOURCE CURRENT (AMPS) t, TIME (ns) td(off) 100 tf tr 10 td(on) 1 10 RG, GATE RESISTANCE (OHMS) 5 4 3 2 1 0 100 VGS = 0 V TJ = 25°C 6 100 ms 1 ms 0.01 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 ms dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (AMPS) 10 ms 0 V ≤ VGS ≤ 20 V SINGLE PULSE TC = 25°C 0.9 Figure 10. Diode Forward Voltage vs. Current 100 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 0.1 12 7 VDD = 24 V ID = 7 A VGS = 10 V 1 4 6 8 10 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 QGD 60 ID = 10.4 A 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 125 100 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 150 NTGS4141N, NVGS4141N TYPICAL PERFORMANCE CURVES References is TJmax = 150°C 2.25 2.0 PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 2.5 1.75 1.5 RqJA, t < 10 s, 1 sq in RqJA, 1 sq in 1.25 1.0 0.75 0.5 RqJA, min pad 0.25 0 Rthja(t), TRANSIENT THERMAL RESPONSE (°C/W) 0 20 40 60 80 100 120 140 160 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 References is TJmax = 150°C RqJA, t < 10 s, 1 sq in RqJA, 1 sq in RqJA, min pad 0 20 40 60 80 100 120 140 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 13. Maximum Power Derating Chart Figure 14. Current Derating Chart 160 1000 100 D = 0.5 0.2 0.1 10 0.05 0.02 1 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, PULSE TIME (s) Figure 15. Thermal Response Table 1. ORDERING INFORMATION Marking (XX) Package Shipping† NTGS4141NT1 S4 TSOP−6 3000 / Tape & Reel NTGS4141NT1G S4 TSOP−6 (Pb−Free) 3000 / Tape & Reel NVGS4141NT1G VS4 TSOP−6 (Pb−Free) 3000 / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTGS4141N, NVGS4141N PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b DETAIL Z e 0.05 M C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. SEATING PLANE DIM A A1 b c D E E1 e L L2 M c A A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 6X 3.20 0.95 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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