MPS MP6402DQT-EF-LF-Z Dual, high psrr 500ma linear regulator with integrated reset circuit Datasheet

MP6402
Dual, High PSRR 500mA Linear Regulator
With Integrated Reset Circuit
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP6402 is a dual-channel, high PSRR
linear regulator with reset function.
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The outputs range from 0.9V and 3.3V with
±1.5% voltage accuracy at both channels by
operating from a +2.5V to +5.5V input. OUT2
pin voltage is recommended to be higher than
OUT1 pin voltage. Short circuit protection and
thermal protection are built in to prevent
damage caused by output short circuit and
overloading, respectively.
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A reset circuit is designed to monitor output
voltage of channel 2. The
becomes
active (low) when OUT2 pin voltage drops
below its threshold. To ensure that a complete
reset occurs, the
remains active for a
pre-set delay time. The delay time is
programmable by the user through changing
the external capacitor. The MP6402 is available
in SOIC8E and 3x3mm TQFN8 packages and
is specified for operation TJ from -40°C to
+125°C.
Up to 500mA Output Current
High Output Voltage Accuracy (±1.5％)
High Reset Voltage Accuracy (±3％)
Programmable Reset Delay Time
High PSRR: 60dB at 100Hz
15µVRMS Low Noise Outputs
Built-in Short Circuit Protection
Built-in Thermal Protection
Output Discharge
SOIC8E and 3x3mm TQFN8
APPLICATIONS
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Consumer electronics
Blu-ray
Portable GPS Devices
Wireless Devices
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
IN
5V
OUT1
VOUT1
OUT2
VOUT2
MP6402
IN
R1
22.1k
RESET
C4
3300pF
MP6402 Rev.1.0
4/8/2011
RESET
EN
ExtCap
GND
EN
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1
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
ORDERING INFORMATION
Part Number
MP6402DN-EF-LF-Z*
MP6402DQT-EF-LF-Z**
Package
SOIC8E
TQFN8 (3x3mm)
Top Marking
6402DNEF
9X
Junction Air Temperature (TJ)
-40°C to +125°C
-40°C to +125°C
* For Tape & Reel, add suffix –Z (e.g. MP6402DN–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP6402DN–LF–Z).
** For Tape & Reel, add suffix –Z (e.g. MP6402DQT–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP6402DQT–LF–Z).
ORDERING GUIDE***
MP6402DQT
DN _ _ - LFZ
Output Voltage 2 (Table 1)
Output Voltage 1 (Table 1)
Package
Temperature
Table 1 — Output Voltage Selector Guide
Code
A
B
C
D
E
F
G
H
VOUT1
0.9
1.05
1.2
1.3
1.8
2.5
2.8
--
VOUT2
---1.3
1.8
2.5
2.8
3.3
*** Code in Bold are standard versions. For other output voltage
between 0.9V to 3.3V contact factory for availability.
Minimum order quantity on no-standard version in 25,000 units.
MP6402 Rev.1.0
4/8/2011
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2
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
IN
1
8
OUT1
IN 1
8 OUT1
IN
2
7
OUT2
IN 2
7 OUT2
EN
3
6
RESET
EN 3
6 RESET
GND
4
5
ExtCap
GND 4
5 ExtCap
SOIC8E
TQFN8 (3mm x 3mm)
Thermal Resistance
IN ...................................................... -0.3V to 6V
............................................. -0.3V to 6V
All Other Pins ..................................-0.3V to +6V
(2)
Continuous Power Dissipation. (TA = +25°C)
SOIC8E ...................................................... 2.2W
TQFN8 (3mm x 3mm) ................................ 2.6W
Storage Temperature Range ..... -55°C to 150°C
Junction Temperature ...............................150°C
Lead Temperature (Soldering, 10sec) ......260°C
SOIC8E ................................... 55 ...... 12 ... °C/W
TQFN8 (3mm x 3mm) ............ 48 ...... 11 ... °C/W
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ABSOLUTE MAXIMUM RATINGS (1)
Recommended Operating Conditions
(3)
Input Voltage VIN ............................. 2.5V to 5.5V
Operating Junct. Temp (TJ)...... -40°C to +125°C
MP6402 Rev.1.0
4/8/2011
(4)
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of
the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient
temperature TA. The maximum allowable continuous power
dissipation at any ambient temperature is calculated by PD
(MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum
allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal
shutdown. Internal thermal shutdown circuitry protects the
device from permanent damage. Thermal shutdown
o
and
disengages
at
engages
at
TJ=150 C(TYP)
o
TJ=130 C(TYP)
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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3
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
ELECTRICAL CHARACTERISTICS
VIN= VOUT2+0.5V or 2.5V for each LDO. Typical Value at TA = +25°C unless otherwise noted.
Parameter
Symbol
Quiescent Current (ON)
Iq
Quiescent Current (OFF)
IqEBL
Output Voltage Range
Dropout Voltage
VOUT
VDROP
Output Voltage Accuracy
Output Current Limit
Short Circuit Current
ILIM
IST
△VOUT1
Load Regulation
△VOUT2
△VLINE1
Line Regulation
△VLINE2
PSRR
VOUT1=1.8V
PSR
VOUT2=2.5V
PSR2
Output Voltage Noise
Condition
Min
Typ
Max
Unit
EN activate without load
0.4
0.58
mA
EN deactivate
17
36
µA
3.3
0.9
IOUT=500mA
IOUT=10mA
IOUT=10mA, TA=-40°C to
85°C
-1.5
1.5
V
mV
%
-2.3
2.3
%
260
550
OUT short to GND
VIN=(VOUT1+0.5V or 2.5V),
IOUT1=1mA to 500mA
VIN=(VOUT2+0.5V or 2.5V),
IOUT2=1mA to 500mA
VIN=(VOUT1+0.5V or 2.5V) to
5.5V, IOUT1=10mA
VIN=(VOUT2+0.5V or 2.5V) to
5.5V, IOUT2=10mA
f=100Hz, IOUT1=100mA
mA
mA
200
f=100Hz, IOUT2=100mA
100Hz
to
80kHz,
COUT=3.3µF, IOUT=10mA
45
mV
50
mV
0.05
0.1
%/V
0.05
0.1
%/V
60
dB
51
dB
15
µVRMS
RESET OUT
Reset Delay Time
RSTDLY
Reset Voltage
Reset Hysteresis
Reset Voltage Accuracy
Reset Low Level Voltage
EN Input High Voltage
EN Input High Voltage
RSTVOL
△VHYS
MP6402 Rev.1.0
4/8/2011
VIN=VOUT2+0.5V,
ExtCap=3300pF
VIN falling
1.4
2.1
ms
3
%VOUT2
%VOUT2
%
0.6
V
V
V
92.5
2
-3
RSTLOW
2.8
0.2
IIN=2mA
1.5
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MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
PIN FUNCTIONS
6
7
8
MP6402 Rev.1.0
4/8/2011
Name
IN
IN
EN
GND
ExtCap
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Pin #
1
2
3
4
5
OUT2
OUT1
Description
Power supply input pin.
Power supply input pin.
Enable (Active High). Connect EN to IN generally. Don’t float EN pin.
Ground.
Reset delay time set external capacitor connect pin.
Reset signal output pin.
Channel 2 LDO output pin.
Channel 1 LDO output pin.
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5
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3V, VOUT1=1.8V, VOUT2=2.5V, CIN = COUT1= COUT2=3.3µF, TA = +25ºC, unless otherwise noted.
Quiescent Current
vs. Temperature
Quiescent Current
vs. Temperature
IOUT1=IOUT2=0mA
Dropout Voltage
vs. Temperature
IOUT1=IOUT2=500mA
450
350
430
DR OP OUT V OL T AG E (mV )
1200
1150
410
390
1100
370
1050
350
330
1000
310
290
950
270
900
-40 -20 0
20 40 60 80 100
TEMPERATURE (oC)
-40 -20
60
100
0. 8
EN low threshold
0. 7
50
0. 5
0
0. 4
100 200 300 400 500
OUT P UT C UR R E NT (mA)
Current Limit
vs. Temperature
900
800
700
600
40
60
TEMPERATURE (oC)
MP6402 Rev.1.0
4/8/2011
80 100
0. 85
0. 8
0. 75
EN low threshold
0. 7
0. 65
3
3. 5
4
4. 5
5
INP UT V OL T AG E (V )
40
Line Regulation
Line Regulation
VOUT2=2.5V
0
IOUT=500mA
-0. 2
3
20
VOUT1=1.8V
IOUT=0A
-0. 1
0
3. 5
4
4. 5
5
INP UT V OL T AG E (V )
60
80 100
TEMPERATURE (oC)
0. 2
0. 1
0. 6
-40 -20
5. 5
0. 3
-0. 3
0
20 40 60 80 100
TEMPERATURE (oC)
EN high threshold
0. 9
0. 6
20
-40 -20
1
VEN (V)
VEN (V)
150
0
50
0. 95
0. 9
200
500
-40 -20
100
EN threshold
vs. Temperature
EN high threshold
1
250
0
150
0
80 100
1. 1
OUT P UT V OL T AG E AC C UR AC Y (% )
DR OP OUT V OL T AG E (mV )
40
200
EN threshold
vs. Input Voltage
300
C UR R E NT L IMIT (mA)
20
250
TEMPERATURE (oC)
Dropout Voltage
vs. Output Current
1000
0
5. 5
OUT P UT V OL T AG E AC C UR AC Y (% )
250
300
0. 3
0. 2
0. 1
IOUT=0A
0
-0. 1
IOUT=500mA
-0. 2
-0. 3
3
3. 5
4
4. 5
5
INP UT V OL T AG E (V )
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5. 5
6
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Load Regulation
VOUT2=2.5V
0.9
0.5
0.1
-0.3
-0.7
-1.1
0
100 200 300 400 500
OUTP UT CUR R ENT(mA)
PSRR Frequency Ranged
From 10Hz to 2MHz
80
IO=100mA
70
0.9
0.5
0.1
-0.3
-0.7
-1.1
0
100 200 300 400 500
OUTP UT CUR R ENT(mA)
Output Voltage Accuracy
vs. Temperature
0. 8
100
IOUT1=10mA
0. 6
0. 4
VOUT2
0. 2
0
VOUT1
-0. 2
-0. 4
-0. 6
-0. 8
-40 -20
Region of Stable COUT ESR
vs. Output Current
0
20 40 60 80 100
TEMPERATURE (oC)
RESET Delay Time
vs. Ext Cap
10000
VOUT1
50
10
VOUT2
40
DELAY TIME (ms)
60
PSRR (dB)
OUT P UT V OL T AG E AC C UR AC Y (% )
Load Regulation
VOUT1=1.8V
OU TP U T V OL TA G E A C C U R A C Y (% )
OU TP U T V OL TA G E A C C U R A C Y (% )
VIN = 3V, VOUT1=1.8V, VOUT2=2.5V, CIN = COUT1= COUT2=3.3µF, TA = +25ºC, unless otherwise noted.
30
20
1
10
Unstable Range
1000
100
10
0
Stable Range
-10
-20
101
102
103 104 105 106
FREQUENCY(Hz)
107
0.1
0
100 200 300 400
OUTPUT CURRENT(mA)
500
1
1
10
100
1000
10000
EXT CAP (nF)
RESET Delay Time
vs. Temperature
ExtCap=3300pF
3
DELAY TIME (ms)
2.5
2
1.5
1
-40
MP6402 Rev.1.0
4/8/2011
-15
10
35
60
TEMPERATURE (oC)
85
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MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3V, VOUT1=1.8V, VOUT2=2.5V, CIN = COUT1= COUT2=3.3µF, TA = +25ºC, unless otherwise noted.
Input Power Start Up
VOUT1
1V/div
IOUT1
500mA/div
VOUT1
1V/div
IOUT1
500mA/div
VOUT2
2V/div
IOUT2
500mA/div
VOUT2
2V/div
IOUT2
500mA/div
VIN
2V/div
1ms/div
VIN
2V/div
EN
3V/div
4ms/div
Line Transient
EN Shutdown
VOUT1/AC
10mV/div
IOUT
500mA/div
VIN
2V/div
EN
3V/div
VOUT1=1.8V, IOUT=10mA to 500mA
with Resistor Load
VOUT1/AC
50mV/div
VOUT2/AC
10mV/div
VOUT2
2V/div
IOUT2
500mA/div
Load Transient
VIN=3V to 5.5V, IOUT=500mA
with Resistor Load
IOUT1=IOUT2=500mA
with Resistor Load
VOUT1
1V/div
IOUT1
500mA/div
IOUT1=IOUT2=500mA
with Resistor Load
IOUT1=IOUT2=500mA
with Resistor Load
VOUT1
1V/div
IOUT1
500mA/div
VOUT2
2V/div
IOUT2
500mA/div
EN Start Up
Input Power Shutdown
IOUT1=IOUT2=500mA
with Resistor Load
4ms/div
Over Current
Protection Entry
Load Transient
VOUT2=2.5V, IOUT=10mA to 500mA
with Resistor Load
Over Current
Protection Steady State
VOUT1
1V/div
VOUT2/AC
50mV/div
VOUT1
1V/div
IOUT
500mA/div
VIN
2V/div
IOUT
200mA/div
VOUT2
2V/div
VIN
2V/div
IIN
200mA/div
10ms/div
MP6402 Rev.1.0
4/8/2011
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MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3V, VOUT1=1.8V, VOUT2=2.5V, CIN = COUT1= COUT2=3.3µF, TA = +25ºC, unless otherwise noted.
Over Current
Protection Recovery
RESET Timing
ExtCap=3300pF
VOUT1
1V/div
VOUT2
1V/div
VIN
2V/div
IOUT
200mA/div
RESET
2V/div
EN
2V/div
2ms/div
MP6402 Rev.1.0
4/8/2011
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MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
BLOCK DIAGRAM
IN
Current Limit
Reference
Voltage
--
+
OUT1
Current Limit
--
+
OUT2
Thermal
Shut Down
Detecter
Reset Timer
SHUTDOWN
LOGIC
EN
ExtCap
RESET
GND
Figure 1—MP6402 Block Diagram
MP6402 Rev.1.0
4/8/2011
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MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
TIMING DIAGRAM
VIN
0.8V
0
t
VIT
VOUT2
0
t
Td
Td
RESET
0
t
Td=RESET Delay
=Undefined State
Figure 2—RESET Timing Diagram
MP6402 Rev.1.0
4/8/2011
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11
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
OPERATION
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The MP6402 integrates two low-noise, lowdropout, low-quiescent current linear regulators
with a reset circuit. It operates from a 2.5V to
5.5V input voltage. The dual-channel LDOs can
supply up to 500mA of load current. The internal
reset circuit is used to monitor the output voltage
of channel 2. The
becomes active (low)
when output voltage drops below its threshold.
The MP6402 uses the internal P-channel
MOSFET as the pass element and features
internal thermal shutdown and internal current
limit circuits.
Linear Regulator
The MP6402 integrates dual-channel LDOs. The
output voltages are fixed. Their values range
from 0.9V and 3.3V with ±1.5% accuracy. Each
channel of MP6402 can supply up to 500mA of
load current.
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Reset Function
The reset circuit monitors the OUT2 pin voltage.
is a open-drain, active-low signal pin. It
should be connected to power supply through a
pull up resistor (R1 should be larger than 10kΩ).
becomes active (low) when output
voltage of channel 2 drops below its threshold.
The thermal shutdown will make the
active. When the activated triggering condition is
will become inactive after a
removed,
pre-set delay time. The delay time is
programmable through external capacitor
between ExtCap and GND.
Current Limit
The MP6402 includes two independent current
limit structures which monitor and control the
gate voltage of the pass element to limit the
guaranteed maximum output current to 500mA.
Output Discharge
The part involves a discharge function that
provides a 100Ω resistive discharge path for the
external output capacitor. The function will be
active when the part is disabled and it will be
done in a very limited time.
Thermal Shutdown
Thermal protection turns off the pass element
when the junction temperature exceeds +150ºC,
allowing cooling the IC. When the IC’s junction
temperature drops by 20ºC, the pass element will
be turned on again. Thermal protection limits
total power dissipation in the MP6402. For
reliable operation, junction temperature should
be limited to 125 ºC maximum.
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EN Shutdown
The MP6402 can be switched ON or OFF by a
logic input at the EN pin. A high voltage at this
pin will turn the device on. When the EN pin is
low, the regulator is off and the supply current is
reduced. If this feature is not to be used, the EN
input should be tied to IN pin to keep the
regulator on at all time. Do not float the EN pin.
MP6402 Rev.1.0
4/8/2011
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MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
APPLICATION INFORMATION
Operating Region and Power Dissipation
The maximum power dissipation of MP6402
depends on the thermal resistance of the case
and circuit board, the temperature difference
between the die junction and ambient air, and the
rate of airflow. The power dissipation across the
device is
Programmable Reset Delay Time
The reset delay time is determined by the value
of external capacitor (C4) connected to ExtCap
pin. Typically the reset delay time is 2.1mSec
when the external capacitor is 3300pF. For a
given delay time, the capacitor value can be
calculated using the following equation:
P = IOUT x (VIN - VOUT)
TD (ms) = [C 4 (nF) × 0.6] + 0.1
The maximum power dissipation is:
PD (MAX) = (TJ (MAX)-TA)/θJA
Where (TJ (MAX) – TA) is the temperature
difference between the MP6402 die junction and
the surrounding environment, θJA is the thermal
resistance from the junction to the surrounding
environment. The FIN of the MP6402 performs
the dual function of providing an electrical
connection to ground and channeling heat away.
Connect the FIN to ground using a large pad or
ground plane.
The reset delay time is determined by the charge
time of external capacitor. Stray capacitance may
cause errors of the delay time. A ceramic
capacitor with low leakage is strongly
recommended.
Input Capacitor Selection
Using a capacitor whose value is higher than 1µF
on the MP6402 input and the amount of
capacitance can be increased without limit.
Larger values will help improve line transient
response with the drawback of increased size.
Ceramic capacitors are preferred.
Output Capacitor Selection
The MP6402 is designed specifically to work with
very low ESR ceramic output capacitor in spacesaving and performance consideration. A
ceramic capacitor in the range of 3.3µF and 10µF,
and with ESR lower than 0.5Ω is suitable for the
MP6402 application circuit. Output capacitor of
larger values will help to improve load transient
response and reduce noise with the drawback of
increased size.
MP6402 Rev.1.0
4/8/2011
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13
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
0.189(4.80)
0.197(5.00)
8
0.124(3.15)
0.136(3.45)
5
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.089(2.26)
0.101(2.56)
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.013(0.33)
0.020(0.51)
0.051(1.30)
0.067(1.70)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.0075(0.19)
0.0098(0.25)
SIDE VIEW
0.050(1.27)
BSC
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0.050(1.27)
0.024(0.61)
0o-8o
0.016(0.41)
0.050(1.27)
0.063(1.60)
DETAIL "A"
0.103(2.62)
0.213(5.40)
NOTE:
0.138(3.51)
RECOMMENDED LAND PATTERN
MP6402 Rev.1.0
4/8/2011
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
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MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
14
MP6402 –DUAL 500MA LDO LINEAR REGULATORS WITH INTEGRATED RESET IC
TQFN8 (3mm x 3mm)
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.20
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
8
1
2.25
2.55
0.65
BSC
4
5
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.70
0.80
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
2.90
0.70
1.70
0.25
2.50
0.65
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP6402 Rev. 1.0
4/8/2011
www. MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
15