LINER LTC2355-14 18-bit, 1.6msps, pseudo-differential unipolar sar Datasheet

LTC2369-18
18-Bit, 1.6Msps, PseudoDifferential Unipolar SAR
ADC with 96.5dB SNR
FEATURES
DESCRIPTION
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The LTC®2369-18 is a low noise, low power, high speed
18-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2369-18 has a 0V
to VREF pseudo-differential unipolar input range with VREF
ranging from 2.5V to 5.1V. The LTC2369-18 consumes only
18mW and achieves ±2.5LSB INL maximum, no missing
codes at 18 bits with 96.5dB SNR.
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1.6Msps Throughput Rate
±2.5LSB INL (Max)
Guaranteed 18-Bit No Missing Codes
Low Power: 18mW at 1.6Msps, 18μW at 1.6ksps
96.5dB SNR (Typ) at fIN = 2kHz
–120dB THD (Typ) at fIN = 2kHz
Guaranteed Operation to 125°C
2.5V Supply
Pseudo-Differential Unipolar Input Range: 0V to VREF
VREF Input Range from 2.5V to 5.1V
No Pipeline Delay, No Cycle Latency
1.8V to 5V I/O Voltages
SPI-Compatible Serial I/O with Daisy-Chain Mode
Internal Conversion Clock
16-Lead MSOP and 4mm × 3mm DFN Packages
The LTC2369-18 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic while
also featuring a daisy-chain mode. The fast 1.6Msps
throughput with no cycle latency makes the LTC2369-18
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing external timing considerations. The LTC2369-18 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
APPLICATIONS
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L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 7705765.
Medical Imaging
High Speed Data Acquisition
Portable or Compact Instrumentation
Industrial Process Control
Low Power Battery-Operated Instrumentation
ATE
TYPICAL APPLICATION
32k Point FFT fS = 1.6Msps, fIN = 2kHz
2.5V
0
1.8V TO 5V
SNR = 96.5dB
THD = –127dB
SINAD = 96.5dB
SFDR = 134dB
–20
VREF
+
0V
VDD
5.1Ω
OVDD
IN+
LT®6202
–
0.1μF
LTC2369-18
10nF
IN–
REF
GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
–40
SAMPLE CLOCK
AMPLITUDE (dBFS)
10μF
–60
–80
–100
–120
–140
236918 TA01a
2.5V TO 5.1V
47μF
(X5R, 0805 SIZE)
–160
–180
0
100 200 300 400 500 600 700 800
FREQUENCY (kHz)
236918 TA01b
236918fa
1
LTC2369-18
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF).................................................6V
Analog Input Voltage (Note 3)
IN+, IN– .........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2369C ................................................ 0°C to 70°C
LTC2369I .............................................–40°C to 85°C
LTC2369H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
CHAIN
1
VDD
2
GND
3
+
4
IN–
5
GND
6
REF
7
REF
8
IN
16 GND
15 OVDD
17
GND
TOP VIEW
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
14 SDO
13 SCK
12 RDL/SDI
11 BUSY
10 GND
9 CNV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
DE PACKAGE
16-LEAD (4mm w 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2369CMS-18#PBF
LTC2369CMS-18#TRPBF
236918
16-Lead Plastic MSOP
0°C to 70°C
LTC2369IMS-18#PBF
LTC2369IMS-18#TRPBF
236918
16-Lead Plastic MSOP
–40°C to 85°C
LTC2369HMS-18#PBF
LTC2369HMS-18#TRPBF
236918
16-Lead Plastic MSOP
–40°C to 125°C
LTC2369CDE-18#PBF
LTC2369CDE-18#TRPBF
23698
16-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2369IDE-18#PBF
LTC2369IDE-18#TRPBF
23698
16-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
236918fa
2
LTC2369-18
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range (IN+)
MIN
TYP
MAX
UNITS
(Note 5)
l
–0.1
VIN –
Absolute Input Range (IN–)
(Note 5)
l
VIN+ – VIN–
Input Differential Voltage Range
VIN = VIN+ – VIN–
l
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
fIN = 800kHz
80
dB
VREF + 0.1
V
–0.1
0.1
V
0
VREF
V
±1
μA
l
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
UNITS
Resolution
l
18
Bits
No Missing Codes
l
18
Bits
l
–2.5
±0.5
2.5
LSB
l
–0.5
±0.1
0.5
LSB
l
–11
0
11
Transition Noise
INL
Integral Linearity Error
DNL
Differential Linearity Error
ZSE
Zero-Scale Error
1.3
(Note 6)
(Note 7)
Zero-Scale Error Drift
FSE
TYP
Full-Scale Error
LSBRMS
0.04
(Note 7)
l
–50
Full-Scale Error Drift
±5
LSB
LSB/°C
50
±0.15
LSB
ppm/°C
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 2kHz, VREF = 5V
l
92.2
96.5
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
l
91.7
96.5
dB
SNR
Signal-to-Noise Ratio
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
l
92.6
87
96.5
90.7
dB
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l
l
92
86.4
96.5
90.7
dB
dB
Total Harmonic Distortion
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
l
Spurious Free Dynamic Range
fIN = 2kHz, VREF = 5V
l
THD
SFDR
–120
–107
–103
–103
UNITS
dB
dB
122
dB
–3dB Input Bandwidth
34
MHz
Aperture Delay
500
ps
4
ps
200
ns
Aperture Jitter
Transient Response
Full-Scale Step
103
MAX
236918fa
3
LTC2369-18
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VREF
Reference Voltage
(Note 5)
l
MIN
IREF
Reference Input Current
(Note 9)
l
TYP
2.5
0.85
MAX
UNITS
5.1
V
1.1
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500μA
l
VOL
Low Level Output Voltage
IO = 500μA
l
l
VIH
VIN = 0V to OVDD
TYP
MAX
UNITS
0.8 • OVDD
l
V
–10
0.2 • OVDD
V
10
μA
5
pF
OVDD – 0.2
V
0.2
–10
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
ISOURCE
Output Source Current
VOUT = 0V
–10
10
mA
μA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
l
OVDD
Supply Voltage
l
IVDD
IOVDD
IPD
IPD
Supply Current
Supply Current
Power Down Mode
Power Down Mode
1.6Msps Sample Rate
1.6Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
PD
Power Dissipation
Power Down Mode
Power Down Mode
1.6Msps Sample Rate
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
MIN
TYP
MAX
2.375
2.5
2.625
V
1.71
5.25
V
8.6
l
l
l
UNITS
7.2
0.7
0.9
0.9
90
140
mA
mA
μA
μA
18
2.25
2.25
21.5
225
315
mW
μW
μW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.6
Msps
412
ns
fSMPL
Maximum Sampling Frequency
l
tCONV
Conversion Time
l
360
tACQ
Acquisition Time
l
200
ns
tCYC
Time Between Conversions
l
625
ns
tCNVH
CNV High Time
l
20
ns
tACQ = tCYC – tCONV – tBUSYLH (Note 10)
tBUSYLH
CNV↑ to BUSY Delay
CL = 20pF
l
tCNVL
Minimum Low Time for CNV
(Note 11)
l
20
ns
tQUIET
SCK Quiet Time from CNV↑
(Note 10)
l
20
ns
tSCK
SCK Period
(Notes 11, 12)
l
10
ns
tSCKH
SCK High Time
l
4
ns
13
ns
236918fa
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LTC2369-18
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
tSCKL
SCK Low Time
CONDITIONS
tSSDISCK
SDI Setup Time From SCK↑
tHSDISCK
tSCKCH
tDSDO
MIN
TYP
MAX
UNITS
l
4
ns
(Note 11)
l
4
ns
SDI Hold Time From SCK↑
(Note 11)
l
1
ns
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
13.5
ns
SDO Data Valid Delay from SCK↑
CL = 20pF (Note 11)
l
tHSDO
SDO Data Remains Valid Delay from SCK↑
CL = 20pF (Note 10)
l
9.5
1
ns
ns
tDSDOBUSYL
SDO Data Valid Delay from BUSY↓
CL = 20pF (Note 10)
l
5
ns
tEN
Bus Enable Time After RDL↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL↑
(Note 11)
l
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1.6MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and
00 0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: fSMPL = 1.6MHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tWIDTH
0.2*OVDD
tDELAY
tDELAY
0.8*OVDD
0.8*OVDD
0.2*OVDD
0.2*OVDD
50%
50%
236918 F01
Figure 1. Voltage Levels for Timing Specifications
236918fa
5
LTC2369-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V,
fSMPL = 1.6Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
0.5
2.0
40000
0.4
1.5
X = 1.3
35000
0.3
0.5
0.0
–0.5
–1.0
30000
0.2
0.1
COUNTS
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0.0
–0.1
20000
15000
–0.2
10000
–0.3
–1.5
25000
5000
–0.4
–0.5
–2.0
0
65536
131072
196608
OUTPUT CODE
0
262144
65536
131072
196608
OUTPUT CODE
0
131067 131069 131071 131073 131075 131077
CODE
262144
236918 G02
236918 G01
236918 G03
32k Point FFT fS = 1.6Msps,
fIN = 2kHz
–20
–70
95
SNR
SNR, SINAD (dBFS)
AMPLITUDE (dBFS)
–40
–60
100
SNR = 96.5dB
THD = –127dB
SINAD = 96.5dB
SFDR = 134dB
–60
–80
–100
–120
HARMONICS, THD (dBFS)
0
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input Frequency
90
SINAD
85
80
–140
–80
THD
–90
2ND
–100
3RD
–110
–120
–130
–140
75
–160
–150
–180
0
70
100 200 300 400 500 600 700 800
FREQUENCY (kHz)
0
25
50
–160
75 100 125 150 175 200
FREQUENCY (kHz)
0
25
50
75 100 125 150 175 200
FREQUENCY (kHz)
236918 G04
236918 G05
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
98.0
97
97.5
96
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
–100
–105
97.0
SNR
96.5
SINAD
96.0
95
HARMONICS, THD (dBFS)
SNR
SNR, SINAD (dBFS)
SNR, SINAD (dBFS)
SNR, SINAD vs Input level,
fIN = 2kHz
236918 G06
SINAD
94
93
92
–110
–115
THD
–120
2ND
–125
–130
3RD
–135
–140
95.5
91
95.0
–40
90
2.5
–30
–20
–10
INPUT LEVEL (dB)
0
236918 G07
–145
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
236918 G08
–150
2.5
3
4
4.5
3.5
REFERENCE VOLTAGE (V)
5
236918 G09
236918fa
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LTC2369-18
TYPICAL PERFORMANCE CHARACTERISTICS
fSMPL = 1.6Msps, unless otherwise noted.
THD, Harmonics vs Temperature,
fIN = 2kHz
–110
97.5
–115
97.0
SNR
96.5
SINAD
96.0
95.5
95.0
–120
THD
–125
2ND
–130
3RD
–135
94.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
–145
–55 –35 –15
0
MIN DNL
–0.5
MIN INL
Full-Scale Error vs Temperature
236918 G12
Supply Current vs Temperature
Offset Error vs Temperature
10
8
IVDD
POWER SUPPLY CURRENT (mA)
8
15
6
OFFSET ERROR (LSB)
10
5
0
–5
–10
4
2
0
–2
–4
–6
–15
–10
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65
TEMPERATURE (°C)
2
IREF
IOVDD
5 25 45 65 85 105 125
TEMPERATURE (°C)
Reference Current
vs Reference Voltage
0.9
40
0.8
95
REFERENCE CURRENT (mA)
35
90
CMRR (dB)
30
85
80
0.7
0.6
0.5
0.4
0.3
0.2
75
0.1
5
0
–55 –35 –15
3
236918 G15
100
10
4
CMRR vs Input Frequency
IVDD + IOVDD + IREF
15
5
236918 G14
Shutdown Current vs Temperature
20
6
0
–55 –35 –15
85 105 125
236918 G13
25
7
1
–8
–20
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
236918 G11
20
FULL-SCALE ERROR (LSB)
MAX DNL
–1.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
236918 G10
POWER-DOWN CURRENT (μA)
MAX INL
0.5
–140
94.5
45
INL/DNL vs Temperature
1.0
INL/DNL ERROR (LSB)
98.0
HARMONICS, THD (dBFS)
SNR, SINAD (dBFS)
SNR, SINAD vs Temperature,
fIN = 2kHz
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V,
70
5 25 45 65 85 105 125
TEMPERATURE (°C)
236918 G16
0
100 200 300 400 500 600 700 800
FREQUENCY (kHz)
0
2.5
3
4.5
4
3.5
REFERENCE VOLTAGE (V)
5
236918 G17
236918 G18
236918fa
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LTC2369-18
PIN FUNCTIONS
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2369-18 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2369-18 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by OVDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10μF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+ (Pin 4): Analog Input. IN+ operates differential with
respect to IN– with an IN+-IN– range of 0V to VREF.
IN– (Pin 5): Analog Ground Sense. IN– has an input range
of ±100mV with respect to GND and must be tied to the
ground plane or a remote ground sense.
REF (Pins 7, 8): Reference Inputs. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47μF ceramic capacitor
(X5R, 0805 size).
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in normal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result
or daisy-chain data is output on this pin on each rising
edge of SCK MSB first. The output data is in straight binary
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.
GND (Exposed Pad Pin 17, DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
236918fa
8
LTC2369-18
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
OVDD = 1.8V to 5V
REF = 5V
IN+
+
18-BIT SAMPLING ADC
IN–
SPI
PORT
–
CHAIN
SDO
RDL/SDI
SCK
CNV
CONTROL LOGIC
BUSY
GND
236918 BD
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0
CNV
BUSY
CONVERT
POWER-DOWN AND ACQUIRE
SCK
SDO
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
D7 D6
D5 D4 D3
D2 D1
D0
236918 TD01
236918fa
9
LTC2369-18
APPLICATIONS INFORMATION
OVERVIEW
Fast 1.6Msps throughput with no cycle latency makes
the LTC2369-18 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The
LTC2369-18 dissipates only 18mW at 1.6Msps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
CONVERTER OPERATION
The LTC2369-18 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins to
sample the pseudo-differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the
conversion phase, the 18-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/262144)
using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog
input. The ADC control logic then prepares the 18-bit
digital output code for serial transfer.
1LSB = FS/262144
111...110
111...101
OUTPUT CODE
The LTC2369-18 is a low noise, low power, high speed 18-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2369-18 supports a
0V to VREF pseudo-differential unipolar input range with
VREF ranging from 2.5V to 5.1V, making it ideal for high
performance applications which require a wide dynamic
range. The LTC2369-18 achieves ±2.5LSB INL max, no
missing codes at 18 bits and 96.5dB SNR.
111...111
111...100
000...011
UNIPOLAR
ZERO
000...010
000...001
000...000
0V
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
236918 F02
Figure 2. LTC2369-18 Transfer Function
ANALOG INPUT
The analog inputs of the LTC2369-18 are pseudo-differential
in order to reduce any unwanted signal that is common
to both inputs. The analog inputs can be modeled by the
equivalent circuit shown in Figure 3. The diodes at the input
provide ESD protection. In the acquisition phase, each
input sees approximately 45pF (CIN) from the sampling
CDAC in series with 40Ω (RON) from the on-resistance
of the sampling switch. The IN+ input draws a current
spike while charging the CIN capacitor during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
REF
RON
40Ω
IN+
REF
IN–
RON
40Ω
CIN
45pF
CIN
45pF
BIAS
VOLTAGE
236918 F03
TRANSFER FUNCTION
The LTC2369-18 digitizes the full-scale voltage of REF
into 218 levels, resulting in an LSB size of 19μV with
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in straight binary format.
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2369-18
236918fa
10
LTC2369-18
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance input of the LTC2369-18 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC input
draws a current spike when entering acquisition.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Pseudo-Differential Unipolar Inputs
For best performance, a buffer amplifier should be used
to drive the analog input of the LTC2369-18. The amplifier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC input draws.
For most applications, we recommend the low power
LT6202 ADC driver to drive the LTC2369-18. With a low
noise density of 1.9nV/√Hz and a low supply current of
3mA, the LT6202 is flexible and may be configured to
convert signals of various amplitudes to the 0V to 5V input
range of the LTC2369-18.
Input Filtering
To achieve the full distortion performance of the
LTC2369-18, a low distortion single-ended signal source
driven through the LT6202 configured as a unity-gain buffer as shown in Figure 4 can be used to get the full data
sheet THD specification of –120dB.
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
LPF1
VREF
0V
50Ω
LPF2
+
66nF
BW = 48kHz
5.1Ω
LT6202
–
IN+
10nF
LTC2369-18
IN–
BW = 3.2MHz
236918 F04
Figure 4. Input Signal Chain
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
The LT6202 can also be used to buffer and convert large
true bipolar signals which swing below ground to the 0V
to 5V input range of the LTC2369-18. Figure 5a shows the
LT6202 being used to convert a ±10V true bipolar signal
for use by the LTC2369-18. In this case, the LT6202 is
configured as an inverting amplifier stage, which acts to
attenuate and level shift the input signal to the 0V to 5V input
range of the LTC2369-18. In the inverting configuration, the
single-ended input signal source no longer directly drives
a high impedance input. The input impedance is instead
set by resistor RIN. RIN must be chosen carefully based on
the source impedance of the signal source. Higher values
of RIN tend to degrade both the noise and distortion of
the LT6202 and LTC2369-18 as a system. Table 1 shows
the resulting SNR and THD for several values of RIN, R1,
R2, R3 and R4 in this configuration. Figure 5b shows the
resulting FFT when using the LT6202 as shown in Figure 5a.
236918fa
11
LTC2369-18
APPLICATIONS INFORMATION
VCM = VREF/2
200pF
R2
499Ω
R4
402Ω
ADC REFERENCE
+
3
R3
2k
10μF
5V
LT6202
0V
–
4
RIN
2k
10V
0V
–10V
1
R1
499Ω
200pF
236918 F05a
Figure 5a. LT6202 Converting a ±10V Bipolar Signal
to a 0V to 5V Input Signal
0
SNR = 96.1dB
THD = –97.3dB
SINAD = 92.7dB
SFDR = 97.5dB
–20
AMPLITUDE (dBFS)
–40
–60
The REF pin of the LTC2369-18 draws charge (QCONV) from
the 47μF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
IREF = QCONV/tCYC. The DC current draw of the REF pin,
IREF, depends on the sampling rate and output code. If
the LTC2369-18 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSBs.
–80
–100
–120
–140
–160
1
The LTC2369-18 requires an external reference to define
its input range. A low noise, low temperature drift reference is critical to achieving the full datasheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and
high accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2369-18. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2369-18 up to 125°C. We recommend bypassing the
LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805 size)
close to the REF pin.
100 200 300 400 500 600 700 800
FREQUENCY (kHz)
236918 F05b
Figure 5b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
Table 1. SNR, THD vs RIN for ±10V Input Signal
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k
499
499
2k
402
96.1
–97.3
10k
2.49k
2.49k
10k
2k
96
–92
100k
24.9k
24.9k
100k
20k
93.8
–93.5
When idling, the REF pin on the LTC2369-18 draws only
a small leakage current (< 1μA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 6, IREF quickly goes from approximately
0μA to a maximum of 1.1mA at 1.6Msps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the reference output voltage will affect the accuracy of the output
CNV
236918 F06
IDLE
PERIOD
IDLE
PERIOD
Figure 6. CNV Waveform Showing Burst Sampling
236918fa
12
LTC2369-18
APPLICATIONS INFORMATION
In applications where power management is critical and
the external reference may be powered down, it is recommended that REF is kept greater than 2V in order to
guarantee a maximum shutdown current of 140μA. In such
applications, a Schottky diode can be placed between REF
and VDD, as shown in Figure 7.
REF
VDD
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 8 shows
that the LTC2369-18 achieves a typical SNR of 96.5dB at
a 1.6MHz sampling rate with a 2kHz input.
0
SNR = 96.5dB
THD = –127dB
SINAD = 96.5dB
SFDR = 134dB
–20
–40
AMPLITUDE (dBFS)
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-5 reference is also recommended.
–60
–80
–100
–120
–140
–160
LTC2369-18
–180
0
236918 F07
100 200 300 400 500 600 700 800
FREQUENCY (kHz)
236918 F08
Figure 7. A Schottky Diode Between REF and VDD Maintains
REF > 2V for Applications Where the Reference May Be
Powered Down
Figure 8. 32k Point FFT with fIN = 2kHz of the LTC2369-18
Total Harmonic Distortion (THD)
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2369-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 8 shows that the LTC2369-18 achieves
a typical SINAD of 96.5dB at a 1.6MHz sampling rate with
a 2kHz input.
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD= 20log
V22 + V32 + V42 +…+ VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2369-18 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2369-18 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
236918fa
13
LTC2369-18
APPLICATIONS INFORMATION
The LTC2369-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2369-18
has a power-on-reset (POR) circuit that will reset the
LTC2369-18 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2369-18 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the
LTC2369-18. Once a conversion has been initiated, it cannot
be restarted until the conversion is complete. For optimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2369-18 powers down and begins acquiring the
input signal.
Internal Conversion Clock
The LTC2369-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 412ns. With a minimum acquisition time of 200ns, throughput performance
of 1.6Msps is guaranteed without any external adjustments.
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2369-18 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2369-18 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 9.
DIGITAL INTERFACE
The LTC2369-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2369-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
100MHz, a 1.6Msps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2369-18 is simple and
straightforward to use. The following sections describe the
operation of the LTC2369-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
8
POWER SUPPLY CURRENT (mA)
Power Supply Sequencing
7
6
5
IVDD
4
3
2
IOVDD
1
Auto Power-Down
The LTC2369-18 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
0
0
IREF
200 400 600 800 1000 1200 1400 1600
SAMPLING RATE (kHz)
236918 F09
Figure 9. Power Supply Current of the LTC2369-18
Versus Sampling Rate
236918fa
14
LTC2369-18
TIMING DIAGRAMS
Normal Mode, Single Device
Figure 10 shows a single LTC2369-18 operated in normal
mode with CHAIN and RDL/SDI tied to ground. With
RDL/SDI grounded, SDO is enabled and the MSB(D17) of
the new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2369-18.
When CHAIN = 0, the LTC2369-18 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven.
CONVERT
DIGITAL HOST
CNV
CHAIN
BUSY
IRQ
LTC2369-18
RDL/SDI
SDO
DATA IN
SCK
CLK
POWER-DOWN
AND ACQUIRE
CONVERT
POWER-DOWN AND ACQUIRE
CHAIN = 0
RDL/SDI = 0
CONVERT
tCYC
tCNVH
tCNVL
CNV
tACQ = tCYC – tCONV – tBUSYLH
tCONV
BUSY
tACQ
tSCK
tBUSYLH
tSCKH
1
SCK
2
3
tHSDO
tDSDOBUSYL
SDO
tQUIET
16
17
18
tSCKL
tDSDO
D17
D16
D15
D1
D0
236918 F10
Figure 10. Using a Single LTC2369-18 in Normal Mode
236918fa
15
LTC2369-18
TIMING DIAGRAMS
Normal Mode, Multiple Devices
be used to allow only one LTC2369-18 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 11,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
Figure 11 shows multiple LTC2369-18 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
RDLB
RDLA
CONVERT
CNV
CNV
CHAIN
CHAIN
LTC2369-18
SDO
B
BUSY
IRQ
LTC2369-18
DIGITAL HOST
SDO
A
RDL/SDI
RDL/SDI
SCK
SCK
DATA IN
CLK
POWER-DOWN
AND ACQUIRE
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
CHAIN = 0
tCNVL
CNV
tCONV
BUSY
tBUSYLH
RDL/SDIA
RDL/SDIB
tSCK
SCK
1
tSCKH
2
3
16
17
18
19
tHSDO
SDO
D17A
D16A
D15A
20
21
34
35
36
tSCKL
tDSDO
tEN
Hi-Z
tQUIET
tDIS
D1A
D0A
Hi-Z
D17B
D16B
D15B
D1B
D0B
Hi-Z
236918 F11
Figure 11. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
236918fa
16
LTC2369-18
TIMING DIAGRAMS
Chain Mode, Multiple Devices
number of converters. Figure 12 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 18 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
When CHAIN = OVDD, the LTC2369-18 operates in
chain mode. In chain mode, SDO is always enabled and
RDL/SDI serves as the serial data input pin (SDI) where
daisy-chain data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
CONVERT
OVDD
OVDD
CNV
CHAIN
RDL/SDI
CNV
CHAIN
LTC2369-18
DIGITAL HOST
LTC2369-18
RDL/SDI
SDO
A
IRQ
BUSY
B
DATA IN
SDO
SCK
SCK
CLK
POWER-DOWN
AND ACQUIRE
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
CHAIN = OVDD
RDL/SDIA = 0
tCYC
tCNVL
CNV
BUSY
tCONV
tBUSYLH
tSCKCH
SCK
1
2
3
16
17
tSSDISCK
18
19
20
34
35
36
tSCKL
tHSDO
tHSDISCK
SDOA = RDL/SDIB
tQUIET
tSCKH
tDSDO
D17A
D16A
D15A
D1A
D0A
D17B
D16B
D15B
D1B
D0B
tDSDOBUSYL
SDOB
D17A
D16A
D1A
D0A
236918 F12
Figure 12. Chain Mode Timing Diagram
236918fa
17
LTC2369-18
BOARD LAYOUT
To obtain the best performance from the LTC2369-18
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital clocks
or signals alongside analog signals or underneath the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1813A, the
evaluation kit for the LTC2369-18.
Partial Top Silkscreen
236918fa
18
LTC2369-18
BOARD LAYOUT
Partial Layer 1 Component Side
Partial Layer 2 Ground Plane
236918fa
19
LTC2369-18
BOARD LAYOUT
Partial Layer 3 PWR Plane
Partial Layer 4 Bottom Layer
236918fa
20
AIN –
J8
E7
EXT
VREF/2
R39
0Ω
JP5
HD1X3-100
EXT_CM
J4
AIN+
R14
0Ω
COUPLING
AC
DC
C46
1μF
3
2
1
C8
1μF
+2.5V
R15
OPT
HD1X3-100
JP2
CM
C18
OPT
C17
10μF
JP1
HD1X3-100
C47
OPT C48
10μF
6.3V
4
2
5
4
+3.3V
C2
0.1μF
R3
CLK
33Ω
TO CPLD
R41
OPT
R40
OPT
R9
OPT
C49
OPT
C63
10μF
6.3V
5
V+
2
C44
1μF
C59
1μF
V+
4
OUT1 1
U15
LT6202CS5
C57
0.1μF
V–
C43
0.1μF
C55
1μF
3 +IN1
V–
C61
10μF
6.3V
C42
15pF
R32
0Ω
V+
U2
R6 3 U8
3
NC7SZ04P5X NC7SVU04P5X
1k
5
COUPLING
AC
DC
1
R5
49.9Ω
1206
2
+3.3V
C1
0.1μF
R2
1k
+3.3V
2
J1
CLKIN
1
3
C5
0.1μF
2
–
+
3
C60
0.1μF
C58
OPT
R35
OPT
R45
ØΩ
R32
5.1Ω
R31
OPT
C11
0.1μF
9V TO 10V
+2.5V
R38
OPT
R58
ØΩ
SDO
5
1
3
5
7
9
11
13
9V TO
10V
C40
OPT
NPO
R19
0Ω
C7
0.1μF
IN–
LTC2369-18
IN+
C10
0.1μF
C6
10μF
6.3V
C39
0.01μF R16
0Ω 4
NPO
C9
10μF
6.3V
+3.3V
C65
OPT
0805 NPO
1
2
3
4
U20
LTC6655AHMS8-5
8
SHDN
GND
7
VIN
OUT_F
6
GND OUT_S
5
GND
GND
J3
DC590
2
4
6
8
10
12
14
R7
1k
RDL/SDI
3
2
1
JP6
FS
C56
0.1μF
1
3
3
R17 R13
2k
1k
U9
NC7SZ04P5X
2
4
VSS
6
5
7
3
2
1
C15
0.1μF
U7
C14
0.1μF 8 24LC025-I/ST
VCC
SCL
SCK
SDA
WP
CNV
ARRAY
A2
EEPROM
A1
A0
4
5
+3.3V
5
2
PR\
Q
D
VCC
R10
4.99k
R11
4.99k
CLKOUT
C16 1
0.1μF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
3
5
2 CNVST_33
FROM CPLD
U4
NC7SVU04P5X
+3.3V
C4
0.1μF
R12
4.99k
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
236918 BL
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J2
CON-EDGE 40-100
R4
7 33Ω 4
8
+3.3V
C3
0.1μF
R8
33Ω
DC590 DETECT
TO CPLD
CLR\
Q\
CP
GND
+3.3V
C13
0.8VREF
0.1μF
VREF
6
U3
NL17SZ74
+3.3V
4
HD1X3-100
U6
OPT NC7SZ66P5X 5
CNV
VCC
9
2 B
A 1
13 SCK
OE 4
14 SDO
GND
11 BUSY
3
12 RD
C20
47μF
6.3V
0805
CNV
SCK
SDO
BUSY
R46
ØΩ
VDD 2
OVDD 15
REF 7
8
REF
GND
GND
GND
GND
3
6
10
16
1
R1
33Ω
LTC2369-18
BOARD LAYOUT
Partial Schematic of Demoboard
236918fa
21
LTC2369-18
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
R = 0.115
TYP
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
9
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ± 0.05
PACKAGE
OUTLINE
0.40 ± 0.10
16
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE16) DFN 0806 REV Ø
8
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.45 BSC
1
0.23 ± 0.05
0.45 BSC
3.15 REF
3.15 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.305 ± 0.038
(.0120 ± .0015)
TYP
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
0.50
(.0197)
BSC
16151413121110 9
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
DETAIL “A”
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0° – 6° TYP
0.280 ± 0.076
(.011 ± .003)
REF
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1234567 8
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
0.50
(.0197)
BSC
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS16) 1107 REV Ø
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
236918fa
22
LTC2369-18
REVISION HISTORY
REV
DATE
DESCRIPTION
A
03/12
Updated conditions for IPD and PD in Power Requirements section
PAGE NUMBER
4
Added Figure 7 and associated text
13
236918fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2369-18
TYPICAL APPLICATION
LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal Into the LTC2369-18
LTC6655-5
VIN
VOUT_F
VOUT_S
8V
5V
200pF
47μF
R2
3k
5
V+
R4
402Ω
3
10μF
LT6202
2.5V
5V
+
0V 5.1Ω
R3
2k
IN+
1
4
–
REF
VDD
LTC2369-18
10nF
IN–
V–
2
10V
0V
–10V
RIN
2k
R1
499Ω
236918 TA02
–3V
220pF
RELATED PARTS
PART NUMBER
ADCs
LTC2379-18/LTC2378-18
LTC2377-18/LTC2376-18
LTC2380-16/LTC2378-16
LTC2377-16/LTC2376-16
LTC2383-16/LTC2382-16/
LTC2381-16
LTC2393-16/LTC2392-16/
LTC2391-16
LTC2355-14/LTC2356-14
LTC2366
DACS
LTC2757
DESCRIPTION
COMMENTS
18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low
Power ADC
16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low
Power ADC
16-Bit, 1Msps/500ksps/250ksps Serial, Low Power
ADC
16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, PinCompatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, PinCompatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages
3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package
2.35V to 3.6V Supply 6- and 8-Lead TSOT-23 Packages
LTC2641
LTC2630
References
LTC6655
LTC6652
Amplifiers
LT6202/LT6203
16-Bit/14-Bit/12-Bit Single Serial VOUT DACs
12-Bit/10-Bit/8-Bit Single VOUT DACs
±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm
LQFP-48 Package
±1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output
SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
Precision Low Drift Low Noise Buffered Reference
Precision Low Drift Low Noise Buffered Reference
5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Single/Dual 100MHz Rail-to-Rail Input/Output Noise
Low Power Amplifiers
165MHz/800MHz/1.6GHz Op Amp with
Unity Gain/AV = 5/AV = 10
Low Power, Fully Differential Input/Output Amplifier/
Driver Family
Low Noise SAR ADC Driver with True Zero Output
1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth
LT6200/LT6200-5/
LT6200-10
LTC1992
LT6360
14-Bit, 3.5Msps Serial ADC
12-Bit, 3Msps Serial ADC
18-Bit, Single Parallel IOUT SoftSpan™ DAC
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at
1MHz, TSOT23-6 Package
1mA Supply Current
Low Noise Integrated Charge Pump
236918fa
24 Linear Technology Corporation
LT 0312 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2011