TI1 LME49600TS/NOPB High-performance, high-fidelity, high-current headphone buffer Datasheet

LME49600
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LME49600 High-Performance, High-Fidelity, High-Current Headphone Buffer
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FEATURES
DESCRIPTION
•
The LME49600 is a high performance, low distortion
high fidelity 250mA audio buffer. The LME49600 is
designed for a wide range of applications. It can be
used inside the feedback loop of op amps.
1
2
•
•
•
•
Pin-Selectable Bandwidth and Quiescent
Current
Pure Fidelity, Pure Performance
Short Circuit Protection
Thermal Shutdown
TO–263 Surface-Mount Package
The LME49600 offers a pin-selectable bandwidth: a
low current, 110MHz bandwidth mode that consumes
7.3mA and a wide 180MHz bandwidth mode that
consumes 13.2mA. In both modes the LME49600 has
a nominal 2000V/μs slew rate. Bandwidth is easily
adjusted by either leaving the BW pin unconnected or
connecting a resistor between the BW pin and the
VEE pin.
APPLICATIONS
•
•
•
•
•
•
Headphone Amplifier Output Drive Stage
Line Drivers
Low Power Audio Amplifiers
High-Current Operational Amplifier Output
Stage
ATE Pin Driver Buffer
Power Supply Regulator
The LME49600 is fully protected through internal
current limit and thermal shutdown.
KEY SPECIFICATIONS
•
•
•
•
•
Low THD+N (VOUT = 3VRMS, f = 1kHz,
Figure 26): 0.00003% (typ)
Slew Rate: 2000V/μs (typ)
High Output Current: 250mA (typ)
Bandwidth
– BW Pin Floating: 110MHz (typ)
– BW Connected to VEE: 180MHz (typ)
Supply Voltage Range: ±2.25V ≤ VS ≤ ±18V
Typical Application Diagram
RFB
V
+
0.1 PF
10 PF
+
RIN
-
VCC
VCC
IN
LME49710
VIN
+
VEE
OUT
LME49600
0.1 PF
VEE
10 PF
+
RL
BW
-
V
Figure 1. High Performance, High Fidelity LME49600 Audio Buffer Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LME49600
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Functional Block Diagram
VCC
Thermal
Shutdown
I1
D1 - D7
Q5
I
Q3
Q1
IN
Q2
OUT
200:
Q4
BW
Q6
D8 - D14
I2
VEE
Figure 2. Simplified Circuit Diagram (Note: I1 and I2 are mirrored from I)
Connection Diagram
TAB (VEE)
AV = 1
1
2
3
BW
4
5
VEE
VIN
VCC
VOUT
The KTT package is non-isolated package. The package's metal back and any heat sink to which it is mounted are
connected to the same potential as the -VEE pin.
Figure 3. KTT Package (Top View)
See Package Number KTT0005B
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS (1) (2) (3)
Supply Voltage
±20V
ESD Ratings (4)
2000V
ESD Rating (5)
200V
−40°C to +150°C
Storage Temperature
Junction Temperature
Thermal Resistance
150°C
θJC
4°C/W
θJA
θJA
Soldering Information
(1)
(2)
(3)
(4)
(5)
(6)
65°C/W
(6)
20°C/W
TO-263 Package (10 seconds)
260°C
All voltages are measured with respect to ground, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF – 240pF discharged through all pins.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower. For the LME49600, typical application (shown in Figure 26) with VSUPPLY = 30V, RL = 32Ω, the total power dissipation is 1.9W.
θJA = 20°C/W for the TO–263 package mounted to 16in2 1oz copper surface heat sink area.
OPERATING RATINGS (1) (2)
Temperature Range
TMIN ≤ TA ≤ TMAX
Supply Voltage
(1)
(2)
−40°C ≤ TA ≤ 85°C
±2.25V to ±18V
All voltages are measured with respect to ground, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
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SYSTEM ELECTRICAL CHARACTERISTICS FOR LME49600
The following specifications apply for VS = ±15V, fIN = 1kHz, unless otherwise specified. Typicals and limits apply for TA =
25°C.
Symbol
IQ
THD+N
SR
Parameter
Total Quiescent Current
IOUT = 0
BW pin: No connect
BW pin: Connected to VEE pin
Total Harmonic Distortion + Noise (3)
AV = 1, VOUT = 3VRMS, RL
= 32Ω, BW = 80kHz,
closed loop see Figure 26.
f = 1kHz
f = 20kHz
7.3
13.2
10.5
18
mA (max)
mA (max)
V/μs
AV = –3dB
BW pin: No Connect
RL = 100Ω
RL = 1kΩ
100
110
MHz
MHz
AV = –3dB
BW pin: Connected to VEE pin
RL = 100Ω
RL = 1kΩ
160
180
MHz
MHz
f = 10kHz
BW pin: No Connect
3.0
nV/√Hz
f = 10kHz
BW pin: Connected to VEE pin
2.6
nV/√Hz
Settling Time
ΔV = 10V, RL = 100Ω
1% Accuracy
BW pin: No connect
BW pin: Connected to VEE pin
200
60
ns
ns
Voltage Gain
VOUT = ±10V
RL = 67Ω
RL = 100Ω
RL = 1kΩ
0.93
0.95
0.99
0.90
0.92
0.98
V/V (min)
V/V (min)
V/V (min)
Positive
IOUT = 10mA
IOUT = 100mA
IOUT = 150mA
VCC –1.4
VCC –2.0
VCC –2.3
VCC –1.6
VCC –2.1
VCC –2.7
V (min)
V (min)
V (min)
Negative
IOUT = –10mA
IOUT = –100mA
IOUT = –150mA
VEE +1.5
VEE +3.1
VEE +3.5
VEE +1.6
VEE +2.4
VEE +3.2
V (min)
V (min)
V (min)
Voltage Noise Density
IOUT
Units
(Limits)
2000
BW
VOUT
Limit (2)
%
%
Bandwidth
AV
LME49600
Typical (1)
0.000035
0.0005
Slew Rate
ts
Conditions
Voltage Output
30 ≤ BW ≤ 180MHz
VOUT = 20VP-P, RL = 100Ω
Output Current
±250
mA
Short Circuit Output Current
BW pin: No Connect
BW pin: Connected to VEE pin
±490
±490
±550
mA (max)
mA (max)
IB
Input Bias Current
VIN = 0V
BW pin: No Connect
BW pin: Connected to VEE pin
±1.0
±3.0
±2.5
±5.0
μA (max)
μA (max)
ZIN
Input Impedance
RL = 100Ω
BW pin: No Connect
BW pin: Connected to VEE pin
7.5
5.5
VOS
Offset Voltage
VOS/°C
Offset Voltage vs Temperature
IOUT-SC
(1)
(2)
(3)
4
±17
40°C ≤ TA ≤ +125°C
±100
MΩ
MΩ
±60
mV (max)
μV/°C
Typical specifications are specified at 25°C and represent the parametric norm.
Tested limits are ensured to AOQL (Average Outgoing Quality Level).
This is the distortion of the LME49600 operating in a closed loop configuration with an LME49710. When operating in an operational
amplifier's feedback loop, the amplifier’s open loop gain dominates, linearizing the system and determining the overall system distortion.
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TYPICAL PERFORMANCE CHARACTERISTICS
Gain vs Frequency vs Quiescent Current
Phase vs Frequency vs Quiescent Current
0
20
IQ = 10.3
-10
15
PHASE (°)
GAIN (dB)
IQ = 13.3
10
-20
-30
5
IQ = 7.4
-40
0
-5
1M
-50
1M
10M
100M
1G
IQ = 13.3 mA
IQ = 10.3 mA
IQ=7.4 mA
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4.
Figure 5.
Gain vs Frequency vs Power Supply Voltage
Wide BW Mode
Phase vs Frequency vs Supply Voltage
Wide BW Mode
0
20
VS = +/-18V
VS = +/-12V
VS = +/-5V
VS = +/-2.5V
-10
15
VS = ±12V
PHASE (°)
VS = ±18V
GAIN (dB)
1G
10
VS = ±5V
5
-20
-30
VS = ±2.5V
-40
0
-5
1M
10M
100M
-50
1M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6.
Figure 7.
Gain vs Frequency vs Power Supply Voltage
Low IQ Mode
Phase vs Frequency vs Supply Voltage
Low IQ Mode
0
20
VS = +/-18V
VS = +/-12V
VS = +/-5V
VS = +/-2.5V
-10
15
VS = ±18V
PHASE (°)
GAIN (dB)
VS = ±12V
10
VS = ±5V
5
-20
-30
VS = ±2.5V
-40
0
-5
1M
10M
100M
-50
1M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8.
Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain vs Frequency vs RLOAD
Wide BW Mode
Phase vs Frequency vs RLOAD
Wide BW Mode
0
20
PHASE (°)
GAIN (dB)
-10
RL = 1 k:
15
10
RL = 100:
-20
-30
5
RL = 1 k:
RL = 100:
RL = 50:
-40
0
RL = 50:
-5
1M
10M
100M
-50
1M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10.
Figure 11.
Gain vs Frequency vs RLOAD
Low IQ Mode
Phase vs Frequency vs RLOAD
Low IQ Mode
0
20
18
16
-10
14
PHASE (°)
GAIN (dB)
12
10
8
RL = 1 k:
RL = 100:
RL = 50:
6
4
2
-20
-30
RL = 1 k:
RL = 100:
RL = 50:
-40
0
-2
-4
1M
10M
-50
1M
1G
100M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12.
Figure 13.
Gain vs Frequency vs CLOAD
Wide BW Mode
Phase vs Frequency vs CLOAD
Wide BW Mode
0
20
CL = 50 pF
CL = 0 pF
CL = 50 pF
CL = 200 pF
CL = 1000 pF
-10
15
PHASE (°)
GAIN (dB)
CL = 0 pF
10
-20
-30
5
CL = 200 pF
-40
0
CL = 1000 pF
-5
1M
10M
-50
1M
100M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14.
6
10M
1G
Figure 15.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain vs Frequency vs CLOAD
Low IQ Mode
Phase vs Frequency vs CLOAD
Low IQ Mode
0
20
CL = 50 pF
CL = 0 pF
CL = 50 pF
CL = 200 pF
CL = 1000 pF
-10
PHASE (°)
GAIN (dB)
15
10
CL = 0 pF
5
-20
-30
CL = 200 pF
-40
0
CL = 1000 pF
-5
1M
10M
100M
-50
1M
1G
10M
Figure 17.
+PSRR vs Frequency
VS = ±15V, Wide BW Mode
+PSRR vs Frequency
VS = ±15V, Low IQ Mode
80
80
70
70
60
60
50
50
PSRR (dB)
PSRR (dB)
Figure 16.
40
30
40
30
20
20
10
10
200
2k
20k
0
20
200k
2k
20k
Figure 18.
Figure 19.
+PSRR vs Frequency
VS = ±15V, Wide BW Mode
+PSRR vs Frequency
VS = ±15V, Low IQ Mode
80
80
70
70
60
60
50
50
PSRR (dB)
PSRR (dB)
200
40
30
40
30
20
20
10
10
2k
200
20k
FREQUENCY (Hz)
200k
FREQUENCY (Hz)
FREQUENCY (Hz)
0
20
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
0
20
100M
200k
0
20
200
2k
20k
200k
FREQUENCY (Hz)
Figure 20.
Figure 21.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Voltage
VS = ±15V, RL = 32Ω, f = 1kHz
Both channels driven
0.01
14
13
12
0.001
THD+N (%)
QUIESCENT POWER SUPPLY CURRENT (mA)
Quiescent Current vs Bandwidth Control Resistance
11
10
9
0.0001
8
7
6
10
100
10000
1000
0.00001
0.00001 0.0001 0.001
100000
Figure 23.
High BW Noise Curve
Low BW Noise Curve
100
10
1
10
100
1k
1
10
10k
100k
100
FREQUENCY (Hz)
10
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 24.
8
0.1
Figure 22.
EQUIVALENT INPUT NOISE VOLTAGE (nV/rtHz)
EQUIVALENT INPUT NOISE VOLTAGE (nV/rtHz)
RESISTANCE (:)
1
0.01
OUTPUT POWER (W)
Figure 25.
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TYPICAL APPLICATION DIAGRAM
RFB
V
+
0.1 PF
10 PF
+
RIN
-
VCC
VCC
IN
LME49710
VIN
+
VEE
OUT
LME49600
0.1 PF
VEE
10 PF
+
RL
BW
-
V
Figure 26. High Performance, High Fidelity LME49600 Audio Buffer Application
DISTORTION MEASUREMENTS
The vanishingly low residual distortion produced by LME49710/LME49600 is below the capabilities of all
commercially available equipment. This makes distortion measurements just slightly more difficult than simply
connecting a distortion meter to the amplifier’s inputs and outputs. The solution, however, is quite simple: an
additional resistor. Adding this resistor extends the resolution of the distortion measurement equipment.
The LME49710/LME49600’s low residual distortion is an input referred internal error. As shown in Figure 27,
adding the 10Ω resistor connected between the amplifier’s inverting and non-inverting inputs changes the
amplifier’s noise gain. The result is that the error signal (distortion) is amplified by a factor of 101. Although the
amplifier’s closed-loop gain is unaltered, the feedback available to correct distortion errors is reduced by 101,
which means that measurement resolution increases by 101. To ensure minimum effects on distortion
measurements, keep the value of R1 low as shown in Figure 27.
This technique is verified by duplicating the measurements with high closed loop gain and/or making the
measurements at high frequencies. Doing so produces distortion components that are within the measurement
equipment’s capabilities. This data sheet’s THD+N and IMD values were generated using the above described
circuit connected to an Audio Precision System Two Cascade.
R2 1 k:
V+
10 PF
+
0.1 PF
R1
10:
VIN
IN
LME49710
+
VCC
VCC
LME49600
OUT
VEE 10 PF
+
VEE 0.1 PF
RL
BW
V-
Figure 27. THD+N Distortion Test Circuit
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APPLICATION INFORMATION
HIGH PERFORMANCE, HIGH FIDELITY HEADPHONE AMPLIFIER
The LME49600 is the ideal solution for high output, high performance high fidelity head phone amplifiers. When
placed in the feedback loop of the LME49710, LME49720 or LME49740 High Performance, High Fidelity audio
operational amplifier, the LME49600 is able to drive 32Ω headphones to a dissipation of greater than 500mW at
0.00003% THD+N while operating on ±15V power supply voltages. The circuit schematic for a typical headphone
amplifier is shown in Figure 28.
Operation
The following describes the circuit operation for the headphone amplifier’s Left Channel. The Right Channel
operates identically.
The audio input signal is applied to the input jack (HP31 or J1/J2) and dc-coupled to the volume control, VR1.
The output signal from VR1’s wiper is applied to the non-inverting input of U2-A, an LME49720 High
Performance, High Fidelity audio operational amplifier. U2-A’s AC signal gain is set by resistors R2, R4, and R6.
To allow for a DC-coupled signal path and to ensure minimal output DC voltage regardless of the closed-loop
gain, the other half of the U2 is configured as a DC servo. By constantly monitoring U2-A’s output, the servo
creates a voltage that compensates for any DC voltage that may be present at the output. A correction voltage is
generated and applied to the feedback node at U2-A, pin 2. The servo ensures that the gain at DC is unity.
Based on the values shown in Figure 28, the RC combination formed by R11 and C7 sets the servo’s high-pass
cutoff at 0.16Hz. This is over two decades below 20Hz, minimizing both amplitude and phase perturbations in the
audio frequency band’s lowest frequencies.
V+
V+
C19
0.1 PF
C24
C1
+
8
3
VR1-A
10k
+
-
+
1
LME49720NA
LME49600
3
C23
+
V-
J1 1
4
U3
BW
C2
4
R1
1k
4.7 PF
2
1
U1-A
2
2
5
1.0 PF
R3
1k
1.0 PF
4.7 PF
C20
JU1
C5
HP31
R9
1M
3
5
4
2
1
-
HP32
R5
1k
7
JU15
U1-B
5
+
1M
C6
2
V+
JU8
R10
0.1 PF
V-
1.0 PF
LME49720NA
6
JU14
C21
3
5
4
2
1
0.1 PF
C10
1.0 PF
+
J2 1
5
JU17
V+
8
+
1
1.0 PF
3
VR1-B
10k
2
C3
4
U4
BW
LME49600
+
1
3
U2-A
-
LME49720NA
4.7 PF
C22
C4
4
R2
1k
V-
C9
+
2
4.7 PF
R4
1k
1.0 PF
V-
0.1 PF
C7
1.0 PF
LME49720NA
6
R12
1M
R6
1k
7
U2-B
5
+
C8
JU4
R11
1M
1.0 PF
Figure 28. LME49600 Delivers High Output Current for this High Performance Headphone Amplifier
10
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AUDIO BUFFERS
Audio buffers or unity-gain followers, have large current gain and a voltage gain of one. Audio buffers serve
many applications that require high input impedance, low output impedance and high output current. They also
offer constant gain over a very wide bandwidth.
Buffers serve several useful functions, either in stand-alone applications or in tandem with operational amplifiers.
In stand-alone applications, their high input impedance and low output impedance isolates a high impedance
source from a low impedance load.
SUPPLY BYPASSING
The LME49600 will place great demands on the power supply voltage source when operating in applications that
require fast slewing and driving heavy loads. These conditions can create high amplitude transient currents. A
power supply’s limited bandwidth can reduce the supply’s ability to supply the needed current demands during
these high slew rate conditions. This inability to supply the current demand is further exacerbated by PCB trace
or interconnecting wire inductance. The transient current flowing through the inductance can produce voltage
transients.
For example, the LME49600’s output voltage can slew at a typical ±2000V/μs. When driving a 100Ω load, the
di/dt current demand is 20 A/μs. This current flowing through an inductance of 50nH (approximately 1.5” of 22
gage wire) will produce a 1V transient. In these and similar situations, place the parallel combination of a solid
5μF to 10μF tantalum capacitor and a ceramic 0.1μF capacitor as close as possible to the device supply pins.
Ceramic capacitors with values in the range of 10μF to 100μF, ceramic capacitor have very lower ESR (typically
less than 10mΩ) and low ESL when compared to the same valued tantalum capacitor. The ceramic capacitors,
therefore, have superior AC performance for bypassing high frequency noise.
In less demanding applications that have lighter loads or lower slew rates, the supply bypassing is not as critical.
Capacitor values in the range of 0.01μF to 0.1μF are adequate.
SIMPLIFIED LME49600 CIRCUIT DIAGRAM
The LME49600’s simplified circuit diagram is shown in Figure 2. The diagram shows the LME49600’s
complementary emitter follower design, bias circuit and bandwidth adjustment node.
Figure 29 shows the LME49600 connected as an open-loop buffer. The source impedance and optional input
resistor, RS, can alter the frequency response. As previously stated, the power supplies should be bypassed with
capacitors connected close to the LME49600’s power supply pins. Capacitor values as low as 0.01μF to 0.1μF
will ensure stable operation in lightly loaded applications, but high output current and fast output slewing can
demand large current transients from the power supplies. Place a recommended parallel combination of a solid
tantalum capacitor in the 5μF to 10μF range and a ceramic 0.1μF capacitor as close as possible to the device
supply pins.
V+
+10 PF
0.1PF
VCC
IN
OUT
LME49600
RS
VEE
0.1PF
BW
RL
10 PF
+
V-
Figure 29. Buffer Connections
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OUTPUT CURRENT
The LME49600 can continuously source or sink 250mA. Internal circuitry limits the short circuit output current to
approximately ±450mA. For many applications that fully utilize the LME49600’s current source and sink
capabilities, thermal dissipation may be the factor that limits the continuous output current.
The maximum output voltage swing magnitude varies with junction temperature and output current. Using
sufficient PCB copper area as a heat sink when the metal tab of the LME49600’s surface mount TO–263
package is soldered directly to the circuit board reduces thermal impedance. This in turn reduces junction
temperature. The PCB copper area should be in the range of 3in2 (12.9cm2) to 6in2 (38.7cm2).
THERMAL PROTECTION
LME49600 power dissipated will cause the buffer’s junction temperature to rise. A thermal protection circuit in the
LME49600 will disable the output when the junction temperature exceeds 150°C. When the thermal protection is
activated, the output stage is disabled, allowing the device to cool. The output circuitry is enabled when the
junction temperature drops below 150°C.
The TO–263 package has excellent thermal characteristics. To minimize thermal impedance, its exposed die
attach paddle should be soldered to a circuit board copper area for good heat dissipation. Figure 30 shows
typical thermal resistance from junction to ambient as a function of the copper area. The TO–263’s exposed die
attach paddle is electrically connected to the VEE power supply pin.
LOAD IMPEDANCE
The LME49600 is stable under any capacitive load when driven by a source that has an impedance of 50Ω or
less. When driving capacitive loads, any overshoot that is present on the output signal can be reduced by
shunting the load capacitance with a resistor.
OVERVOLTAGE PROTECTION
If the input-to-output differential voltage exceeds the LME49600’s Absolute Maximum Rating of 3V, the internal
diode clamps shown in Figure 2 and conduct, diverting current around the compound emitter followers of Q1/Q5
(D1 – D7 for positive input), or around Q2/Q6 (D8 – D14 for negative inputs). Without this clamp, the input
transistors Q1/Q2 and Q5/Q6 will zener and damage the buffer.
To ensure that the current flow through the diodes is held to a save level, the internal 200Ω resistor in series with
the input limits the current through these clamps. If the additional current that flows during this situation can
damage the source that drives the LME49600’s input, add an external resistor in series with the input (see
Figure 29).
BANDWITH CONTROL PIN
The LME49600’s –3dB bandwidth is approximately 110MHz in the low quiescent-current mode (7.3mA typical).
Select this mode by leaving the BW pin unconnected.
Connect the BW pin to the VEE pin to extend the LME49600’s bandwidth to a nominal value of 180MHz. In this
mode, the quiescent current increases to approximately 13.2mA. Bandwidths between these two limits are easily
selected by connecting a series resistor between the BW pin and VEE .
Regardless of the connection to the LME49600’s BW pin, the rated output current and slew rate remain constant.
With the power supply voltage held constant, the wide-bandwidth mode’s increased quiescent current causes a
corresponding increase in quiescent power dissipation. For all values of the BW pin voltage, the quiescent power
dissipation is equal to the total supply voltage times the quiescent current (IQ * (VCC + |VEE |)).
BOOSTING OP AMP OUTPUT CURRENT
When placed in the feedback loop, the LME49600 will increase an operational amplifier’s output current. The
operational amplifier’s open loop gain will correct any LME49600 errors while operating inside the feedback loop.
To ensure that the operational amplifier and buffer system are closed loop stable, the phase shift must be low.
For a system gain of one, the LME49600 must contribute less than 20° at the operational amplifier’s unity-gain
frequency. Various operating conditions may change or increase the total system phase shift. These phase shift
changes may affect the operational amplifier's stability.
12
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Unity gain stability is preserved when the LME49600 is placed in the feedback loop of most general-purpose or
precision op amps. When the LME46900 is driving high value capacitive loads, the BW pin should be connected
to the VEE pin for wide bandwidth and stable operation. The wide bandwidth mode is also suggested for high
speed or fast-settling operational amplifiers. This preserves their stability and the ability to faithfully amplify high
frequency, fast-changing signals. Stability is ensured when pulsed signals exhibit no oscillations and ringing is
minimized while driving the intended load and operating in the worst-case conditions that perturb the
LME49600’s phase response.
HIGH FREQUENCY APPLICATIONS
The LME49600’s wide bandwidth and very high slew rate make it ideal for a variety of high-frequency open-loop
applications such as an ADC input driver, 75Ω stepped volume attenuator driver, and other low impedance loads.
Circuit board layout and bypassing techniques affect high frequency, fast signal dynamic performance when the
LME49600 operates open-loop.
A ground plane type circuit board layout is best for very high frequency performance results. Bypass the power
supply pins (VCC and VEE) with 0.1μF ceramic chip capacitors in parallel with solid tantalum 10μF capacitors
placed as close as possible to the respective pins.
Source resistance can affect high-frequency peaking and step response overshoot and ringing. Depending on
the signal source, source impedance and layout, best nominal response may require an additional resistance of
25Ω to 200Ω in series with the input. Response with some loads (especially capacitive) can be improved with an
output series resistor in the range of 10Ω to 150Ω.
THERMAL MANAGEMENT
Heatsinking
For some applications, the LME49600 may require a heat sink. The use of a heat sink is dependent on the
maximum LME49600 power dissipation and a given application’s maximum ambient temperature. In the TO-263
package, heat sinking the LME49600 is easily accomplished by soldering the package’s tab to a copper plane on
the PCB. (Note: The tab on the LME49600’s TO-263 package is electrically connected to VEE.)
Through the mechanisms of convection, heat conducts from the LME49600 in all directions. A large percentage
moves to the surrounding air, some is absorbed by the circuit board material and some is absorbed by the
copper traces connected to the package’s pins. From the PCB material and the copper, it then moves to the air.
Natural convection depends on the amount of surface area that contacts the air.
If a heat conductive copper plane has perfect thermal conduction (heat spreading) through the plane’s total area,
the temperature rise is inversely proportional to the total exposed area. PCB copper planes are, in that sense, an
aid to convection. These planes, however, are not thick enough to ensure perfect heat conduction. Therefore,
eventually a point of diminishing returns is reached where increasing copper area offers no additional heat
conduction to the surrounding air. This is apparent in Figure 30 as the thermal resistance reaches an asymptote
above a copper area of 8in2). As can be seen, increasing the copper area produces decreasing improvements in
thermal resistance. This occurs, roughly, at 4in2 of 1 oz copper board. Some improvement continues until about
16in2. Boards using 2 oz copper boards will have decrease thermal resistance providing a better heat sink
compared to 1 oz. copper. Beyond 1oz or 2oz copper plane areas, external heat sinks are required. Ultimately,
the 1oz copper area attains a nominal value of 20°C/W junction to ambient thermal resistance (θJA) under zero
air flow.
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THERMAL IMPEDANCE (TJA)
70
60
50
40
30
20
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2
COPPER HEAT SINK AREA (in )
Figure 30. Thermal Resistance for 5-lead TO–263 Package Mounted on 1oz. Copper
A copper plane may be placed directly beneath the tab. Additionally, a matching plane can be placed on the
opposite side. If a plane is placed on the side opposite of the LME49600, connect it to the plane to which the
buffer’s metal tab is soldered with a matrix of thermal vias per JEDEC Standard JESD51-5.
Determining Copper Area
Find the required copper heat sink area using the following guidelines:
1. Determine the value of the circuit’s power dissipation, PD.
2. Specify a maximum operating ambient temperature, TA(MAX). (Note that the die temperature, TJ, will be higher
than TA by an amount that is dependent on the thermal resistance from junction to ambient, θJA). Therefore, TA
must be specified such that TJ does not exceed the absolute maximum die temperature of 150°C.
3. Specify a maximum allowable junction temperature, TJ(MAX), This is the LME49600’s die temperature when the
buffer is drawing maximum current (quiescent and load). It is prudent to design for a maximum continuous
junction temperature of 100°C to 130°C. Ensure, however, that the junction temperature never exceeds the
150°C absolute maximum rating for the part.
4. Calculate the value of junction to ambient thermal resistance, θJA
5. θJA as a function of copper area in square inches is shown in Figure 30. Choose a copper area that will ensure
the specified TJ(MAX) for the calculated θJA. The maximum value of junction to ambient thermal resistance, θJA, is
defined as:
θJA= (TJ(MAX) - TA(MAX) )/ PD(MAX)
(°C/W)
where
•
•
•
TJ(MAX) = the maximum recommended junction temperature
TA(MAX) = the maximum ambient temperature in the LME49600’s environment
PD(MAX) = the maximum recommended power dissipation
(1)
NOTE
The allowable thermal resistance is determined by the maximum allowable temperature
increase:
TRISE = TJ(MAX) - TA(MAX)
Thus, if ambient temperature extremes force TRISE to exceed the design maximum, the part must be de-rated by
either decreasing PD to a safe level, reducing θJA further or, if available, using a larger copper area.
Procedure
1. First determine the maximum power dissipated by the LME49600, PD(MAX). For the simple case of the buffer
driving a resistive load, and assuming equal supplies, PD(MAX) is given by:
PDMAX(AC) = (IS x VS) + (VS)2 / (2π2RL) (Watts)
14
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(2)
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PDMAX(DC) = (IS x VS) + (VS)2 / RL (Watts)
where
•
•
VS = |VEE| + VCC (V)
IS =quiescent supply current (A)
(3)
Equation (2) is for sinusoidal output voltages and Equation (3) is for DC output voltages.
2. Determine the maximum allowable die temperature rise,
TRISE(MAX) = TJ(MAX) - TA(MAX) (°C)
(4)
3. Using the calculated value of TRISE(MAX) and PD(MAX), find the required value of junction to ambient thermal
resistance combining Equation (1) and Equation (5) to derive Equation (9):
θJA = TRISE(MAX) / PD(MAX)
(5)
4. Finally, choose the minimum value of copper area from Figure 30 based on the value for θJA.
Example
Assume the following conditions: VS = |VEE| + VCC = 30V, RL = 32Ω, IS = 15mA, sinusoidal output voltage, TJ(MAX)
= 125°C, TA(MAX) = 85°C.
Applying Equation (3):
PDMAX = (IS x VS) + (VS)2 / 2π2RL
= (15mA)(30V) + 900V2 / 142Ω
= 1.86W
(6)
Applying Equation (5):
TRISE(MAX) = 125°C – 85°C
= 40°C
(7)
Applying Equation (9):
θJA = 40°C/1.86W
= 21.5°C/W
(8)
Examining the Copper Area vs. θJA plot indicates that a thermal resistance of 50°C/W is possible with a 12in2
plane of one layer of 1oz copper. Other solutions include using two layers of 1oz copper or the use of 2oz
copper. Higher dissipation may require forced air flow. As a safety margin, an extra 15% heat sinking capability is
recommended.
When amplifying AC signals, wave shapes and the nature of the load (reactive, non-reactive) also influence
dissipation. Peak dissipation can be several times the average with reactive loads. It is particularly important to
determine dissipation when driving large load capacitance.
The LME49600’s dissipation in DC circuit applications is easily computed using Equation (4). After the value of
dissipation is determined, the heat sink copper area calculation is the same as for AC signals.
SLEW RATE
A buffer’s voltage slew rate is its output signal’s rate of change with respect to an input signal’s step changes.
For resistive loads, slew rate is limited by internal circuit capacitance and operating current (in general, the higher
the operating current for a given internal capacitance, the faster the slew rate).
However, when driving capacitive loads, the slew rate may be limited by the available peak output current
according to the following expression.
dv/dt = IPK / CL
(9)
Output voltages with high slew rates will require large output load currents. For example if the part is required to
slew at 1000V/μs with a load capacitance of 1nF, the current demanded from the LME49600 is 1A. Therefore,
fast slew rate is incompatible with a capacitive load of this value. Also, if CL is in parallel with the load, the peak
current available to the load decreases as CL increases.
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V
+
Positive
Regulator
300:
1 k:
-
6550:
+VREG
+
OUT
1 PF
LM4040-5.0
LME49710
Negative
Regulator
300:
LME49600
1 k:
-
LM4040-5.0
-VREG
+
1 PF
OUT
-
-
V
6550:
V
-
LME49710
V
LME49600
Figure 31. High Speed Positive and Negative Regulator
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REVISION HISTORY
Rev
Date
1.0
01/15/08
Initial release.
Description
1.01
01/16/08
Edited specification table.
1.02
02/07/08
Edited applications information.
1.03
03/28/08
Text edits.
E
04/04/13
Changed layout of National Data Sheet to TI format
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17
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
LME49600TS/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DDPAK/
TO-263
KTT
5
45
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
LME49600
TS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2016
Addendum-Page 2
MECHANICAL DATA
KTT0005B
TS5B (Rev D)
BOTTOM SIDE OF PACKAGE
www.ti.com
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