Anpec APL5315-15 Selectable adjustable/fixed low dropout 300ma linear regulator Datasheet

APL5315
Selectable Adjustable/Fixed Low dropout 300mA Linear Regulator
Features
General Description
•
•
The APL5315 is a P-channel low dropout linear regulator
which needs only one input voltage from 2.7~6V, and
Wide Operating Voltage: 2.7~6V
Low Dropout Voltage:
delivers current up to 300mA to set output voltage. It also
can work with low ESR ceramic capacitors and is ideal for
230mV(typical) @ 300mA
•
•
•
•
•
•
•
•
Guaranteed 300mA Output Current
Two Modes for Setting Output Voltage
using in the battery-powered applications such as notebook computers, cellular phones. Typical dropout voltage
- Fixed Output Voltage: 1~5V
- Adjustable Output Voltage: 0.8~5.5V
is only 230mV at 300mA loading.
Current Limit Protection with Foldback Current
The APL5315 provides two kinds of output voltage
operation modes for setting the output voltage. Fixed
Internal Soft-Start
output voltage mode senses the output voltage on
VOUT, adjustable output voltage mode needs two
Over Temperature Protection
Stable with Low ESR Ceriamic Capacitor
resistors as a voltage divider. Current limit with current
foldback and thermal shutdown functions protect the
SOT-23-5 Package
Lead Free Available (RoHS Compliant)
device against current over-loads and over temperature.
The APL5315 is available in a SOT-23-5 package.
Simplified Application Circuit
Applications
APL5315
VIN
3
CIN
1
VIN
VOUT
SHDN
SET
4
VOUT
•
•
•
5
GND
COUT
2
Cellular Phones
Portable and Battery-powered Equipment
Notebook and Personal Computers
Ordering and Marking Information
APL5315
Lead Free Code
Handling Code
Temperature Range
Package Code
Voltage Code
Package Code
B : SOT- 23-5
Operating Junction Temperature Range
I : -40 to 85°C
Handling Code
TR : Tape & Reel
Voltage Code
12 : 1.2V
Blank: Adjustable
Lead Free Code
L : Lead Free Device
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully
compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Product Name
Marking
Product Name
Marking
Product Name
Marking
APL5315
35RX
APL5315-12
355X
APL5315-15
359X
APL5315-18
35CX
APL5315-25
35JX
APL5315- 33
35RX (Note2)
Note1 : Other voltage version please contact ANPEC for detail.
Note2 : Because APL5315 and APL5315-33 are identical, the marking of APL5315 is same as APL5315-33.
Pin Configuration
SHDN 1
GND 2
VIN 3
5 SET
4 VOUT
SOT-23-5
Absolute Maximum Ratings
Symbol
VIN
VSHND
PD
Rating
Unit
VIN Supply Voltage (VIN to GND)
Parameter
-0.3 ~ 6.5
V
SHND Input Voltage (SHND to GND)
-0.3 ~ 6.5
V
Power Dissipation
Internally Limited
W
TJ
Junction Temperature
-40 ~ 150
°C
TSTG
Storage Temperature
-65 ~ 150
°C
TSDR
Soldering Temperature, 10 Seconds
260
°C
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Thermal Resistance-Junction to Ambient (Note 3)
Unit
o
240
C/W
Note3 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VIN
Parameter
Range
2.7 ~ 6
V
VOUT
Output Voltage
0.8 ~ 5.5
V
IOUT
VOUT Output Current
0 ~ 300
mA
COUT
Output Capacitor
1.5 ~ 33
µF
Junction Temperature
-40 ~ 125
TJ
VIN Supply Voltage
Unit
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
2
o
C
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APL5315
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN = VOUT+1V (min VIN=2.7V), IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF,
TA = -40 to 85oC. Typical values are at TA = 25oC.
Symbol
VIN
VOUT
Parameter
APL5315
Test Condition
Unit
Min.
Typ.
Max.
Input Voltage
2.7
---
6
V
Output Voltage Range
0.8
---
5.5
V
UVLO Threshold
1.5
2.3
2.6
V
UVLO Hysteresis
---
0.8
---
V
---
120
160
µA
0.784
0.8
0.816
V
-2
---
+2
%
IQ
Quiescent Current
IOUT =10mA ~300mA
VREF
Reference Voltage
Measured on SET, VIN=2.7V, IOUT=10mA
Output Voltage Accuracy
Fixed output voltage, IOUT=10mA
REGLINE Line Regulation
ΔVOUT%/ΔVIN, IOUT=10mA
-0.06
---
+0.06
%/V
REGLOAD Load Regulation
ΔVOUT%/ΔIOUT
-0.2
---
+0.2
%/A
VOUT = 2.5V, IOUT = 300mA
---
230
360
VOUT = 3.3V, IOUT = 300mA
---
170
300
f = 10kHz, IOUT = 300mA
---
45
---
dB
f = 80Hz to 100KHz, IOUT = 300mA
---
160
---
µVRMS
400
500
650
mA
mA
VDROP
PSRR
Dropout Voltage
Power Supply Ripple Rejection
Ratio
Noise
ILIMIT
Current Limit
ISHORT
Foldback Current
mV
---
80
---
SHDN Input Voltage High
VOUT = 0V
1.6
---
---
SHDN Input Voltage Low
---
---
0.4
---
0.1
1
µA
---
3
---
MΩ
---
60
---
Ω
Over Temperature Threshold
---
160
---
°
C
Over Temperature Hysteresis
---
40
---
°
C
SET Input Threshold for
Fixed/Adjustable Output Voltage
---
100
---
mV
-100
---
100
nA
60
80
100
µs
V
Shutdown VIN Supply Current
SHDN = Low, VIN = 6V
SHDN Pull Low Resistance
VOUT Discharge MOSFET
SHDN = Low
RDS(ON)
Mode
SET input bias current
TSS
VSET=0.8V
Soft-Start Interval
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Typical Operating Characteristics
Quiescent Current vs. Supply Voltage
Quiescent Current vs. Junction Temperature
160
114
IOUT= 0mV
112
Quiescent Current, IQ (µA)
Quiescent Current, IQ (µA)
140
120
100
80
60
40
110
108
106
104
20
102
0
0
1
2
3
4
5
6
7
-50
-25
Supply Voltage, VIN (V)
Quiescent Current vs. Output Current
50
75
100
125
PSRR vs. Frequency
-10
140
-20
PSRR (dB)
160
VIN=5.5V
120
100
VIN=3.3V, VOUT=1.2V
CIN=1µF, COUT=2.2µF
IOUT=300mA
-30
-40
VIN=4.5V
-50
80
-60
60
0
50
100
150
200
250
1000
300
10000
100000
1000000
Frequency (Hz)
Output Current, I OUT (mA)
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
300
250
250
TJ=25°
C
TJ=75°
C
TJ=125°
C
200
150
100
TJ=25°
C
VOUT=3.3V
Dropout Voltage, VDROP (mV)
VOUT=2.5V
Dropout Voltage, VDROP (mV)
25
0
180
Quiescent Current, IQ (µA)
0
Junction Temperature, T J (°
C)
TJ=0°
C
TJ=-50°
C
50
0
TJ=75°
C
200
TJ=125°
C
150
100
TJ=0°
C
50
TJ=-50°
C
0
0
100
200
Output Current, I OUT (mA)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
0
300
4
100
200
Output Current, IOUT (mA)
300
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APL5315
Typical Operating Characteristics (Cont.)
Loop Gain vs. Frequency
Phase vs. Frequency
160
50
VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF
40
30
140
IOUT=100mA
IOUT=300mA
Phase (degree)
120
20
Loop Gain (dB)
VIN=3.3V, VOUT=1.2V, CIN=1µF, C OUT=2.2µF
10
0
100
80
60
-10
40
IOUT=300mA
-20
IOUT=100mA
20
-30
0
-40
1000
10000
100000
1000
1000000
Frequency (Hz)
10000
100000
1000000
Frequency (Hz)
Current Limit vs. Junction Temperature
600
Current Limit, ILIMIT (mA)
VIN=5V
550
500
450
400
-50
-25
0
25
50
75
Junction Temperature, T J (°
C)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
100
125
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APL5315
Operating Waveforms
Load Transient
Line Transient
VIN=3.3V, CIN=1µF, COUT=2.2µF, TR=1µs
CIN=1µF, COUT=2.2µF, TR=10µs, IOUT=10mA
V OUT
V IN
V OUT
IOUT
CH1 : VOUT, 50mV/div, AC
CH2 : IOUT, 100mA/div, DC
Time : 100µs/div
CH1 : VIN, 1V/div, DC
CH2 : VOUT, 20mV/div, AC
Time : 100µs/div
Enable
Shutdown
V OUT
V OUT
V SHDN
V SHDN
I OUT
I OUT
CH1 : VOUT, 500mV/div
CH2 : VSHDN, 5V/div
CH3 : IOUT, 200mA/div
Time : 50µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
CH1 : VOUT, 500mV/Div
CH2 : V
, 5V/Div
SHDN
CH3 : IOUT, 200mA/Div DC
Time : 10µs/Div
6
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APL5315
Operating Waveforms (Cont.)
Power on
Power off
V IN
V IN
V OUT
V OUT
I OUT
I OUT
CH1 : VIN, 2V/div
CH2 : VOUT, 500mV/div
CH3 : IOUT, 100mA/div
Time : 200µs/Div
CH1 : VIN, 2V/div
CH2 : VOUT,, 500mV/div,
CH3 : IOUT, 100mA/div
Time : 50ms/Div
Pin Descriptions
PIN
I/O
No
NAME
1
2
3
4
SHDN
GND
VIN
VOUT
I
O
5
SET
I
I
FUNCTION
Shutdown control pin, logic high: enable; logic low: shutdown
Ground pin
Voltage supply input pin
Regulator output pin
Connect this pin to ground for fixed output voltage operation. Connect this pin to an
external resistor divider for adjustable output voltage mode operation.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Block Diagram
UVLO &
Shutdown
Logic
SHDN
VIN
Foldback
current
limit
Thermal
Shutdown
+
VOUT
Low
3MΩ
SET
High
+
V REF
GND
100mV
Typical Application Circuits
1. Fixed Output Voltage Mode
APL5315
VIN
3
CIN
1µF
1
VIN
VOUT
SHDN
SET
4
VOUT
5
GND
COUT
2.2µF
2
Enable
Shutdown
2.2µF/GRM155R60J225M Murata
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Typical Application Circuits (Cont.)
2. Adjustable Output Voltage Mode
APL5315
VIN
3
CIN
1µF
1
VOUT
VIN
SET
SHDN
VOUT
4
5
R1
GND
COUT
2.2µF
2
Enable
R2
Shutdown
R1 

VOUT = 0.8 ⋅  1 +

R2


Functional Descriptions
Internal Soft-Start
ture of APL5315. When the junction temperature exceeds
+160οC, a thermal sensor turns off the output PMOS,
An internal soft-start function controls rising rate of the
output voltage to limit the surge current at start-up. The
allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-
typical soft-start interval is about 80µs.
start cycle after the junction temperature cools by 40οC.
The thermal shutdown designed with a 40οC hysteresis
Output Voltage Regulation
The APL5315 can works in either fixed or adjustable mode
lowers the average junction temperature during continuous thermal overload conditions, extending life time of
by connecting the SET to GND or a resistor-divider which
receives the feedback voltage of the regulator. The output
the device.
For normal operation, device power dissipation should
voltage set by the resistor-divider is determined by:
R1 

VOUT = 0.8 ⋅  1 +

R2 

be externally limited so that junction temperature will not
exceed 125οC.
Where R1 is connected from VOUT to SET with Kelvin
sensing and R2 is connected from SET to GND. The
Under-Voltage Lock Out (UVLO)
The APL5315 monitors the input voltage to prevent
wrong logic control. The UVLO function initiates a soft-
recommended value of R2 is in the range of 100~100KΩ.
An error amplifier working with a temperature compen-
start process after input voltage exceeds its rising
UVLO threshold during power on. The UVLO function
sated 0.8V reference and an output PMOS regulates the
output to the presetting voltage. The error amplifier
also shuts off the output when the input voltage falls
below it’s falling threshold. Typical UVLO hysteresis
designed with high bandwidth and DC gain provides
very fast transient response and less load regulation.
voltage is 0.8V.
It compares the reference with the feedback voltage and
amplifies the difference to drive the output PMOS which
Shutdown Control
provides load current from VIN to VOUT.
The APL5315 has an active-low shutdown function. Force
SHDN high (>1.6V) enables the VOUT; force SHDN low
Thermal Shutdown
(<0.4V) disables the VOUT. SHDN is internally pulled low
by a resistor (3MΩ typical). If it is not used, connect to VIN
A thermal shutdown circuit limits the junction tempera-
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
for normal operation.
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APL5315
Application Information
Input Capacitor
The APL5315 requires proper input capacitors to supply
Operation Region and Power dissipation
The APL5315 maximum power dissipation depends
surge current during stepping load transients to prevent
the input rail from dropping . Because the parasitic induc-
on the thermal resistance and temperature difference
between the die junction and ambient air. The power dis-
tor from the voltage sources or other bulk capacitors to
the VIN limit the slew rate of the surge current. Place the
sipation PD across the device is:
PD = (TJ - TA) / θJA
Input capacitors near VIN as close as possible. Input
capacitors should be larger than 1µF and a minimum
where (TJ-TA) is the temperature difference between the
junction and ambient air. θ JA is the thermal resistance
ceramic capacitor of 1µF is necessary.
Output Capacitor
between Junction and ambient air. Assuming the
TA=25 oC and maximum TJ=160 oC (typical thermal limit
The APL5315 needs a proper output capacitor to maintain circuit stability and to improve transient response over
threshold), the maximum power dissipation is calculated as:
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
PD(max)=(160-25)/240
= 0.56(W)
than 2.2µF. With X5R and X7R dielectrics, 2.2µF is sufficient at all operating temperatures. Large output capaci-
For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated power
tor value can reduce noise and improve load-transient
response and PSRR, however it also affects power on
dissipation should less than:
issue. Equation (1) shows the relationship between the
maximum COUT value and VOUT.
PD =(125-25)/240
= 0.41(W)

0.1155 
..................(1)
COUT(max) = 87 ⋅  0.55 VOUT 

The GND provides an electrical connection to ground and
channels heat away. Connect the GND to ground by
using a large pad or ground plane.
Where the unit of COUT is µF and VOUT is V. Figure 1 shows
the curve of maximum output capacitor over the output
Layout Considerations
Figure 2 illustrates the layout. Below is a checklist for
voltage. The output voltage range is from 0.8 to 5.5V and
the output capacitor value should be under the line. Out-
yours layout:
1. Please place the input capacitors close to the VIN.
put capacitors must be placed at the load and ground pin
as close as possible and the impedance of the layout
2. Ceramic capacitors for load must be placed near
the load as close as possible.
Output Capacitor (uF)
must be minimized.
3. To place APL5315 and output capacitors near the
load is good for performance.
48
45
4. Large current paths, the bold lines in figure 2,
must have wide tracks.
42
39
5. Divider resistor R1 and R2 must be placed near
36
the SET as close as possible.
33
30
0
1
2
3
4
5
6
Output voltage (V)
Figure 1
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Application Information (Cont.)
PCB Layout Consideration( Cont.)
CIN
APL5315
VIN
VOUT
SET
VIN
3
VOUT
4
5
R1
COUT
GND
2
LOAD
R2
Figure 2
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Package Information
SOT23-5
D
e
E
E1
SEE
VIEW A
b
c
0.25
A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e1
VIEW A
S
Y
M
B
O
L
SOT23-5
INCHES
MILLIMETERS
MIN.
MAX.
A
MAX.
1.45
0.057
0.000
0.006
1.30
0.035
0.051
0.50
0.012
0.020
0.22
0.003
0.009
0.00
0.15
A2
0.90
b
0.30
c
0.08
A1
MIN.
D
2.90 BSC
0.114 BSC
E
2.80 BSC
0.110 BSC
E1
1.60 BSC
0.063 BSC
e
0.95 BSC
0.037 BSC
e1
1.90 BSC
0.075 BSC
L
0.30
0.60
0
0°
8°
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
0.012
0°
12
0.024
8°
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APL5315
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
D1
T2
J
C
A
B
T1
Application
A
178 ±1
SOT-23-5
B
C
J
72 ± 1.0 13.0 + 0.2 2.5 ± 0.15
F
D
D1
Po
3.5 ± 0.05
1.5± 0.1
1.5± 0.1
4.0 ± 0.1
T1
T2
W
P
E
8.4 ± 2
1.5 ± 0.3
8.0 ± 0.3
4 ± 0.1
1.75± 0.1
P1
Ao
Bo
Ko
2.0 ± 0.1 3.15 ± 0.1
3.2± 0.1
t
(mm)
1.4± 0.1 0.2±0.033
Cover Tape Dimensions
Application
Carrier Width
Cover Tape Width
Devices Per Reel
SOT23-5
8
5.3
3000
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material: 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Mar., 2007
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APL5315
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
3
3
Volume mm
≥350
225 +0/-5°C
225 +0/-5°C
Volume mm
<350
240 +0/-5°C
225 +0/-5°C
Package Thickness
<2.5 mm
≥2.5 mm
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Package Thickness
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pao Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
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