OKI MSM5259 40-dot segment driver Datasheet

E2B0019-27-Y2
¡ Semiconductor
MSM5259
¡ Semiconductor
This version: Nov.
1997
MSM5259
Previous version: Mar. 1996
40-DOT SEGMENT DRIVER
GENERAL DESCRIPTION
The MSM5259 is a dot matrix LCD segment driver which is fabricated using low power CMOS
metal gate technology. This LSI consists of 40-bit shift register, 40-bit latch and 40-bit 4-level
driver.
It converts serial data, which is received from an LCD controller LSI, to parallel data and outputs
LCD driving waveforms to LCD.
Expansion of the display can be easily made according to the number and structure of characters.
Since the 40-bit shift register of this device consists of two 20-bit shift registers, it is possible to
allot bits efficiently according to the number of characters.
The MSM5259 can drive a variety of LCD panels because the bias voltage, which determines the
LCD driving voltage, can be optionally supplied from the external source. For static operation
only, the device is available with a power supply voltage of 2.5V or more.
FEATURES
• Supply voltage
•
•
•
•
•
: 3.5 to 6.0V (Dynamic display)
: 2.5 to 6.0V (Static display)
LCD driving voltage : 2.5 to 6.0V (Static display)
Applicable LCD duty : 1/8 to 1/16
Interface with MSM6222-xx (Dot matrix LCD controller with 16-dot common driver and 40dot segment driver)
Bias voltage can be supplied externally.
Package options:
56-pin plastic QFP (QFP56-P-910-0.65-K) (Product name : MSM5259GS-K)
56-pin plastic QFP (QFP56-P-910-0.65-L2) (Product name : MSM5259GS-L2)
56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM5259GS-2K)
56-pin plastic QFP (QFP56-P-910-0.65-2L2) (Product name : MSM5259GS-2L2)
1/18
¡ Semiconductor
MSM5259
BLOCK DIAGRAM
O1 O2
VDD
V2
V3
V5
O19 O20 O21 O22
O39 O40
40-Bit 4-Level Driver
DF
40-Bit Latch
LOAD
VSS
DI1
CP
20-Bit Shift
Register
20-Bit Shift
Register
DO40
DO20 DI21
2/18
¡ Semiconductor
MSM5259
PIN CONFIGURATION
44
43
47
46
45
50
49
48
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
12
31
13
30
14
29
DO40
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
O29
O28
O15
O16
O17
O18
O19
O20
*(VDD)
O21
O22
O23
O24
O25
O26
O27
27
28
3
24
25
26
41
21
22
23
42
2
18
19
20
1
15
16
17
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
53
52
51
56
55
54
NC
NC
NC
DF
LOAD
DI 1
CP
VDD
VSS
V2
V3
V5
DO20
DI 21
(Top View)
NC : No connection
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27
43
28
O15
O16
O17
O18
O19
O20
*(VDD)
O21
O22
O23
O24
O25
O26
O27
DO40
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
O29
O28
37
36
35
34
33
32
31
30
29
56
42
41
40
39
38
NC
NC
NC
DF
LOAD
DI
CP
VDD
VSS
V2
V3
V5
DO20
DI 21
6
7
8
9
10
11
12
13
14
1
2
3
4
5
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
56-Pin Plastic QFP (Type K)
NC : No connection
56-Pin Plastic QFP (Type L)
*
Do not connect pin 21 to the other signal pins, because the pin is internally connected to VDD.
Do not use pin 21 as a single VDD signal line. It is permissible to use pin 21 for supplying a
higher power of VDD.
Note : The figure for Type L shows the configuration viewed from the reverse side of the package.
Pay attention to the difference in pin arrangement.
3/18
¡ Semiconductor
MSM5259
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage (1)
Supply Voltage (2)
Input Voltage
Storage Temperature
Symbol
Condition
VDD
VDD – V5 *1
Ta = 25°C
VI
TSTG
—
Rating
Unit
–0.3 to +6.5
V
0 to +6.5
V
–0.3 to VDD +0.3
V
–55 to +150
°C
Rnage
Unit
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (1)
Supply Voltage (2)
Operating Temperature
Symbol
VDD
VDD – V5 *1
Top
Condition
Dynamic
3.5 to 6.0
Static
2.5 to 6.0
—
2.5 to 6.0
—
–30 to +85
V
*2
V
°C
*1 VDD > V2 > V3 > V5 > VSS (Dynamic display)
VDD = V3 > V2 = V5 = VSS (Static display)
For VDD of less than 3.5V, the device is available only for static operation.
*2 VDD is the reference potential for the LCD driving voltage.
To determine the LCD driving voltage, change the value of V5. (0V Minimum)
4/18
¡ Semiconductor
MSM5259
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD = 5V±10%, Ta=–30 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage
VIH
*1
—
0.8VDD
—
VDD
V
"L" Input Voltage
VIL
*1
—
0
—
0.2VDD
V
"H" Input Current
IIH
*1 VIH = VDD
—
—
1
mA
IIL
*1 VIL = 0V
—
—
–1
mA
"H" Output Voltage
VOH *2 IO = –40mA
4.2
—
—
V
"L" Output Voltage
VOL *2 IO = 0.4mA
—
—
0.4
V
—
—
5
kW
—
—
0.5
mA
"L" Input Current
ON Resistance
RON *3
Supply Current
IDD
VDD–V5= 5V
|VN–VO| = 0.25V
*4
fCP = 0Hz, No load
*1 Applicable to DF, LOAD, DI1 and DI21.
*2 Applicable to DO20 and DO40.
*3 Applicable to O1 to O40.
*4 Dynamic display : VN = VDD to V5, V2 =
2
1
(VDD – V5), V3 =
(VDD – V5)
3
3
Static display : VN = VDD to V5, V3 = VDD, V2 = V5 = VSS
DC Characteristics (2)
(Only for static operation)
(VDD = 3V±0.5V, Ta=–30 to +85°C)
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage
VIH *1
—
0.8VDD
—
VDD
V
"L" Input Voltage
VIL *1
—
"H" Input Current
IIH *1 VIH = VDD
Parameter
Symbol
—
0.2VDD
V
—
1
mA
—
—
–1
mA
"H" Output Voltage
VOH *5 IO = –40mA
2.2
—
—
V
"L" Output Voltage
VOL *5 IO = 0.2mA
—
—
0.4
V
ON Resistance
RON *6
—
—
10
kW
Supply Current
IDD
—
—
0.5
mA
"L" Input Current
IIL *1 VIL = 0V
0
—
V3 = VDD = 3V, V2 = V5 = VSS = 0V,
| VN–VO | = 0.25V
fCP = 0Hz, No load
*5 Applied to DO20 and DO40.
*6 Applied to O1 to O40.
5/18
¡ Semiconductor
MSM5259
Switching Characteristics (1)
(VDD = 5V±10%, Ta=–30 to +85°C, CL=15pF)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H", "L" Propagation Delay Time
tPLH, tPHL
—
—
—
250
ns
fCP
Duty = 50%
—
—
3.3
MHz
Clock Pulse Width
tW (CP)
—
125
—
—
ns
Load Pulse Width
tW (L)
—
125
—
—
ns
Data Set-up Time DI Æ CP
tSETUP
—
50
—
—
ns
Data Hold Time DI Æ CP
tHOLD
—
50
—
—
ns
CP Æ LOAD Set-up Time
tCL
—
250
—
—
ns
LOAD Æ CP Hold Time
tLC
—
0
—
—
ns
tr(CP), tf(CP)
—
—
—
50
ns
tr(L), tf(L)
—
—
—
1
ms
Clock Frequency
CP Rise/Fall Time
LOAD Rise/Fall Time
Switching Characteristics (2)
(VDD = 3V±0.5V, Ta=–30 to +85°C, CL=15pF)
(Only for static operation)
Parameter
Symbol
"H", "L" Propagation Delay Time
tPLH, tPHL
—
fCP
Duty = 50%
Clock Pulse Width
tW (CP)
—
Load Pulse Width
tW (L)
—
DI Æ CP Set-up Time
tSETUP
DI Æ CP Hold Time
tHOLD
CP Æ LOAD Set-up Time
LOAD Æ CP Hold Time
Clock Frequency
CP Rise/Fall Time
LOAD Rise/Fall Time
Condition
Min.
Typ.
Max.
Unit
—
—
800
ns
—
—
1.0
MHz
300
—
—
ns
300
—
—
ns
—
200
—
—
ns
—
200
—
—
ns
tCL
—
800
—
—
ns
tLC
—
0
—
—
ns
tr(CP)
—
—
—
1
ms
tr(L), tf(L)
—
—
—
1
ms
6/18
¡ Semiconductor
MSM5259
tf(CP)
tw(CP)
0.8VDD
CP
tr(CP)
tw(CP)
tSETUP
0.2VDD
DI21
0.2VDD
0.2VDD
tSETUP
tHOLD
DI1
0.8VDD
0.8VDD
0.8VDD
tHOLD
0.8
VDD
0.2
VDD
0.8VDD 0.8VDD
0.2VDD 0.2VDD
0.8
VDD
0.2
VDD
tPLH
tPHL
DO20
0.8VDD
0.2VDD
DO40
tCL
tLC
0.8VDD
LOAD
0.2VDD
tr(L)
0.8VDD
0.2VDD
tw(L)
tf(L)
7/18
¡ Semiconductor
MSM5259
TIMING DIAGRAM
1/5 bias, 1/16 duty
Frame
signal
16
1
2
3
H
L
H
L
16
1
2
3
H
L
H
H
LOAD
LATCH
DATA
DF
DF
LOAD
DI
CP
LATCH
DATA
LOAD
LATCH
DATA
L
DF
VDD
Va
Vb
Vc
Vd
Ve
VLCD
VDD
VDD
R
Va
1
Va = VDD – –5 VLCD
MSM5259
R
V2
Vb
2
R
V3
VLCD
Vc
R
R
V5
3
Vc = VDD – –5 VLCD
Vd
Ve
Vb = VDD – –5 VLCD
4
Vd = VDD – –5 VLCD
Ve = VDD – VLCD
VLCD = LCD driving voltage
VR
Vss
8/18
¡ Semiconductor
MSM5259
Static Display
VDD
DF
VSS
VDD, V3
Output (lighting on)
VSS, V5, V2
VDD, V3
Output (lighting off)
VSS, V5, V2
VDD
VDD
V2
O1
V3
V5
O40
VSS
DF
Common signal
Bias supply pin
9/18
¡ Semiconductor
MSM5259
FUNCTIONAL DESCRIPTION
Pin Functional Description
• DI1
The data (1st to 20th bit) from the LCD controller LSI is input to 20-bit shift register from DI1.
(Positive logic)
• DI21
Data input to the shift register (21st to 41st bit).
Connecting DO20 and DI21 allows configuration of a 40-bit register.
If DI21 is not used, connect this pin to VSS.
• CP
Clock pulse input pin for the two 20-bit shift registers. The data is input to the 20-bit shift
register at the falling edge of the clock pulse. A data set up time (tSETUP) and data hold time
(tHOLD) are required between the DI1 and DI21 signals and a clock pulse.
• DO20
20th bit of the shift register contents is output from DO20. The data which was input from DI1
is output from this pin with a delay of the number of bits of the shift register (20), synchronized
with the clock pulse. By connecting DO20 to DI21, two 20-bit shift registers can be used as a
40-bit shift register.
• DO40
40th bit of the shift register contents is output from DO40. The data which was input from DI21
is output from this pin with a delay of the number of bits of the shift register (20), synchronized
with the clock pulse. By connecting DO40 to the next MSM5259’s DI1, this LSI is applicable
to a wide screen LCD.
Refer to the application circuit.
• DF
Alternate signal input pin for LCD driving.
• LOAD
Signal for latching the shift register contents is input from this pin. When the LOAD pin is
set at "H" level, the shift register contents are transferred to the 40-bit 4-level driver. When
LOAD pin is set at "L" level, the last display output data (O1 - O40), which was transferred
when LOAD pin was at "H" level, is held.
• VDD, VSS
Supply voltage pins.
VDD is generally set to 4.0 to 6.0V. VSS is a ground pin (VSS = 0V)
• V2, V3, V5
Bias supply voltage pins to drive the LCD. Bias voltage divided by the register is usually used
as supply voltage source.
Refer to the application circuit.
For static operation, connect V3 to VDD and also connect V2, V5, to VSS.
10/18
¡ Semiconductor
MSM5259
• O1 to O40
Display data output pin which corresponds to each data bit in the latch. One of VDD, V2, V3
and V5 is selected as a display driving voltage source according to the combination of latched
data level and DF signal. (Refer to the truth table below.)
Truth Table
Latched data
DF
Driver output level
"H"
(Select)
H
V5
L
VDD
"L"
(Non-select)
H
V3
L
V2
11/18
¡ Semiconductor
MSM5259
LCD Driving Waveform (1/5 bias, 1/16 duty)
Common
O1
O2
O3
O4
O5
O6
O7
O8
O1
O9
O10
O11
O12
O13
O14
O15
O16
O2
O1
O1 O2 O3 O4 O5
VDD
Va
Vb
Vc
Vd
Ve
1
2
3
4
16
1
VLCD
VDD
Va
Vb
Vc
Vd
Ve
VDD
Va
Vb
Vc
Vd
Ve
Segment
Va = VDD –
Vb = VDD –
Vc = VDD –
Vd = VDD –
1
–
5
2
–
5
3
–
5
4
–
5
VLCD
VLCD
O2
VLCD
VLCD
VDD
Va
Vb
Vc
Vd
Ve
VLCD
Ve = VDD – VLCD
Common O1-Segment O1
(Select waveform)
1
5
O
1
– –5 VLCD
– VLCD
–VLCD
VLCD
3
5
O
– VLCD
1
5
– VLCD
Common O2-Segment O1
(Non-select waveform)
1
– –5 VLCD
3
– –5 VLCD
–VLCD
1 frame
12/18
O1-O40
O1-O40
DO
DO40
DI1
CP MSM5259 DO20
DI21
LOAD
DF
VDD VSS V2 V3 V5
DO40
DI1
CP MSM5259 DO20
DI21
LOAD
DF
VDD VSS V2 V3 V5
DO40
DI1
CP MSM5259 DO20
DI21
LOAD
DF
VDD VSS V2 V3 V5
MSM6222B-01
CP
L
DF
VDD
GND
V1
V2
V3
V4
V5
R
R
C
R
C
R
C
C
OV
13/18
+5V
MSM5259
C
R
¡ Semiconductor
O1-O40
SEG 1-40
APPLICATION CIRCUITS
COM 1-16
(Connected to MSM6222B-01 LCD Controller)
LCD
COM
Seg40
Seg1
Seg41
Seg80
COM
MSM4069
32-120HZ
Duty 50%
COMMON
SIGNAL
DATA IN
SHIFT
CLOCK
+5V
O1
VDD
V2
V3
V5
DF
LOAD
DI1
CP
VSS(GND)
O40
O1
VDD
V2
V3
V5
DF
LOAD
MSM5259
DO40
DO20 DI21
+5V
DI1
CP
VSS(GND)
¡ Semiconductor
80-DOT LCD PANEL
Application Circuit for Static Display
The MSM5259 is applicable to a static LCD by setting V2 and V5 at ground level, connecting V3 to VDD and
inputting COMMON SIGNAL to DF pin.
This sample application circuit below is the case when the MSM5259 is applied to an 80-bit LCD panel by connecting
two MSM5259s in series.
O40
MSM5259
DO20 DI21
LOAD
MSM5259
14/18
¡ Semiconductor
MSM5259
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.36 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/18
¡ Semiconductor
MSM5259
(Unit : mm)
QFP56-P-910-0.65-L2
Spherical surface
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.36 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/18
¡ Semiconductor
MSM5259
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.43 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/18
¡ Semiconductor
MSM5259
(Unit : mm)
QFP56-P-910-0.65-2L2
Spherical surface
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.43 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
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