Fujitsu MBM29DL164BE70PBT 16m (2m x 8/1m x 16) bit dual operation Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20874-4E
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
Dual Operation
MBM29DL16XTD/BD -70/90/12
■ FEATURES
• 0.33 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29DL16XTD/MBM29DL16XBD
VCC = 3.3 V
+0.3 V
–0.3 V
70
—
—
VCC = 3.0 V
+0.6 V
–0.3 V
—
90
12
Max. Address Access Time (ns)
70
90
120
Max. CE Access Time (ns)
70
90
120
Max. OE Access Time (ns)
30
35
50
Ordering Part No.
■ PACKAGES
48-pin plastic TSOP (I)
48-pin plastic TSOP (I)
48-pin plastic FBGA
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
(BGA-48P-M13)
MBM29DL16XTD/BD-70/90/12
(Continued)
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
Eight 4K word and thirty one 32K word sectors in word mode
Eight 8K byte and thirty one 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
2
MBM29DL16XTD/BD-70/90/12
■ GENERAL DESCRIPTION
The MBM29DL16XTD/BD are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.
These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V
VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in
standard EPROM programmers.
MBM29DL16XTD/BD are organized into two banks, Bank 1 and Bank 2, which can be considered to be two
separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is
simultaneously taking place on the other bank.
In the MBM29DL16XTD/BD, a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL16XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/15.5 Mb, 2 Mb/14 Mb, 4 Mb/12 Mb, 8 Mb/8 Mb.
The standard MBM29DL16XTD/BD offer access times 70 ns, 90 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29DL16XTD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29DL16XTD/BD are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL16XTD/BD are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL16XTD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29DL16XTD/BD-70/90/12
Table 1
Device
Part Number
Organization
MBM29DL16XTD/BD Device Bank Divisions
Bank 1
Megabits
Sector Sizes
Megabits
Sector Sizes
MBM29DL161TD/BD
0.5 Mbit
Eight 8K byte/4K word
15.5 Mbit
Thirty-one
64K byte/32K word
MBM29DL162TD/BD
2 Mbit
Eight 8K byte/4K word,
three 64K byte/32K word
14 Mbit
Twenty-eight
64K byte/32K word
MBM29DL163TD/BD
4 Mbit
Eight 8K byte/4K word,
seven 64K byte/32K word
12 Mbit
Twenty-four
64K byte/32K word
MBM29DL164TD/BD
8 Mbit
Eight 8K byte/4K word,
fifteen 64K byte/32K word
8 Mbit
Sixteen
64K byte/32K word
× 8/× 16
4
Bank 2
MBM29DL16XTD/BD-70/90/12
■ PIN ASSIGNMENTS
TSOP(I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
N.C.
WE
RESET
N.C.
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
Standard Pinout
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ 15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
FPT-48P-M19
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
WP/ACC
N.C.
RESET
WE
N.C.
A19
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Pinout
FPT-48P-M20
(Continued)
5
MBM29DL16XTD/BD-70/90/12
(Continued)
FBGA
(TOP VIEW)
Marking side
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
(BGA-48P-M13)
6
A1
A3
A2
A7
A3
RY/BY
B1
A4
B2
A17
B3
C1
A2
C2
A6
D1
A1
D2
E1
A0
F1
A4
WE
A5
A9
A6
A13
WP/ACC B4
RESET
B5
A8
B6
A12
C3
A18
C4
N.C.
C5
A10
C6
A14
A5
D3
N.C.
D4
A19
D5
A11
D6
A15
E2
DQ0
E3
DQ2
E4
DQ5
E5
DQ7
E6
A16
CE
F2
DQ8
F3
DQ10
F4
DQ12
F5
DQ14
F6
BYTE
G1
OE
G2
DQ9
G3
DQ11
G4
VCC
G5
DQ13
G6
DQ15/A-1
H1
VSS
H2
DQ1
H3
DQ3
H4
DQ4
H5
DQ6
H6
VSS
MBM29DL16XTD/BD-70/90/12
■ BLOCK DIAGRAM
V CC
Cell Matrix
Bank 2 Address
A0 to A19
(A-1)
(Bank 2)
Y-Gating & Data Latch
V SS
X-Decoder
RY/BY
State
Control
&
Command
Register
Status
DQ 0 to DQ 15
Control
X-Decoder
Bank 1 Address
Cell Matrix
(Bank 1)
Y-Gating &
Data Latch
RESET
WE
CE
OE
BYTE
WP/ACC
DQ 0 to DQ 15
7
MBM29DL16XTD/BD-70/90/12
■ LOGIC SYMBOL
Table 2 MBM29DL16XTD/BD Pin Configuration
Pin
A-1
20
A0 to A19
16 or 8
DQ 0 to DQ 15
CE
Function
A-1, A0 to A19
Address Inputs
DQ0 to DQ15
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
OE
WE
RESET
BYTE
WP/ACC
RY/BY
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector
Group Unprotection
BYTE
WP/ACC
8
Selects 8-bit or 16-bit mode
Hardware Write Protection/Program
Acceleration
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
MBM29DL16XTD/BD-70/90/12
■ DEVICE BUS OPERATION
Table 3 MBM29DL16XTD/BD User Bus Operations (BYTE = VIH)
Operation
CE OE WE
A0
A1
A6
A9
DQ0 to DQ15 RESET WP/ACC
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
VID
Code
H
X
Auto-Select Device Code (1)
L
L
H
H
L
L
VID
Code
H
X
Read (3)
L
L
H
A0
A1
A6
A9
DOUT
H
X
Standby
H
X
X
X
X
X
X
HIGH-Z
H
X
Output Disable
L
H
H
X
X
X
X
HIGH-Z
H
X
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
DIN
H
X
Enable Sector Group Protection (2), (4)
L
VID
L
H
L
VID
X
H
X
Verify Sector Group Protection (2), (4)
L
L
H
L
H
L
VID
Code
H
X
Temporary Sector Group Unprotection (5)
X
X
X
X
X
X
X
X
VID
X
Reset (Hardware)/Standby
X
X
X
X
X
X
X
HIGH-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
L
Table 4 MBM29DL16XTD/BD User Bus Operations (BYTE = VIL)
Operation
15/
CE OE WE DQ
A-1 A0
A1
A6
A9
DQ0 to DQ7 RESET WP/ACC
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
L
VID
Code
H
X
Auto-Select Device Code (1)
L
L
H
L
H
L
L
VID
Code
H
X
Read (3)
L
L
H
A-1
A0
A1
A6
A9
DOUT
H
X
Standby
H
X
X
X
X
X
X
X
HIGH-Z
H
X
Output Disable
L
H
H
X
X
X
X
X
HIGH-Z
H
X
Write (Program/Erase)
L
H
L
A-1
A0
A1
A6
A9
DIN
H
X
Enable Sector Group Protection
(2), (4)
L
VID
L
L
H
L
VID
X
H
X
Verify Sector Group Protection
(2), (4)
L
L
H
L
L
H
L
VID
Code
H
X
Temporary Sector Group
Unprotection (5)
X
X
X
X
X
X
X
X
X
VID
X
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
HIGH-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 12.
2. Refer to the section on Sector Group Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 3.3 V ± 10%
5. It is also used for the extended sector group protection.
9
MBM29DL16XTD/BD-70/90/12
■ ABSOLUTE MAXIMUM RATINGS(See WARNING)
Parameter
Symbol
Conditions
Tstg
Ambient Temperature with
Power Applied
Voltage with respect to
Ground All pins except A9,
OE, RESET (Note 1)
Rating
Unit
Min.
Max.

–55
+125
°C
TA

–40
+85
°C
VIN, VOUT

–0.5
VCC+0.5
V
Power Supply Voltage
(Note 1)
VCC

–0.5
+4.0
V
A9, OE, and RESET
(Note 2)
VIN

–0.5
+13.0
V
WP/ACC (Note 3)
VIN

–0.5
+10.5
V
Storage Temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
up to 20 ns. when VCC is applied.
3. Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may
negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin
iis when Vcc is applied.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Ambient Temperature
TA
Power Supply Voltage
VCC
Conditions
Value
Unit
Min.
Max.
MBM29DL16XTD/BD-70
–20
+70
°C
MBM29DL16XTD/BD-90/12
–40
+85
°C
MBM29DL16XTD/BD-70
+3.0
+3.6
V
MBM29DL16XTD/BD-90/12
+2.7
+3.6
V
Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
10
MBM29DL16XTD/BD-70/90/12
■ MAXIMUM OVERSHOOT
+0.6 V
20 ns
20 ns
–0.5 V
–2.0 V
20 ns
Figure 1 Maximum Negative Overshoot Waveform
20 ns
V CC +2.0 V
V CC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
V CC +0.5 V
20 ns
20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
11
MBM29DL16XTD/BD-70/90/12
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Value
Conditions
Min.
Max.
Unit
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
A9, OE, RESET Inputs Leakage
Current
ILIT
VCC = VCC Max.
A9, OE, RESET = 12.5 V
—
35
µA
CE = VIL, OE = VIH,
f = 5 MHz
VCC Active Current (Note 1)
ICC1
CE = VIL, OE = VIH,
f = 1 MHz
Byte
Word
Byte
Word
—
—
13
mA
15
7
mA
7
VCC Active Current (Note 2)
ICC2
CE = VIL, OE = VIH
—
35
mA
VCC Current (Standby)
ICC3
VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
—
5
µA
VCC Current (Standby, Reset)
ICC4
VCC = VCC Max., WP/ACC= VCC±
0.3 V, RESET = VSS ± 0.3 V
—
5
µA
VCC Current
(Automatic Sleep Mode) (Note 3)
ICC5
VCC = VCC Max., CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V
VIN = VCC ± 0.3 V or VSS ± 0.3 V
—
5
µA
VCC Active Current (Note 5)
(Read-While-Program)
ICC6
CE = VIL, OE = VIH
Byte
—
48
Word
—
50
VCC Active Current (Note 5)
(Read-While-Erase)
ICC7
CE = VIL, OE = VIH
Byte
—
48
Word
—
50
VCC Active Current
(Erase-Suspend-Program)
ICC8
CE = VIL, OE = VIH
—
35
mA
ACC Accelerated Program
Current
IACC
VCC = VCC Max.
WP/ACC = VACC Max.
—
20
mA
Input Low Level
VIL
—
–0.5
0.6
V
Input High Level
VIH
—
2.0
VCC+0.3
V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration
VACC
—
8.5
9.5
V
Voltage for Autoselect and Sector
Protection (A9, OE, RESET)
(Note 4)
VID
—
11.5
12.5
V
mA
mA
(Continued)
Notes: 1.
2.
3.
4.
5.
12
The ICC current listed includes both the DC operating current and the frequency dependent component.
ICC active while Embedded Algorithm (program or erase) is in progress.
Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
Applicable for only VCC applying.
Embedded Algorithm (program or erase) is in progress. (@5 MHz)
MBM29DL16XTD/BD-70/90/12
(Continued)
Parameter
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
Notes: 1.
2.
3.
4.
5.
Symbol
Conditions
Value
Min.
Max.
Unit
VOL
IOL = 4.0 mA, VCC = VCC Min.
—
0.45
V
VOH1
IOH = –2.0 mA, VCC = VCC Min.
2.4
—
V
VOH2
IOH = –100 µA
VCC–0.4
—
V
2.3
2.5
V
VLKO
—
The ICC current listed includes both the DC operating current and the frequency dependent component.
ICC active while Embedded Algorithm (program or erase) is in progress.
Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
Applicable for only VCC applying.
Embedded Algorithm (program or erase) is in progress. (@5 MHz)
13
MBM29DL16XTD/BD-70/90/12
2. AC Characteristics
• Read Only Operations Characteristics
Parameter
Symbols
Description
70
(Note)
90
(Note)
12
(Note)
Unit
Min.
70
90
120
ns
Test Setup
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
CE = VIL
Max.
OE = VIL
70
90
120
ns
tELQV
tCE
Chip Enable to Output Delay
OE = VIL Max.
70
90
120
ns
tGLQV
tOE
Output Enable to Output Delay
—
Max.
30
35
50
ns
tEHQZ
tDF
Chip Enable to Output High-Z
—
Max.
25
30
30
ns
tGHQZ
tDF
Output Enable to Output High-Z
—
Max.
25
30
30
ns
tAXQX
tOH
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
—
Min.
0
0
0
ns
—
tREADY
RESET Pin Low to Read Mode
—
Max.
20
20
20
µs
—
tELFL
tELFH
CE or BYTE Switching Low or High
—
Max.
5
5
5
ns
—
Note: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29DL16XTD/BD-70)
1 TTL gate and 100 pF (MBM29DL16XTD/BD-90/12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Figure 4 Test Conditions
14
MBM29DL16XTD/BD-70/90/12
• Write/Erase/Program Operations
Parameter Symbols
Description
70
90
12
Unit
Min.
70
90
120
ns
Address Setup Time
Min.
0
0
0
ns
tASO
Address Setup Time to OE Low During
Toggle Bit Polling
Min.
12
15
15
ns
tWLAX
tAH
Address Hold Time
Min.
45
45
50
ns
—
tAHT
Address Hold Time from CE or OE High
During Toggle Bit Polling
Min.
0
0
0
ns
tDVWH
tDS
Data Setup Time
Min.
30
35
50
ns
tWHDX
tDH
Data Hold Time
Min.
0
0
0
ns
Min.
0
0
0
ns
tOEH
Output Enable
Hold Time
Read
—
Toggle and Data Polling
Min.
10
10
10
ns
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
—
—
tCEPH
CE High During Toggle Bit Polling
Min.
20
20
20
ns
—
tOEPH
OE High During Toggle Bit Polling
Min.
20
20
20
ns
tGHWL
tGHWL
Read Recover Time Before Write
Min.
0
0
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
Min.
0
0
0
ns
tELWL
tCS
CE Setup Time
Min.
0
0
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
0
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
0
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
0
0
ns
tWLWH
tWP
Write Pulse Width
Min.
35
35
50
ns
tELEH
tCP
CE Pulse Width
Min.
35
35
50
ns
tWHWL
tWPH
Write Pulse Width High
Min.
25
30
30
ns
tEHEL
tCPH
CE Pulse Width High
Min.
25
30
30
ns
tWHWH1
tWHWH1
Byte Programming Operation
Typ.
8
8
8
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
Typ.
1
1
1
sec
—
tVCS
VCC Setup Time
Min.
50
50
50
µs
—
tVIDR
Rise Time to VID (Note 2)
Min.
500
500
500
ns
—
tVACCR
Rise Time to VACC (Note 2)
Min.
500
500
500
ns
—
tVLHT
Voltage Transition Time (Note 2)
Min.
4
4
4
µs
—
tWPP
Write Pulse Width (Note 2)
Min.
100
100
100
µs
—
tOESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
4
µs
(Continued)
15
MBM29DL16XTD/BD-70/90/12
(Continued)
Parameter Symbols
Description
70
90
12
Unit
Min.
4
4
4
µs
Recover Time From RY/BY
Min.
0
0
0
ns
tRP
RESET Pulse Width
Min.
500
500
500
ns
—
tRH
RESET High Level Period before Read
Min.
200
200
200
ns
—
tFLQZ
BYTE Switching Low to Output High-Z
Max.
30
30
40
ns
—
tFHQV
BYTE Switching High to Output Active
Max.
70
90
120
ns
—
tBUSY
Program/Erase Valid to RY/BY Delay
Max.
90
90
90
ns
—
tEOE
Delay Time from Embedded Output Enable Max.
70
90
120
ns
—
tTOW
Erase Time-out Time
Min.
50
50
50
µs
—
tSPD
Erase Suspend Transition Time
Max.
20
20
20
µs
JEDEC
Standard
—
tCSP
CE Setup Time to WE Active (Note 2)
—
tRB
—
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Group Protection operation.
16
MBM29DL16XTD/BD-70/90/12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min.
Typ.
Max.
Sector Erase Time
—
1
10
sec
Word Programming Time
—
16
360
µs
Byte Programming Time
—
8
300
µs
Chip Programming Time
—
—
50
sec
100,000
—
—
cycles
Program/Erase Cycle
Excludes programming time
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead
—
■ PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
6
7.5
pF
8.5
12
pF
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
8
10
pF
CIN3
WP/ACC Pin Capacitance
VIN = 0
17
18
pF
Note: Test conditions TA = 25°C, f = 1.0 MHzs
17
MBM29DL16XTD/BD-70/90/12
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
t RC
Addresses
Addresses Stable
t ACC
CE
t OE
t DF
OE
t OEH
WE
t OH
t CE
Outputs
High-Z
Output Valid
Figure 5.1 AC Waveforms for Read Operations
18
High-Z
MBM29DL16XTD/BD-70/90/12
t RC
Addresses
Addresses Stable
t ACC
CE
t RH
t
RP
t
RH
t
CE
RESET
t OH
Outputs
High-Z
Output Valid
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
19
MBM29DL16XTD/BD-70/90/12
Data Polling
3rd Bus Cycle
Addresses
555H
t WC
PA
t AS
PA
t RC
t AH
CE
t CH
t CS
t CE
OE
t GHWL
t WP
t WPH
t OE
t WHWH1
WE
t OH
t DS
t DH
A0H
Data
Notes: 1.
2.
3.
4.
5.
6.
PD
DQ 7
D OUT
D OUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
20
MBM29DL16XTD/BD-70/90/12
3rd Bus Cycle
Addresses
Data Polling
PA
555H
t WC
t AS
PA
t AH
WE
t WS
t WH
OE
t GHEL
t CP
t CPH
t WHWH1
CE
t DS
t DH
Data
Notes: 1.
2.
3.
4.
5.
6.
A0H
PD
DQ 7
D OUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
21
MBM29DL16XTD/BD-70/90/12
Addresses
2AAH
555H
t WC
t AS
555H
555H
2AAH
SA *
t AH
CE
t CS
t CH
OE
t GHWL
t WP
t WPH
WE
t DS
AAH
Data
t DH
55H
80H
AAH
55H
10H/
30H
t VCS
V CC
*
SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase.
Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 8 AC Waveforms for Chip/Sector Erase Operations
22
MBM29DL16XTD/BD-70/90/12
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
DQ7
Data
DQ7 =
Valid Data
DQ7
High-Z
t WHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag
t BUSY
DQ0 to DQ6
Valid Data
High-Z
t EOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation).
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
23
MBM29DL16XTD/BD-70/90/12
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
Output
Valid
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
24
MBM29DL16XTD/BD-70/90/12
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA2
(PA)
BA1
BA2
(PA)
BA2
(555H)
BA1
tAS
BA1
tACC
tAH
tAS
tAHT
tCE
CE
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
Valid
Output
DQ
tDH
Valid
Intput
(A0H)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
Figure 11 Bank-to-bank Read/Write Timing Diagram
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE or CE
Note: DQ2 is read from the erase-suspended sector.
Figure 12 DQ2 vs. DQ6
25
MBM29DL16XTD/BD-70/90/12
CE
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
t BUSY
Figure 13 RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
t RB
RY/BY
tREADY
Figure 14 RESET, RY/BY Timing Diagram
26
MBM29DL16XTD/BD-70/90/12
CE
tCE
BYTE
Data Output
(DQ0 to DQ7)
DQ0 to DQ14
tELFH
DQ15/A-1
Data Output
(DQ0 to DQ14)
tFHQV
DQ15
A-1
Figure 15 Timing Diagram for Word Mode Configuration
CE
BYTE
DQ0 to DQ14
tELFL
Data Output
(DQ0 to DQ7)
Data Output
(DQ0 to DQ14)
tACC
DQ15/A-1
DQ15
A-1
tFLQZ
Figure 16 Timing Diagram for Byte Mode Configuration
The falling edge of the last write signal
CE or WE
Input
Valid
BYTE
tSET
(tAS)
tHOLD (tAH)
Figure 17 BYTE Timing Diagram for Write Operations
27
MBM29DL16XTD/BD-70/90/12
A19, A18, A17
A16, A15, A14
A13, A12
SGAX
SGAY
A0
A1
A6
VID
3V
A9
t VLHT
VID
3V
OE
t VLHT
t VLHT
t VLHT
t WPP
WE
t OESP
t CSP
CE
Data
01H
t VCS
t OE
VCC
SGAX : Sector Group Address for initial sector
SGAY : Sector Group Address for next sector
Note: A-1 is VIL on byte mode.
Figure 18 AC Waveforms for Sector Group Protection
28
MBM29DL16XTD/BD-70/90/12
VCC
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
Figure 19 Temporary Sector Group Unprotection Timing Diagram
29
MBM29DL16XTD/BD-70/90/12
VCC
tVCS
tVLHT
RESET
tVIDR
tWC
Add
tWC
SGAX
SGAX
SGAY
A0
A1
A6
CE
OE
TIME-OUT
tWP
WE
Data
60H
60H
40H
01H
tOE
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (min)
Figure 20 Extended Sector Group Protection Timing Diagram
30
60H
MBM29DL16XTD/BD-70/90/12
VCC
tVACCR
tVCS
tVLHT
VACC
3V
3V
WP/ACC
CE
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Acceleration period
Figure 21 Accelerated Program Timing Diagram
31
MBM29DL16XTD/BD-70/90/12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
Table 5.1 Sector Address Tables (MBM29DL161TD)
Bank Sector
Bank 2
Bank 1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Sector Address
Sector
Size
(×8)
(×16)
Bank Address
(Kbytes/
Address Range
Address Range
A19 A18 A17 A16 A15 A14 A13 A12 Kwords)
0
0
0
0
0 X X X
64/32
000000H to 00FFFFH 000000H to 007FFFH
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
1
0
0
0
1 X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
1
1
1
1
1
0
0
0
8/4
1F0000H to 1F1FFFH 0F8000H to 0F8FFFH
1
1
1
1
1
0
0
1
8/4
1F2000H to 1F3FFFH 0F9000H to 0F9FFFH
1
1
1
1
1
0
1
0
8/4
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH
1
1
1
1
1
0
1
1
8/4
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH
1
1
1
1
1
1
0
0
8/4
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH
1
1
1
1
1
1
0
1
8/4
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH
1
1
1
1
1
1
1
0
8/4
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH
1
1
1
1
1
1
1
1
8/4
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH)
32
MBM29DL16XTD/BD-70/90/12
Table 5.2 Sector Address Tables (MBM29DL161BD)
Bank Sector
Bank 2
Bank 1
SA38
SA37
SA36
SA35
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Sector Address
Sector
(×8)
(×16)
Size
Bank Address
(Kbytes/
Address Range
Address Range
A19 A18 A17 A16 A15 A14 A13 A12 Kwords)
1
1
1
1
1 X X X
64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
1
0
0
0 X X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
0
0
0
0
0
1
1
1
8/4
00E000H to 00FFFFH 007000H to 007FFFH
0
0
0
0
0
1
1
0
8/4
00C000H to 00DFFFH 006000H to 006FFFH
0
0
0
0
0
1
0
1
8/4
00A000H to 00BFFFH 005000H to 005FFFH
0
0
0
0
0
1
0
0
8/4
008000H to 009FFFH 004000H to 004FFFH
0
0
0
0
0
0
1
1
8/4
006000H to 007FFFH 003000H to 003FFFH
0
0
0
0
0
0
1
0
8/4
004000H to 005FFFH 002000H to 002FFFH
0
0
0
0
0
0
0
1
8/4
002000H to 003FFFH 001000H to 001FFFH
0
0
0
0
0
0
0
0
8/4
000000H to 001FFFH 000000H to 000FFFH
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH).
33
MBM29DL16XTD/BD-70/90/12
Table 6.1 Sector Address Tables (MBM29DL162TD)
Bank Sector
Bank 2
Bank 1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Sector Address
Sector
Size
Bank
(×8)
(×16)
(Kbytes/
Address
Address Range
Address Range
Kwords)
A19 A18 A17 A16 A15 A14 A13 A12
0
0
0
0
0 X X X
64/32
000000H to 00FFFFH 000000H to 007FFFH
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
1
0
0
0
1 X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
1
1
1
1
1
0
0
0
8/4
1F0000H to 1F1FFFH 0F8000H to 0F8FFFH
1
1
1
1
1
0
0
1
8/4
1F2000H to 1F3FFFH 0F9000H to 0F9FFFH
1
1
1
1
1
0
1
0
8/4
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH
1
1
1
1
1
0
1
1
8/4
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH
1
1
1
1
1
1
0
0
8/4
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH
1
1
1
1
1
1
0
1
8/4
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH
1
1
1
1
1
1
1
0
8/4
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH
1
1
1
1
1
1
1
1
8/4
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH)
34
MBM29DL16XTD/BD-70/90/12
Table 6.2 Sector Address Tables (MBM29DL162BD)
Bank Sector
Bank 2
Bank 1
SA38
SA37
SA36
SA35
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Sector Address
Sector
Bank
(×8)
(×16)
Size
(Kbytes/
Address
Address Range
Address Range
Kwords)
A19 A18 A17 A16 A15 A14 A13 A12
1
1
1
1
1 X X X
64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
1
0
0
0 X X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
0
0
0
0
0
1
1
1
8/4
00E000H to 00FFFFH 007000H to 007FFFH
0
0
0
0
0
1
1
0
8/4
00C000H to 00DFFFH 006000H to 006FFFH
0
0
0
0
0
1
0
1
8/4
00A000H to 00BFFFH 005000H to 005FFFH
0
0
0
0
0
1
0
0
8/4
008000H to 009FFFH 004000H to 004FFFH
0
0
0
0
0
0
1
1
8/4
006000H to 007FFFH 003000H to 003FFFH
0
0
0
0
0
0
1
0
8/4
004000H to 005FFFH 002000H to 002FFFH
0
0
0
0
0
0
0
1
8/4
002000H to 003FFFH 001000H to 001FFFH
0
0
0
0
0
0
0
0
8/4
000000H to 001FFFH 000000H to 000FFFH
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH).
35
MBM29DL16XTD/BD-70/90/12
Table 7.1 Sector Address Tables (MBM29DL163TD)
Bank Sector
Bank 2
Bank 1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Sector Address
Sector
Size
(×8)
(×16)
BA
(Kbytes/
Address Range
Address Range
A19 A18 A17 A16 A15 A14 A13 A12 Kwords)
0
0
0
0
0 X X X
64/32
000000H to 00FFFFH 000000H to 007FFFH
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
1
0
0
0
1 X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
1
1
1
1
1
0
0
0
8/4
1F0000H to 1F1FFFH 0F8000H to 0F8FFFH
1
1
1
1
1
0
0
1
8/4
1F2000H to 1F3FFFH 0F9000H to 0F9FFFH
1
1
1
1
1
0
1
0
8/4
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH
1
1
1
1
1
0
1
1
8/4
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH
1
1
1
1
1
1
0
0
8/4
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH
1
1
1
1
1
1
0
1
8/4
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH
1
1
1
1
1
1
1
0
8/4
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH
1
1
1
1
1
1
1
1
8/4
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH
BA: Bank Address
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH)
36
MBM29DL16XTD/BD-70/90/12
Table 7.2 Sector Address Tables (MBM29DL163BD)
Bank Sector
Bank 2
Bank 1
SA38
SA37
SA36
SA35
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Sector Address
Sector
(×8)
(×16)
Size
BA
(Kbytes/
Address Range
Address Range
A19 A18 A17 A16 A15 A14 A13 A12 Kwords)
1
1
1
1
1 X X X
64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
1
0
0
0 X X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
0
0
0
0
0
1
1
1
8/4
00E000H to 00FFFFH 007000H to 007FFFH
0
0
0
0
0
1
1
0
8/4
00C000H to 00DFFFH 006000H to 006FFFH
0
0
0
0
0
1
0
1
8/4
00A000H to 00BFFFH 005000H to 005FFFH
0
0
0
0
0
1
0
0
8/4
008000H to 009FFFH 004000H to 004FFFH
0
0
0
0
0
0
1
1
8/4
006000H to 007FFFH 003000H to 003FFFH
0
0
0
0
0
0
1
0
8/4
004000H to 005FFFH 002000H to 002FFFH
0
0
0
0
0
0
0
1
8/4
002000H to 003FFFH 001000H to 001FFFH
0
0
0
0
0
0
0
0
8/4
000000H to 001FFFH 000000H to 000FFFH
BA: Bank Address
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH).
37
MBM29DL16XTD/BD-70/90/12
Table 8.1 Sector Address Tables (MBM29DL164TD)
Sector Address
Sector
Size
(×8)
(×16)
Bank Sector BA
(Kbytes/
Address Range
Address Range
A19 A18 A17 A16 A15 A14 A13 A12 Kwords)
SA0
0
0
0
0
0 X X X
64/32
000000H to 00FFFFH 000000H to 007FFFH
SA1
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
SA2
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
SA3
0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
SA4
0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
SA5
0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
SA6
0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
SA7
0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
Bank 2
SA8
0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
SA9
0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
SA10 0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA11 0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA12 0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
SA13 0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
SA14 0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA15 0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA16 1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
SA17 1
0
0
0
1 X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
SA18 1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
SA19 1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
SA20 1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
SA21 1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
SA22 1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
SA23 1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
SA24 1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25 1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26 1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
Bank 1 SA27 1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28 1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29 1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30 1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31 1
1
1
1
1
0
0
0
8/4
1F0000H to 1F1FFFH 0F8000H to 0F8FFFH
SA32 1
1
1
1
1
0
0
1
8/4
1F2000H to 1F3FFFH 0F9000H to 0F9FFFH
SA33 1
1
1
1
1
0
1
0
8/4
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH
SA34 1
1
1
1
1
0
1
1
8/4
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH
SA35 1
1
1
1
1
1
0
0
8/4
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH
SA36 1
1
1
1
1
1
0
1
8/4
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH
SA37 1
1
1
1
1
1
1
0
8/4
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH
SA38 1
1
1
1
1
1
1
1
8/4
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH
BA: Bank Address
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH)
38
MBM29DL16XTD/BD-70/90/12
Table 8.2 Sector Address Tables (MBM29DL164BD)
Sector Address
Sector
(×8)
(×16)
Size
Bank Sector BA
(Kbytes/
Address Range
Address Range
A19 A18 A17 A16 A15 A14 A13 A12 Kwords)
SA38 1
1
1
1
1 X X X
64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA37 1
1
1
1
0 X X X
64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36 1
1
1
0
1 X X X
64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35 1
1
1
0
0 X X X
64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA34 1
1
0
1
1 X X X
64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33 1
1
0
1
0 X X X
64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32 1
1
0
0
1 X X X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31 1
1
0
0
0 X X X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
Bank 2
SA30 1
0
1
1
1 X X X
64/32
170000H to 17FFFFH 0B8000H to 0BFFFFH
SA29 1
0
1
1
0 X X X
64/32
160000H to 16FFFFH 0B0000H to 0B7FFFH
SA28 1
0
1
0
1 X X X
64/32
150000H to 15FFFFH 0A8000H to 0AFFFFH
SA27 1
0
1
0
0 X X X
64/32
140000H to 14FFFFH 0A0000H to 0A7FFFH
SA26 1
0
0
1
1 X X X
64/32
130000H to 13FFFFH 098000H to 09FFFFH
SA25 1
0
0
1
0 X X X
64/32
120000H to 12FFFFH 090000H to 097FFFH
SA24 1
0
0
0 X X X X
64/32
110000H to 11FFFFH 088000H to 08FFFFH
SA23 1
0
0
0
0 X X X
64/32
100000H to 10FFFFH 080000H to 087FFFH
SA22 0
1
1
1
1 X X X
64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA21 0
1
1
1
0 X X X
64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA20 0
1
1
0
1 X X X
64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH
SA19 0
1
1
0
0 X X X
64/32 0C0000H to 0CFFFFH 060000H to 067FFFH
SA18 0
1
0
1
1 X X X
64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA17 0
1
0
1
0 X X X
64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA16 0
1
0
0
1 X X X
64/32
090000H to 09FFFFH 048000H to 04FFFFH
SA15 0
1
0
0
0 X X X
64/32
080000H to 08FFFFH 040000H to 047FFFH
SA14 0
0
1
1
1 X X X
64/32
070000H to 07FFFFH 038000H to 03FFFFH
SA13 0
0
1
1
0 X X X
64/32
060000H to 06FFFFH 030000H to 037FFFH
SA12 0
0
1
0
1 X X X
64/32
050000H to 05FFFFH 028000H to 02FFFFH
Bank 1 SA11 0
0
1
0
0 X X X
64/32
040000H to 04FFFFH 020000H to 027FFFH
SA10 0
0
0
1
1 X X X
64/32
030000H to 03FFFFH 018000H to 01FFFFH
SA9
0
0
0
1
0 X X X
64/32
020000H to 02FFFFH 010000H to 017FFFH
SA8
0
0
0
0
1 X X X
64/32
010000H to 01FFFFH 008000H to 00FFFFH
SA7
0
0
0
0
0
1
1
1
8/4
00E000H to 00FFFFH 007000H to 007FFFH
SA6
0
0
0
0
0
1
1
0
8/4
00C000H to 00DFFFH 006000H to 006FFFH
SA5
0
0
0
0
0
1
0
1
8/4
00A000H to 00BFFFH 005000H to 005FFFH
SA4
0
0
0
0
0
1
0
0
8/4
008000H to 009FFFH 004000H to 004FFFH
SA3
0
0
0
0
0
0
1
1
8/4
006000H to 007FFFH 003000H to 003FFFH
SA2
0
0
0
0
0
0
1
0
8/4
004000H to 005FFFH 002000H to 002FFFH
SA1
0
0
0
0
0
0
0
1
8/4
002000H to 003FFFH 001000H to 001FFFH
SA0
0
0
0
0
0
0
0
0
8/4
000000H to 001FFFH 000000H to 000FFFH
BA: Bank Address
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH).
39
MBM29DL16XTD/BD-70/90/12
Table 9.1 Sector Group Addresses (MBM29DL16XTD)
(Top Boot Block)
Sector Group
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
X
X
X
SA0
0
0
0
0
1
X
X
X
0
0
0
1
0
X
X
X
0
0
0
1
1
X
X
X
SGA2
0
0
1
X
X
X
X
X
SA4 to SA7
SGA3
0
1
0
X
X
X
X
X
SA8 to SA11
SGA4
0
1
1
X
X
X
X
X
SA12 to SA15
SGA5
1
0
0
X
X
X
X
X
SA16 to SA19
SGA6
1
0
1
X
X
X
X
X
SA20 to SA23
SGA7
1
1
0
X
X
X
X
X
SA24 to SA27
1
1
1
0
0
X
X
X
1
1
1
0
1
X
X
X
1
1
1
1
0
X
X
X
SGA9
1
1
1
1
1
0
0
0
SA31
SGA10
1
1
1
1
1
0
0
1
SA32
SGA11
1
1
1
1
1
0
1
0
SA33
SGA12
1
1
1
1
1
0
1
1
SA34
SGA13
1
1
1
1
1
1
0
0
SA35
SGA14
1
1
1
1
1
1
0
1
SA36
SGA15
1
1
1
1
1
1
1
0
SA37
SGA16
1
1
1
1
1
1
1
1
SA38
SGA1
SGA8
40
SA1 to SA3
SA28 to SA30
MBM29DL16XTD/BD-70/90/12
Table 9.2 Sector Group Addresses (MBM29DL16XBD)
(Bottom Boot Block)
Sector Group
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
1
1
1
SA7
0
0
0
0
1
X
X
X
0
0
0
1
0
X
X
X
0
0
0
1
1
X
X
X
SGA9
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
1
1
0
X
X
X
X
X
SA31 to SA34
1
1
1
0
0
X
X
X
1
1
1
0
1
X
X
X
1
1
1
1
0
X
X
X
1
1
1
1
1
X
X
X
SGA8
SGA15
SGA16
SA8 to SA10
SA35 to SA37
SA38
41
MBM29DL16XTD/BD-70/90/12
■ FUNCTIONAL DESCRIPTION
• Simultaneous Operation
MBM29DL16XTD/BD have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A15 to A19) with zero latency.
The MBM29DL161TD/BD have two banks which contain
Bank 1 (8KB × eight sectors) and Bank 2 (64KB × thirty-one sectors).
The MBM29DL162TD/BD have two banks which contain
Bank 1 (8KB × eight sectors, 64KB × three sectors) and Bank 2 (64KB × twenty eight sectors).
The MBM29DL163TD/BD have two banks which contain
Bank 1 (8KB × eight sectors, 64KB × seven sectors) and Bank 2 (64KB × twenty four sectors).
The MBM29DL164TD/BD have two banks which contain
Bank 1 (8KB × eight sectors, 64KB × fifteen sectors) and Bank 2 (64KB × sixteen sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 10 shows combination
to be possible for simultaneous operation. (Refer to the Figure 11 Bank-to-bank Read/Write Timing Diagram.)
Table 10 Simultaneous Operation
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode *
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode *
Read mode
*: An erase operation may also be supended to read from or program to a sector not being erased.
• Read Mode
The MBM29DL16XTD/BD have two control functions which must be satisfied in order to obtain data at the
outputs. CE is the power control and should be used for a device selection. OE is the output control and should
be used to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
42
MBM29DL16XTD/BD-70/90/12
• Standby Mode
There are two ways to implement the standby mode on the MBM29DL16XTD/BD devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
• Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL16XTD/BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29DL16XTD/BD automatically switch themselves to low power mode when
MBM29DL16XTD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL16XTD/BD read-out the data for changed addresses.
• Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
• Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Tables 3 and 4.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL16XTD/BD are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 12. (Refer to Autoselect Command section.)
43
MBM29DL16XTD/BD-70/90/12
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04H) and word 1 (A0 = VIH) represents the device
identifier code (MBM29DL161TD = 36H and MBM29DL161BD = 39H for ×8 mode; MBM29DL161TD = 2236H
and MBM29DL161BD = 2239H for ×16 mode), (MBM29DL162TD = 2DH and MBM29DL162BD = 2EH for ×8
mode; MBM29DL162TD = 222DH and MBM29DL162BD = 222EH for ×16 mode), (MBM29DL163TD = 28H and
MBM29DL163BD = 2BH for ×8 mode; MBM29DL163TD = 2228H and MBM29DL163BD = 222BH for ×16 mode),
(MBM29DL164TD = 33H and MBM29DL164BD = 35H for ×8 mode; MBM29DL164TD = 2233H and
MBM29DL164BD = 2235H for ×16 mode). These two bytes/words are given in the tables 11.1 to 11.8. All
identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read
the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 11.1 to 11.8.)
In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation
can not be executed.
Table 11.1 MBM29DL161TD/BD Sector Group Protection Verify Autoselect Codes
Type
A12 to A19
A6
A1
A0
A-1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04H
VIL
36H
X
VIL
VIL
VIH
X
2236H
VIL
39H
X
2239H
VIL
01H*2
Manufacture’s Code
Byte
MBM29DL161TD
Word
Device
Code
Byte
MBM29DL161BD
X
VIL
VIL
VIH
Word
Sector Group
Addresses
Sector Group Protection
VIH
VIL
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.2 Expanded Autoselect Code Table
Type
Code
Manufacturer’s Code
04H
(B)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
0
0
0
0
0
1
0
0
36H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
39H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
1
1
0
0
1
A-1/0
0
0
0
0
0
0
0
MBM29DL161TD
(W) 2236H 0
Device
Code
(B)
0
1
0
0
0
1
0
MBM29DL161BD
(W) 2239H 0
Sector Group Protection
(B): Byte mode
(W): Word mode
44
01H
A-1/0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL16XTD/BD-70/90/12
Table 11.3 MBM29DL162TD/BD Sector Group Protection Verify Autoselect Codes
Type
A12 to A19
A6
A1
A0
A-1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04H
VIL
2DH
X
VIL
VIL
VIH
X
222DH
VIL
2EH
X
222EH
VIL
01H*2
Manufacture’s Code
Byte
MBM29DL162TD
Word
Device
Code
Byte
MBM29DL162BD
X
VIL
VIL
VIH
Word
Sector Group
Addresses
Sector Group Protection
VIH
VIL
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.4 Expanded Autoselect Code Table
Type
Code
Manufacturer’s Code
04H
(B)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
0
0
0
0
0
1
0
0
2DH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
2EH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
0
1
1
1
0
A-1/0
0
0
0
0
0
0
0
MBM29DL162TD
(W) 222DH 0
Device
Code
(B)
0
1
0
0
0
1
0
MBM29DL162BD
(W) 222EH 0
Sector Group Protection
01H
A-1/0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(B): Byte mode
(W): Word mode
45
MBM29DL16XTD/BD-70/90/12
Table 11.5 MBM29DL163TD/BD Sector Group Protection Verify Autoselect Codes
Type
A12 to A19
A6
A1
A0
A-1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04H
VIL
28H
X
VIL
VIL
VIH
X
2228H
VIL
2BH
X
222BH
VIL
01H*2
Manufacture’s Code
Byte
MBM29DL163TD
Word
Device
Code
Byte
MBM29DL163BD
X
VIL
VIL
VIH
Word
Sector Group
Addresses
Sector Group Protection
VIH
VIL
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.6 Expanded Autoselect Code Table
Type
Code
Manufacturer’s Code
04H
(B)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
0
0
0
0
0
1
0
0
28H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
2BH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
0
1
0
1
1
A-1/0
0
0
0
0
0
0
0
MBM29DL163TD
(W) 2228H 0
Device
Code
(B)
0
1
0
0
0
1
0
MBM29DL163BD
(W) 222BH 0
Sector Group Protection
(B): Byte mode
(W): Word mode
46
01H
A-1/0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL16XTD/BD-70/90/12
Table 11.7 MBM29DL164TD/BD Sector Group Protection Verify Autoselect Codes
Type
A12 to A19
A6
A1
A0
A-1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04H
VIL
33H
X
VIL
VIL
VIH
X
2233H
VIL
35H
X
2235H
VIL
01H*2
Manufacture’s Code
Byte
MBM29DL164TD
Word
Device
Code
Byte
MBM29DL164BD
X
VIL
VIL
VIH
Word
Sector Group
Addresses
Sector Group Protection
VIH
VIL
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.8 Expanded Autoselect Code Table
Type
Code
Manufacturer’s Code
04H
(B)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
0
0
0
0
0
1
0
0
33H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
35H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
1
1
0
1
0
1
A-1/0
0
0
0
0
0
0
0
MBM29DL164TD
(W) 2233H 0
Device
Code
(B)
0
1
0
0
0
1
0
MBM29DL164BD
(W) 2235H 0
Sector Group Protection
01H
A-1/0
0
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(B): Byte mode
(W): Word mode
47
MBM29DL16XTD/BD-70/90/12
• Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
• Sector Group Protection
The MBM29DL16XTD/BD feature hardware sector group protection. This feature will disable both program and
erase operations in any combination of seventeen sector groups of memory. (See Tables 9.1 and 9.2). The sector
group protection feature is enabled using programming equipment at the user’s site. The device is shipped with
all sector groups unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A19, A18, A17, A16, A15, A14, A13,
and A12) should be set to the sector to be protected. Tables 5.1 to 8.2 define the sector address for each of the
thirty nine (39) individual sectors, and tables 9.1 and 9.2 define the sector group address for each of the seventeen
(17) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse
and is terminated with the rising edge of the same. Sector group addresses must be held constant during the
WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and
A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.
Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except
for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer
and device codes. A-1 requires to apply to VIL on byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A19, A18, A17,
A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected
sector group. See Tables 11.1 to 11.8 for Autoselect codes.
• Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL16XTD/BD
devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to
high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector
groups will be protected again. Refer to Figures 19 and 27.
48
MBM29DL16XTD/BD-70/90/12
• RESET
Hardware Reset
The MBM29DL16XTD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 14 for the timing
diagram. Refer to Temporary Sector Group Unprotection for additional functionality.
• Boot Block Sector Protection
The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This
function is one of two provided by the WP/ACC pin.
If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two
“outermost” 8K byte boot sectors independently of whether those sectors were protected or unprotected using
the method described in “Sector Protection/Unprotection”. The two outermost 8K byte boot sectors are the two
sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the
highest addresses in a top-boot-congfigured device.
(MBM29DL16XTD: SA37 and SA38, MBM29DL16XBD: SA0 and SA1)
If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
sectors depends on whether they were last protected or unprotected using the method described in “Sector
protection/unprotection”.
• Accelerated Program Operation
MBM29DL16XTD/BD offers accelerated program operation which enables the programming in high speed.
If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the
time required for program operation will reduce to about 60%. This function is primarily intended to allow high
speed program, so caution is needed as the sector group will temporarily be unprotected.
The system would use a fact program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be
used for programming and detection of completion during acceleration mode.
Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/
ACC pin while programming. See Figure 21.
49
MBM29DL16XTD/BD-70/90/12
Table 12 MBM29DL16XTD/BD Command Definitions
Command
Sequence
Read/Reset
Read/Reset
Word
Byte
Word
Byte
Bus
Write
Cycles
Req’d
1
3
Word
3
Autoselect
Byte
Program
Word
Byte
Program Suspend
Program Resume
Chip Erase
Sector Erase
Word
Byte
Word
Byte
Erase Suspend
Erase Resume
Set to
Fast Mode
Word
Fast
Program *1
Word
Reset from
Fast Mode *1
Word
Extended
Sector Group
Protection *2
Query *3
Byte
Byte
Byte
Word
Byte
Word
Byte
Hi-ROM
Entry
Word
Hi-ROM
Program *4
Word
Hi-ROM
Erase *4
Word
Hi-ROM
Exit *4
Byte
Byte
Byte
1
1
6
6
1
1
3
2
2
4
1
3
4
6
XXXH F0H
—
—
—
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
(BA)
555H
2AAH
555H
AAH
55H
(BA)
AAAH
555H
AAAH
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
BA
B0H
—
—
—
BA
30H
—
—
—
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
BA
B0H
—
—
—
BA
30H
—
—
—
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
XXXH
A0H
PA
PD
—
XXXH
BA
XXXH
90H
F0H
—
BA
XXXH
XXXH 60H
55H
AAH
555H
AAAH
555H
AAAH
555H
AAAH
98H
4
—
—
—
—
—
—
F0H
RA
RD
—
—
—
—
90H
—
—
—
—
—
—
A0H
PA
PD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
555H
2AAH
555H
80H
AAH
55H
10H
AAAH
555H
AAAH
555H
2AAH
80H
AAH
55H
SA
30H
AAAH
555H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPA
60H
SPA
40H
SPA
SD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HRA
30H
—
—
2AAH
555H
55H
88H
—
—
—
—
555H
AAAH
2AAH
555H
AAH
55H
A0H
PA
PD
—
—
555H
AAAH
2AAH
555H
555H
2AAH
AAH
55H
80H
AAH
55H
555H
AAAH
AAAH
555H
(HRBA)
2AAH
AAH
AAAH
—
AAH
555H
Word
Byte
50
4
First Bus Second Bus Third Bus Fourth Bus
Fifth Bus
Sixth Bus
Write Cycle Write Cycle Write Cycle Read/Write
Write
Cycle
Write
Cycle
Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
55H
555H
555H
(HRBA)
AAAH
90H XXXH 00H
—
—
MBM29DL16XTD/BD-70/90/12
Notes: 1. Address bits A11 to A19 = X = “H” or “L” for all address commands except or Program Address (PA), Sector
Address (SA), and Bank Address (BA).
2. Bus operations are defined in Tables 3 and 4.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank Address (A15 to A19)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).
SD = Sector group protection verify data. Output 01H at protected sector group addresses and output
00H at unprotected sector group addresses.
6. HRA = Address of the Hi-ROM area
29DL16XTD (Top Boot Type)
Word Mode: 0F8000H to 0FFFFFH
Byte Mode: 1F0000H to 1FFFFFH
29DL16XBD (Bottom Boot Type) Word Mode: 000000H to 007FFFH
Byte Mode: 000000H to 00FFFFH
7. HRBA =Bank Address of the Hi-ROM area
29DL16XTD (Top Boot Type)
:A15 = A16= A17 = A18 = A19 = 1
29DL16XBD (Bottom Boot Type) :A15 = A16= A17 = A18 = A19 = 0
8. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A–1 and A0 to A10
9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*1:This command is valid while Fast Mode.
*2:This command is valid while RESET = VID.
*3:The valid addresses are A6 to A0.
*4:This command is valid while Hi-ROM mode.
51
MBM29DL16XTD/BD-70/90/12
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed
to bank being read, the commands have priority than reading. Table 12 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Also the Program Suspend (B0H) and Program Resume (30H) commands
are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally
equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7
and DQ8 to DQ15 bits are ignored.
• Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
• Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA)00H retrieves the manufacture code of 04H. A
read cycle from address (BA)01H for ×16((BA)02H for ×8) returns the device code (MBM29DL161TD = 36H and
MBM29DL161BD = 39H for ×8 mode; MBM29DL161TD = 2236H and MBM29DL161BD = 2239H for ×16 mode),
(MBM29DL162TD = 2DH and MBM29DL162BD = 2EH for ×8 mode; MBM29DL162TD = 222DH and
MBM29DL162BD = 222EH for ×16 mode), (MBM29DL163TD = 28H and MBM29DL163BD = 2BH for ×8 mode;
MBM29DL163TD = 2228H and MBM29DL163BD = 222BH for ×16 mode), (MBM29DL164TD = 33H and
MBM29DL164BD = 35H for ×8 mode; MBM29DL164TD = 2233H and MBM29DL164BD = 2235H for ×16 mode).
(See Tables 11.1 to 11.8.)
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (BA)02H for ×16 ((BA)04H for ×8). Scanning the sector group
addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device
output DQ0 for a protected sector group. The programming verification should be performed by verify sector
group protection on the protected sector. (See Tables 3 and 4.)
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
52
MBM29DL16XTD/BD-70/90/12
If the software (program code) for Autoselect command is stored into the Flash memory, the device and
manufacture codes should be read from the other bank where is not contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
• Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit),
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13,
Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by
the system at this particular instance of time. Hence, Data Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 22 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
• Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 23 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
53
MBM29DL16XTD/BD-70/90/12
• Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first.
After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 12. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW”
from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase
command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out
window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section
DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period
will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once
execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 38).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY.
The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe.
Figure 23 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
• Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30H) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writting the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the
54
MBM29DL16XTD/BD-70/90/12
RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must
use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30H) should be written to the bank being
erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
55
MBM29DL16XTD/BD-70/90/12
• Extended Command
(1) Fast Mode
MBM29DL16XTD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. The first cycle must contain the bank address. (Refer to the Figure 28.) The VCC active current is
required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 28.)
(3) Extended Sector Group Protection
In addition to normal sector group protection, the MBM29DL16XTD/BD has Extended Sector Group
Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin
and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control
timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended
sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing
the set-up command (60H) into the command register. Then, the sector group addresses pins (A19, A18, A17,
A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected
(recommend to set VIL for the other addresses pins), and write extended sector group protection command
(60H). A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the
sector group addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set
and write a command (40H). Following the command write, a logical “1” at device output DQ0 will produce
for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended
sector group protection command (60H) again. To terminate the operation, it is necessary to set RESET pin
to VIH. (Refer to the Figures 20 and 29.)
(4) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. The bank address
should be set when writing this command. Then the device information can be read from the bank, and an
actual data of memory cell be read from the another bank. Following the command write, a read cycle from
specific address retrives device information. Please note that output data of upper byte (DQ8 to DQ15) is “0”
in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the
read/reset command sequence into the register. (See Table 15.)
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MBM29DL16XTD/BD-70/90/12
• Hidden ROM (Hi-ROM) Region
The Hi-ROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the Hi-ROM region is protected, any further
modification of that region is impossible. This ensures the security of the ESN once the product is shipped to
the field.
The Hi-ROM region is 64K bytes in length and is stored at the same address of the 8KB ×8 sectors. The
MBM29DL16XTD occupies the address of the byte mode 1F0000H to 1FFFFFH (word mode 0F8000H to
0FFFFFH) and the MBM29DL16XBD type occupies the address of the byte mode 000000H to 00FFFFH (word
mode 000000H to 007FFFH). After the system has written the Enter Hi-ROM command sequence, the system
may read the Hi-ROM region by using the addresses normally occupied by the boot sectors. That is, the device
sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation
continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the
device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.
• Hidden ROM (Hi-ROM) Entry Command
MBM29DL16XTD/BD has a Hidden ROM area with One Time Protect function. This area is to enter the security
code and to unable the change of the code once set. Program/erase is possible in this area until it is protected.
However, once it is protected, it is impossible to unprotect, so please use this with caution.
Hidden ROM area is 64K Byte and in the same address area of 8KB sector. The address of top boot is 1F0000H
to 1FFFFFH at byte mode (0F8000H to 0FFFFFH at word mode) and the bottom boot is 000000H to 00FFFFH
at byte mode (000000H to 007FFFH at word mode). These areas are normally the boot block area (8KB ×8
sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called
as Hidden ROM mode when the Hidden ROM area appears.
Sector other than the boot block area could be read during Hidden ROM mode. Read/program/earse of the
Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to
exit the Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset
command sequence.
In case of MBM29DL161TD/BD, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute
multi-function mode between the Hidden ROM area and Bank 2 Region.
• Hidden ROM (Hi-ROM) Program Command
To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden
ROM mode. This command is same as the program command in the past except to write the command during
Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7
data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address
other than the Hidden ROM area is selected to program, the data of the address will be changed.
• Hidden ROM (Hi-ROM) Erase Command
To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode.
This command is same as the sector erase command in the past except to write the command during Hidden
ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling,
DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address
other than the Hidden ROM area is selected, the data of the sector will be changed.
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MBM29DL16XTD/BD-70/90/12
• Hidden ROM (Hi-ROM) Protect Command
There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup
command(60H), set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0), and write the sector
group protect command(60H) during the Hidden ROM mode. The same command sequence could be used
because except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is
the same as the extension sector group protect in the past. Please refer to “Function Explanation Extended
Command (3) Extentended Sector Group Protection” for details of extention sector group protect setting.
The other is to apply high voltage (VID) to A9 and OE, set the sector address in the Hidden ROM area and (A6,
A1, A0) = (0,1,0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high
voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the Hidden ROM area, and read.
When “1” appears to DQ0, the protect setting is completed. “0” will appear to DQ0 if it is not protected. Please
apply write pulse agian. The same command sequence could be used for the above method because other than
the Hidden ROM mode, it is the same as the sector group protect in the past. Please refer to “Function Explanation
Secor Group Protection” for details of sector group protect setting
Other sector group will be effected if the address other than the Hidden ROM area is selected for the sectoer
group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay closest
attention.
• Write Operation Status
Detailed in Table 13 are all the status flags that can determine the status of the bank for the current mode
operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory
cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The
information on DQ2 is address sensitive. This means that if an address from an erasing sector is consectively
read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is
consectively read. This allows the user to determine which sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>,
[2] <non-busy bank>, [3] <busy bank>, the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of
memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled
in the [1] and [3].
In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
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MBM29DL16XTD/BD-70/90/12
Table 13 Hardware Sequence Flags
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle*
Data
Data
Data Data
Data
Data
Data
Data Data
Data
1
1
Data
Data
DQ7
Toggle
0
0
1*
Embedded Program Algorithm
DQ7
Toggle
1
0
1
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Status
Embedded Program Algorithm
Embedded Erase Algorithm
In Progress
Program Suspend Read
Program
(Program Suspended Sector)
Suspended
Program Suspend Read
Mode
(Non-Program Suspended Sector)
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspended
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
*
0
0
Data Data
Toggle
Data
Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase
suspend sector address will indicate logic “1” at the DQ2 bit.
Notes: 1. DQ0 and DQ1 are reserve pins for future use.
2. DQ4 is Fujitsu internal use only.
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MBM29DL16XTD/BD-70/90/12
• DQ7
Data Polling
The MBM29DL16XTD/BD devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 24.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL16XTD/BD data pins (DQ7)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6
may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 13.)
See Figure 9 for the Data Polling timing specifications and diagrams.
• DQ6
Toggle Bit I
The MBM29DL16XTD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
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MBM29DL16XTD/BD-70/90/12
The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the
Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause
DQ6 to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
• DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 3 and 4.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
• DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
See Table 13: Hardware Sequence Flags.
• DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
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MBM29DL16XTD/BD-70/90/12
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 14 and Figure 12.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Table 14 Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
DQ7
Toggle
1 (Note)
Mode
Program
Erase-Suspend Program
Note: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from nonerase suspend sector address will indicate logic “1” at the DQ2 bit.
• RY/BY
Ready/Busy
The MBM29DL16XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL16XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
• Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL16XTD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to Figures 15, 16 and 17 for the timing diagram.
• Data Protection
The MBM29DL16XTD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
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MBM29DL16XTD/BD-70/90/12
• Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO (min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when VCC is above VLKO (min).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
• Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
• Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
• Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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MBM29DL16XTD/BD-70/90/12
Table 15 Common Flash Memory Interface Code
Description
Query-unique ASCII string
“QRY”
Primary OEM Command Set
2h: AMD/FJ standard type
Address for Primary
Extended Table
Alternate OEM Command
Set (00h = not applicable)
Address for Alternate OEM
Extended Table
VCC Min. (write/erase)
D7-4: volt, D3-0: 100 mvolt
VCC Max. (write/erase)
D7-4: volt, D3-0: 100 mvolt
VPP Min. voltage
VPP Max. voltage
Typical timeout per single
byte/word write 2N µs
Typical timeout for Min. size
buffer write 2N µs
Typical timeout per individual
block erase 2N ms
Typical timeout for full chip
erase 2N ms
Max. timeout for byte/word
write 2N times typical
Max. timeout for buffer write
2N times typical
Max. timeout per individual
block erase 2N times typical
Max. timeout for full chip
erase 2N times typical
Device Size = 2N byte
Flash Device Interface
description
Max. number of byte in
multi-byte write = 2N
Number of Erase Block
Regions within device
Erase Block Region 1
Information
Erase Block Region 2
Information
64
A0 to A6
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
DQ0 to DQ15
1Ch
0036h
1Dh
1Eh
1Fh
0000h
0000h
0004h
20h
0000h
21h
000Ah
22h
0000h
23h
0005h
24h
0000h
25h
0004h
26h
0000h
27h
28h
29h
2Ah
2Bh
2Ch
0015h
0002h
0000h
0000h
0000h
0002h
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
0007h
0000h
0020h
0000h
001Eh
0000h
0000h
0001h
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
0027h
Description
Query-unique ASCII string
“PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0h = Required
1h = Not Required
Erase Suspend
0h = Not Supported
1h = To Read Only
2h = To Read & Write
Sector Protection
0h = Not Supported
X = Number of sectors in per
group
Sector Temporary
Unprotection
00h = Not Supported
01h = Supported
Sector Protection Algorithm
Number of Sector for Bank 2
00h = Not Supported
3Fh = MBM29DL161TD
38h = MBM29DL162TD
30h = MBM29DL163TD
20h = MBM29DL164TD
3Fh = MBM29DL161BD
38h = MBM29DL162BD
30h = MBM29DL163BD
20h = MBM29DL164BD
Burst Mode Type
00h = Not Supported
Page Mode Type
00h = Not Supported
ACC (Acceleration) Supply
Minimum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
ACC (Acceleration) Supply
Maximum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
Boot Type
02h = MBM29DL16XBD
03h = MBM29DL16XTD
A0 to A6
40h
41h
42h
43h
44h
45h
DQ0 to DQ15
46h
0002h
47h
0001h
48h
0001h
49h
4Ah
0004h
00XXh
4Bh
0000h
4Ch
0000h
4Dh
0085h
4Eh
0095h
4Fh
00XXh
0050h
0052h
0049h
0031h
0031h
0000h
MBM29DL16XTD/BD-70/90/12
■ FLOW CHART
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See below)
Data Polling Device
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 22 Embedded ProgramTM Algorithm
65
MBM29DL16XTD/BD-70/90/12
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequence
(See below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Sector Address/30H
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 23 Embedded EraseTM Algorithm
66
MBM29DL16XTD/BD-70/90/12
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase
Yes
No
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
Yes
No
Fail
Pass
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 24 Data Polling Algorithm
67
MBM29DL16XTD/BD-70/90/12
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 6 = Toggle
?
VA = Bank address being executed
Embedded Algorithm.
No
Yes
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 6 = Toggle
?
No
Yes
Fail
Pass
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1” .
Figure 25 Toggle Bit Algorithm
68
MBM29DL16XTD/BD-70/90/12
Start
Setup Sector Group Addr.
(A19, A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = V ID, A 9 = V ID,
A 6 = CE = V IL, RESET = V IH
A 0 = V IL, A 1 = V IH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A 9 should remain V ID)
Read from Sector Group
(Addr. = SGA, A 0 = V IL,
A 1 = V IH, A 6 = V IL)*
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Yes
Remove V ID from A 9
Write Reset Command
Protect Another Sector
Group ?
No
Device Failed
Remove V ID from A 9
Write Reset Command
Sector Group Protection
Completed
* : A-1 is V IL on byte mode.
Figure 26 Sector Group Protection Algorithm
69
MBM29DL16XTD/BD-70/90/12
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotection Completed
(Note 2)
Notes: 1. All protected sector groups are unprotected.
2. All previously protected sector groups are protected once again.
Figure 27 Temporary Sector Group Unprotection Algorithm
70
MBM29DL16XTD/BD-70/90/12
FAST MODE ALGORITHM
Start
555H/AAH
Set Fast Mode
2AAH/55H
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
(BA) XXXH/90H
Reset Fast Mode
XXXH/F0H
Note: The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 28 Embedded ProgramTM Algorithm for Fast Mode
71
MBM29DL16XTD/BD-70/90/12
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector Group
Unprotection Mode
No
Extended Sector Group
Protection Entry?
Yes
To Setup Sector Group
Protection Write XXXH/60H
PLSCNT = 1
To Sector Group Protection
Write SGA/60H
(A0 = VIL, A1 = VIH, A6 = VIL)
Time Out 250 µs
Increment PLSCNT
To Verify Sector Group
Protection Write SGA/40H
(A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Group
Address
Read from Sector Group
Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
Data = 01H?
Yes
Yes
Protection Other Sector
Group ?
No
Device Failed
Remove VID from RESET
Write Reset Command
Sector Group Protection
Completed
Figure 29 Extended Sector Group Protection Algorithm
72
MBM29DL16XTD/BD-70/90/12
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29DL16X
T
E
70
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PBT = 48-Ball Fine pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29DL16X
16Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
Valid Combinations
Valid Combinations
MBM29DL161TD/BD
MBM29DL162TD/BD
MBM29DL163TD/BD
MBM29DL164TD/BD
70
90
12
PFTN
PFTR
PBT
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Fujitsu sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
73
MBM29DL16XTD/BD-70/90/12
■ PACKAGE DIMENSIONS
48-pin plastic TSOP(I)
(FPT-48P-M19)
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
(.472±.008)
11.50REF
(.460)
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting height)
0.50(.0197)
TYP
0.10(.004)
0.05(0.02)MIN
(STAND OFF)
0.15±0.05
(.006±.002)
19.00±0.20
(.748±.008)
C
0.25(.010)
0.20±0.10
(.008±.004)
0.10(.004)
M
0.50±0.10
(.020±.004)
Dimensions in mm (inches)
1996 FUJITSU LIMITED F48029S-2C-2
48-pin plastic TSOP(I)
(FPT-48P-M20)
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
24
0.25(.010)
25
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
0.15±0.10
(.006±.002)
0.10(.004)
0.20±0.10
(.008±.004)
0.50(.0197)
TYP
0.10(.004)
M
0.05(0.02)MIN
(STAND OFF)
+0.10
1.10 –0.05
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
1996 FUJITSU LIMITED F48030S-2C-2
11.50(.460)REF
+.004
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
Dimensions in mm (inches)
(Continued)
74
MBM29DL16XTD/BD-70/90/12
(Continued)
48-pin plastic FBGA
(BGA-48P-M13)
+0.15
9.00±0.20(.354±.008)
+.006
1.05 –0.10 .041 –.004
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
5.60(.221)
0.80(.031)TYP
6
5
8.00±0.20
(.315±.008)
4
4.00(.157)
3
INDEX
2
1
H
C0.25(.010)
G
F
E
D
C
48-Ø0.45±0.10
(48-.018±.004)
B
A
Ø0.08(.003)
M
0.10(.004)
C
1998 FUJITSU LIMITED B480013S-1C-1
Dimensions in mm (inches)
75
MBM29DL16XTD/BD-70/90/12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9909
 FUJITSU LIMITED Printed in Japan
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notice. Customers are advised to consult with FUJITSU sales
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presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
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