HP HCPL-0466 Intelligent power module and gate drive interface optocoupler Datasheet

H
Intelligent Power Module and
Gate Drive Interface Optocouplers
HCPL-4506
HCPL-0466
HCNW4506
Technical Data
Features
Applications
• Performance Specified for
Common IPM Applications
over Industrial Temperature
Range: -40°C to 100°C
• Fast Maximum Propagation
Delays
tPHL = 400 ns
tPLH = 550 ns
• Minimized Pulse Width
Distortion (PWD = 450 ns)
• 15 kV/µs Minimum Common
Mode Transient Immunity at
VCM = 1500 V
• CTR > 44% at IF = 10 mA
• Safety Approval
UL Recognized - 2500 V rms
for 1 minute (5000 V rms for
1 minute for HCNW4506 and
HCPL-4506 Option 020) per
UL1577
CSA Approved
VDE 0884 Approved
-VIORM = 630 V peak for
HCPL-4506 Option 060
-VIORM = 1414 V peak for
HCNW4506
BSI Certified (HCNW4506)
• IPM Isolation
• Isolated IGBT/MOSFET Gate
Drive
• AC and Brushless DC Motor
Drives
• Industrial Inverters
Description
The HCPL-4506 and HCPL-0466
contain a GaAsP LED while the
HCNW4506 contains an AlGaAs
LED. The LED is optically
coupled to an integrated high gain
photo detector. Minimized propa-
Functional Diagram
NC
1
gation delay difference between
devices make these optocouplers
excellent solutions for improving
inverter efficiency through
reduced switching dead time.
An on chip 20 kΩ output pull-up
resistor can be enabled by shorting output pins 6 and 7, thus
eliminating the need for an
external pull-up resistor in
common IPM applications. Specifications and performance plots
are given for typical IPM
applications.
Truth Table
8
VCC
20 kΩ
ANODE
2
7
VL
CATHODE
3
6
VO
NC
4
5
GND
SHIELD
LED
VO
ON
OFF
L
H
Selection Guide
Operating Temperature
TA [°C]
Min.
-40
Max.
100
-55
125
Single Channel Packages
8-Pin DIP
(300 Mil)
HCPL-4506
Small Outline
SO-8
HCPL-0466
Widebody
(400 Mil)
HCNW4506
Hermetic*
HCPL-5300
HCPL-5301
*Technical data for these products are on separate HP publications.
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
5965-3603E
1-49
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4506#XXX
020
060
300
500
= UL 5000 V rms/1 Minute Option*
= VDE 0884 VIORM = 630 V peak Option*
= Gull Wing Surface Mount Option†
= Tape and Reel Packaging Option
*For HCPL-4506 only. Combination of Option 020 and
Option 060 is not available.
†Gull wing surface mount option applies to through
hole parts only.
Option data sheets are available. Contact your Hewlett-Packard sales representative or authorized
distributor for information.
Package Outline Drawings
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
HP XXXXZ
YYWW RU
1
2
3
UL
RECOGNITION
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5° TYP.
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
Figure 1. HCPL-4506 Outline Drawing (Standard DIP Package).
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
1.194 (0.047)
5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
9.398 (0.370)
9.906 (0.390)
4
0.381 (0.015)
0.635 (0.025)
1.194 (0.047)
1.778 (0.070)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
Figure 2. HCPL-4506 Gull Wing Surface Mount Option #300 Outline Drawing.
1-50
8
7
6
5
5.842 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
1
2
3
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
4
0.381 ± 0.076
(0.016 ± 0.003)
1.270 BSG
(0.050)
0.432
45° X (0.017)
7°
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.152 ± 0.051
(0.006 ± 0.002)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Figure 3. HCPL-0466 Outline Drawing (8-Pin Small Outline Package).
Pin Location (for reference only)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
6
7
8
9.00 ± 0.15
(0.354 ± 0.006)
5
TYPE NUMBER
HP
HCNWXXXX
DATE CODE
YYWW
1
3
2
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
0.51 (0.021) MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 4a. HCNW4506 Outline Drawing (8-Pin Widebody Package).
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
PAD LOCATION (FOR REFERENCE ONLY)
5
6.15 TYP.
(0.242)
9.00 ± 0.15
(0.354 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
1
2
3
4
1.3
(0.051)
1.55
(0.061)
MAX.
0.9
(0.035)
12.30 ± 0.30
(0.484 ± 0.012)
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
2.54
(0.100)
BSC
0.75 ± 0.25
(0.030 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
1.00 ± 0.15
(0.039 ± 0.006)
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
7° NOM.
Figure 4b. HCNW4506 Outline Drawing (8-Pin Widebody Package with Gull Wing Surface Mount Option 300).
1-51
TEMPERATURE – °C
Solder Reflow Temperature Profile
260
240
220
200
180
160
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
140
120
100
80
60
40
20
0
∆T = 100°C, 1.5°C/SEC
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is recommended.
Regulatory Information
The devices contained in this data
sheet have been approved by the
following organizations:
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
VDE
Approved according to VDE
0884/06.92 (HCNW4506 and
HCPL-4506 Option 060 only).
BSI
Certification according to
BS451:1994
(BS EN60065:1994);
BS EN60950:1992
(BS7002:1992) and
EN41003:1993 for Class II
applications (HCNW4506 only).
Insulation and Safety Related Specifications
Symbol
8-Pin DIP
(300 Mil)
Value
SO-8
Value
Minimum External
Air Gap (External
Clearance)
L(101)
7.1
4.9
9.6
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External
Tracking (External
Creepage)
L(102)
7.4
4.8
10.0
mm
Measured from input terminals
to output terminals, shortest
distance path along body.
0.08
0.08
1.0
mm
Through insulation distance,
conductor to conductor, usually
the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
NA
NA
4.0
mm
Measured from input terminals
to output terminals, along
internal cavity.
200
200
200
Volts
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
IIIa
Parameter
Minimum Internal
Plastic Gap
(Internal Clearance)
Minimum Internal
Tracking (Internal
Creepage)
Tracking Resistance
(Comparative
Tracking Index)
Isolation Group
CTI
Widebody
(400 Mil)
Value
Units
Conditions
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-52
VDE 0884 Insulation Related Characteristics
(HCPL-4506 OPTION 060 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/100/21
2
630
V peak
VPR
1181
V peak
VPR
945
V peak
VIOTM
6000
V peak
TS
IS,INPUT
PS,OUTPUT
RS
175
230
600
≥ 109
°C
mA
mW
Ω
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/100/21
2
1414
V peak
VPR
2652
V peak
VPR
2121
V peak
VIOTM
8000
V peak
TS
IS,INPUT
PS,OUTPUT
RS
150
400
700
≥ 109
°C
mA
mW
Ω
VDE 0884 Insulation Related Characteristics (HCNW4506 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage ≤ 1000 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-53
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current[1]
Peak Input Current[2] (50% duty cycle, ≤ 1 ms pulse width)
Peak Transient Input Current (<1 µs pulse width, 300 pps)
Reverse Input Voltage (Pin 3-2)
HCPL-4506, HCPL-0466
HCNW4506
Average Output Current (Pin 6)
Resistor Voltage (Pin 7)
Output Voltage (Pin 6-5)
Supply Voltage (Pin 8-5)
Output Power Dissipation[3]
Total Power Dissipation[4]
Lead Solder Temperature (HCPL-4506)
Lead Solder Temperature (HCNW4506)
Infrared and Vapor Phase Reflow Temperature
(HCPL-0466 and Option 300)
Symbol
TS
TA
IF(avg)
IF(peak)
IF(tran)
VR
Min.
-55
-40
Max.
Units
125
°C
100
°C
25
mA
50
mA
1.0
A
5
Volts
3
IO(avg)
15
mA
V7
-0.5
VCC
Volts
VO
-0.5
30
Volts
VCC
-0.5
30
Volts
PO
100
mW
PT
145
mW
260°C for 10 s, 1.6 mm below seating plane
260°C for 10 s (up to seating plane)
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Power Supply Voltage
Output Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
Symbol
VCC
VO
IF(on)
VF(off)*
TA
Min.
4.5
0
10
-5
-40
Max.
30
30
20
0.8
100
Units
Volts
Volts
mA
V
°C
*Recommended VF(OFF) = -3 V to 0.8 V for HCNW4506.
Electrical Specifications
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Current Transfer Ratio
Low Level Output Current
Low Level Output Voltage
Input Threshold Current
High Level Output Current
High Level Supply Current
Low Level Supply Current
Input Forward Voltage
Symbol Min. Typ.* Max. Units
CTR
44
90
%
IOL
4.4
9.0
mA
VOL
0.3
0.6
V
ITH
1.5
5.0
mA
IOH
5
50
µA
ICCH
0.6
1.3
mA
ICCL
0.6
1.3
mA
VF
1.5
1.8
V
Temperature Coefficient
of Forward Voltage
∆VF /∆TA
Input Reverse Breakdown
Voltage
BVR
Input Capacitance
CIN
1.6
-1.6
-1.3
5
3
Internal Pull-up Resistor
Internal Pull-up Resistor
Temperature Coefficient
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCNW4506.
1-54
RL
∆RL /∆TA
60
14
72
20
0.014
Test Conditions
Fig. Note
IF = 10 mA, VO = 0.6 V
5
IF = 10 mA, VO = 0.6 V
5,6
IO = 2.4 mA
VO = 0.8 V, IO = 0.75 mA
5
14
VF = 0.8 V
7
VF = 0.8 V, VO = Open
14
IF = 10 mA, VO = Open
14
HCPL-4506 IF = 10 mA 8
HCPL-0466
1.85
HCNW4506
9
mV/°C HCPL-4506 IF = 10 mA
HCPL-0466
HCNW4506
V
HCPL-4506 IR = 100 µA
HCPL-0466
HCNW4506
pF
HCPL-4506 f = 1 MHz,
HCPL-0466 VF = 0 V
HCNW4506
25
kΩ
TA = 25°C
10,11
kΩ/°C
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol
Propagation Delay
tPHL
Time to Low
Output Level
Propagation Delay
tPLH
Time to High
Output Level
Pulse Width
PWD
Distortion
Propagation Delay tPLH-tPHL
Difference Between
Any 2 Parts
Output High Level
|CMH|
Common Mode
Transient Immunity
Output Low Level
|CML|
Common Mode
Transient Immunity
Min. Typ.* Max.
30
200
400
100
270
Units
ns
ns
Test Conditions
CL = 100 pF IF(on) = 10 mA,
VF(off) = 0.8 V,
CL = 10 pF V = 15.0 V,
CC
VTHLH = 2.0 V,
CL = 100 pF
VTHHL = 1.5 V
CL = 10 pF
CL = 100 pF
400
550
ns
130
200
450
ns
-150
200
450
ns
15
30
kV/µs
IF = 0 mA,
VO > 3.0 V
15
30
kV/µs
IF = 10 mA
VO < 1.0 V
Fig. Note
10,
9,
12,
12,
14-17 14
18
15
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 VP-P
TA = 25°C
11
16
17
Switching Specifications (RL = Internal Pull-up)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Min. Typ.* Max.
Propagation Delay
tPHL
20
200 400
Time to Low
Output Level
Propagation Delay
tPLH
220 450 650
Time to High
Output Level
Pulse Width
PWD
250 500
Distortion
Propagation Delay tPLH-tPHL -150 250 500
Difference Between
Any 2 Parts
Output High Level
|CMH|
30
Common Mode
Transient Immunity
Output Low Level
|CML|
30
Common Mode
Transient Immunity
Power Supply
PSR
1.0
Rejection
Units
ns
Test Conditions
IF(on) = 10 mA, VF(off) = 0.8 V,
VCC = 15.0 V, CL = 100 pF,
VTHLH = 2.0 V, VTHHL = 1.5 V
Fig.
10,
13
Note
9-12,
14
ns
ns
18
ns
15
kV/µs
IF = 0 mA,
VO > 3.0 V
kV/µs
IF = 16 mA,
VO < 1.0 V
VP-P
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 VP-P,
TA = 25°C
Square Wave, tRISE, tFALL
> 5 ns, no bypass capacitors
11
16
17
14
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCNW4506.
1-55
Package Characteristics
Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.
Parameter
Input-Output Momentary
Withstand Voltage†
Sym.
VISO
Resistance
(Input-Output)
RI-O
Capacitance
(Input-Output)
CI-O
Min. Typ.* Max. Units
Test Conditions
Fig. Note
2500
V rms HCPL-4506
RH < 50%,
6, 7, 8
HCPL-0466
t = 1 min.
5000
HCNW4506 TA = 25°C
6, 8, 13
Option 020
5000
HCNW4506
6, 8
12
10
Ω
HCPL-4506
VI-O = 500 Vdc
6
HCPL-0466
1012 1013
HCNW4506
0.6
pF
HCPL-4506
f = 1 MHz
6
HCPL-0466
0.5
HCNW4506
*All typical values at 25°C, VCC = 15 V.
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.
Notes:
1. Derate linearly above 90°C free-air
temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air
temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air
temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air
temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in
percent is defined as the ratio of
output collector current (IO) to the
forward LED input current (IF) times
100.
6. Device considered a two-terminal
device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8
shorted together.
7. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% Production test shown in the
VDE 0884 Insulation Related
Characteristics Table, if applicable.
1-56
8. For option 020, in accordance with
UL 1577, each optocoupler is proof
tested by applying an insulation test
voltage ≥ 6000 V rms for 1 second
(leakage detection current limit, II-O
≤ 5 µA). This test is performed before
the 100% Production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Related
Characteristics Table, if applicable.
9. Pulse: f = 20 kHz, Duty Cycle = 10%.
10. The internal 20 kΩ resistor can be
used by shorting pins 6 and 7
together.
11. Due to tolerance of the internal
resistor, and since propagation delay
is dependent on the load resistor
value, performance can be improved
by using an external 20 kΩ 1% load
resistor. For more information on
how propagation delay varies with
load resistance, see Figure 12.
12. The RL = 20 kΩ, CL = 100 pF load
represents a typical IPM (Intelligent
Power Module) load.
13. See Option 020 data sheet for more
information.
14. Use of a 0.1 µF bypass capacitor
connected between pins 5 and 8 can
improve performance by filtering
power supply line noise.
15. The difference between tPLH and tPHL
between any two devices under the
same test condition. (See IPM Dead
Time and Propagation Delay
Specifications section.)
16. Common mode transient immunity in
a Logic High level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic High
state (i.e., VO > 3.0 V).
17. Common mode transient immunity in
a Logic Low level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low
state (i.e., VO < 1.0 V).
18. Pulse Width Distortion (PWD) is
defined as |tPHL - tPLH| for any given
device.
8
6
4
VO = 0.6 V
2
0
100 °C
25 °C
-40 °C
0
5
10
15
1.00
0.95
0.90
IF = 10 mA
VO = 0.6 V
0.85
0.80
-40
20
-20
IF – FORWARD CURRENT – mA
TA = 25°C
IF
+
VF
–
10
1.0
0.1
0.01
0.001
1.10
1.20
1.30
1.40
80
100
1.50
1.60
15.0
4.5 V
30 V
10.0
5.0
0
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE – °C
Figure 7. High Level Output
Current vs. Temperature.
TA = 25 °C
10
IF
+
1
VF
–
0.1
0.01
0.001
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VF – INPUT FORWARD VOLTAGE – V
Figure 8. HCPL-4506 and HCPL-0466
Input Current vs. Forward Voltage.
1
VF = 0.8 V
VCC = VO = 4.5 V OR 30 V
100
VF – FORWARD VOLTAGE – VOLTS
Figure 9. HCNW4506 Input Current
vs. Forward Voltage.
8
20 kΩ
0.1 µF
20 kΩ
IF(ON) =10 mA
+
–
7
2
+
60
Figure 6. Normalized Output Current
vs. Temperature.
IF – INPUT FORWARD CURRENT – mA
Figure 5. Typical Transfer
Characteristics.
100
40
20.0
TA – TEMPERATURE – °C
IF – FORWARD LED CURRENT – mA
1000
20
0
IOH – HIGH LEVEL OUTPUT CURRENT – µA
1.05
NORMALIZED OUTPUT CURRENT
IO – OUTPUT CURRENT – mA
10
If
VCC = 15 V
5V
–
3
6
tf
VO
VOUT
tr
90%
90%
10%
10%
CL *
4
5
SHIELD
*TOTAL LOAD CAPACITANCE
VTHHL
VTHLH
tPHL
tPLH
Figure 10. Propagation Delay Test Circuit.
1-57
1
0.1 µF
20 kΩ
IF
2
B
VCM
8
δV = VCM
δt
∆t
20 kΩ
7
+
–
A
3
6
4
5
VCC = 15 V
OV
∆t
VOUT
100 pF*
+
VO
*100 pF TOTAL
CAPACITANCE
–
VCC
SWITCH AT A: IF = 0 mA
SHIELD
VFF
VO
VOL
+
–
SWITCH AT B: IF = 10 mA
VCM = 1500 V
Figure 11. CMR Test Circuit. Typical CMR Waveform.
500
300
tPLH
tPHL
200
100
-40
-20
0
20
40
60
80
(INTERNAL)
300
tPLH
tPHL
200
100
-40
100
TA – TEMPERATURE – °C
800
1000
400
200
0
100
200
300
400
500
CL – LOAD CAPACITANCE – pF
Figure 15. Propagation Delay vs. Load
Capacitance.
1-58
80
400
tPLH
tPHL
200
100
0
500
600
400
200
5
10
15
20
25
VCC – SUPPLY VOLTAGE – V
Figure 16. Propagation Delay vs.
Supply Voltage.
30
40
50
Figure 14. Propagation Delay vs. Load
Resistance.
800
0
20
10
RL – LOAD RESISTANCE – K Ω
IF = 10 mA
CL = 100 pF
RL = 20 kΩ
TA = 25°C
tPLH
tPHL
1200
600
0
60
Figure 13. Propagation Delay with
Internal 20 kΩ RL vs. Temperature.
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
1000
40
1400
IF = 10 mA
VCC = 15 V
RL = 20 kΩ
TA = 25°C
tPLH
tPHL
1200
20
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25 °C
600
TA – TEMPERATURE – °C
Figure 12. Propagation Delay with
External 20 kΩ RL vs. Temperature.
1400
0
-20
tP – PROPAGATION DELAY – ns
400
800
IF = 10 mA
VCC = 15 V
CL = 100 pF
400 RL = 20 kΩ
tP – PROPAGATION DELAY – ns
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
500
30
VCC = 15 V
CL = 100 pF
RL = 20 kΩ
TA = 25°C
400
tPLH
tPHL
300
200
100
0
5
10
15
20
IF – FORWARD LED CURRENT – mA
Figure 17. Propagation Delay vs. Input
Current.
OUTPUT POWER – PS, INPUT CURRENT – IS
OUTPUT POWER – PS, INPUT CURRENT – IS
HCPL-4506 OPTION 060
800
PS (mW)
700
IS (mA)
600
500
400
300
(230)
200
100
0
0
50
25
75 100 125 150 175 200
HCNW4506
1000
PS (mW)
900
1
8
IS (mA)
800
20 kΩ
CLEDP
700
2
7
600
500
3
6
CLEDN
400
300
4
200
5
SHIELD
100
0
0
25
50
75
100 125 150 175
TS – CASE TEMPERATURE – °C
TS – CASE TEMPERATURE – °C
Figure 20. Optocoupler Input to
Output Capacitance Model for
Unshielded Optocouplers.
Figure 18. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per VDE 0884.
1
1
8
2
310 Ω
CLEDP
20 kΩ
CLED02
+
– VCC = 15 V
7
7
CLED01
20 kΩ
0.1 µF
20 kΩ
+5 V
2
8
3
6
CLEDN
3
6
VOUT
CMOS
4
5
SHIELD
100 pF
4
5
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 21. Optocoupler Input to
Output Capacitance Model for
Shielded Optocouplers.
Figure 19. Recommended LED Drive Circuit.
1
ITOTAL*
1
310 Ω
8
+5 V
0.1 µF
20 kΩ
310 Ω
2
ICLEDP
2
IF
CLED02
CLEDP
3
+
– VCC = 15 V
6
6
4
5
VOUT
100 pF
100 pF
5
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
+
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 22. LED Drive Circuit with Resistor Connected to LED
Anode (Not Recommended).
VOUT
CLEDN
–
3
7
CLED01
4
CMOS
20 kΩ
ICLED01
20 kΩ
7
8
20
kΩ
VCM
Figure 23. AC Equivalent Circuit for Figure 22 During
Common Mode Transients.
1-59
1
2
8
CLEDP
1
20
kΩ
CLED02
20 kΩ
20 kΩ
7
CLED01
310 Ω
CLEDN
3
6
7
3
6
Q1
100 pF
4
2
VOUT
ICLEDN*
+ VR** –
8
+5 V
5
4
SHIELD
5
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.
Figure 25. Not Recommended Open
Collector LED Drive Circuit.
–
+
VCM
Figure 24. AC Equivalent Circuit for Figure 19 During
Common Mode Transients.
1
2
8
CLEDP
20
kΩ
CLED02
20 kΩ
7
1
CLED01
Q1
CLEDN
3
8
+5 V
6
VOUT
ICLEDN*
20 kΩ
2
7
3
6
100 pF
4
5
SHIELD
4
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
–
+
5
SHIELD
VCM
Figure 27. Recommended LED Drive
Circuit for Ultra High CMR.
Figure 26. AC Equivalent Circuit for Figure 25 During
Common Mode Transients.
HCPL-4506
8
1
I
20 kΩ
LED1
2
+5 V
VCC1
0.1 µF
IPM
20 kΩ
7
+HV
310 Ω
3
6
4
5
VOUT1
CMOS
Q1
M
SHIELD
Q2
HCPL-4506
8
1
I
20 kΩ
LED2
2
+5 V
VCC2
0.1 µF
7
HCPL-4506
HCPL-4506
20 kΩ
HCPL-4506
310 Ω
3
6
4
5
CMOS
HCPL-4506
HCPL-4506
SHIELD
Figure 28. Typical Application Circuit.
1-60
VOUT2
-HV
ILED1
Q1 OFF
ILED1
VOUT1
VOUT2
Q1 ON
Q2 OFF
Q2 ON
Q1 OFF
VOUT1
VOUT2
Q1 ON
ILED2
Q2 OFF
tPLH
Q2 ON
MIN.
tPLH
MAX.
ILED2
PDD*
MAX.
tPLH MAX.
tPHL
MIN.
tPHL
MAX.
tPHL
MIN.
MAX.
DEAD TIME
PDD* MAX. =
(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
*PDD = PROPAGATION DELAY DIFFERENCE
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
Figure 29. Minimum LED Skew for Zero Dead Time.
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 30. Waveforms for Dead Time Calculation.
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive coupling
from the input side of the optocoupler, through the package, to
the detector IC as shown in
Figure 20. The HCPL-4506,
HCPL-0466 and HCNW4506
improve CMR performance by
using a detector IC with an optically transparent Faraday shield,
which diverts the capacitively
coupled current away from the
sensitive IC circuitry. However,
this shield does not eliminate the
capacitive coupling between the
LED and the optocoupler output
pins and output ground as shown
in Figure 21. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes keeping the LED in the proper state
(on or off) during common mode
transients. For example, the
recommended application circuit
(Figure 19), can achieve 15 kV/µs
CMR while minimizing component
complexity. Note that a CMOS
gate is recommended in Figure 19
to keep the LED off when the gate
is in the high state.
Another cause of CMR failure for
a shielded optocoupler is direct
coupling to the optocoupler
output pins through CLEDO1 and
CLEDO2 in Figure 21. Many factors
influence the effect and magnitude of the direct coupling including: the use of an internal or
external output pull-up resistor,
the position of the LED current
setting resistor, the connection of
the unused input package pins,
and the value of the capacitor at
the optocoupler output (CL).
Techniques to keep the LED in
the proper state and minimize the
effect of the direct coupling are
discussed in the next two
sections.
CMR with the LED On
(CMRL )
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. The recommended
minimum LED current of 10 mA
provides adequate margin over
the maximum ITH of 5.0 mA (see
Figure 5) to achieve 15 kV/µs
CMR. Capacitive coupling is
higher when the internal load
resistor is used (due to CLEDO2)
and an IF = 16 mA is required to
obtain 10 kV/µs CMR.
The placement of the LED current
setting resistor effects the ability of
the drive circuit to keep the LED on
during transients and interacts with
the direct coupling to the
optocoupler output. For example,
the LED resistor in Figure 22 is
connected to the anode. Figure 23
shows the AC equivalent circuit for
Figure 22 during common mode
transients. During a +dVcm/dt in
Figure 23, the current available at
the LED anode (Itotal) is limited by
the series resistor. The LED current
(IF) is reduced from its DC value by
an amount equal to the current that
flows through CLEDP and CLEDO1.
The situation is made worse
1-61
because the current through CLEDO1
has the effect of trying to pull the
output high (toward a CMR failure)
at the same time the LED current is
being reduced. For this reason, the
recommended LED drive circuit
(Figure 19) places the current setting resistor in series with the LED
cathode. Figure 24 is the AC equivalent circuit for Figure 19 during
common mode transients. In this
case, the LED current is not
reduced during a +dVcm/dt transient because the current flowing
through the package capacitance is
supplied by the power supply.
During a -dVcm/dt transient, however, the LED current is reduced by
the amount of current flowing
through CLEDN. But, better CMR
performance is achieved since the
current flowing in CLEDO1 during a
negative transient acts to keep the
output low.
Coupling to the LED and output
pins is also affected by the connection of pins 1 and 4. If CMR is
limited by perturbations in the LED
on current, as it is for the recommended drive circuit (Figure 19),
pins 1 and 4 should be connected to
the input circuit common. However,
if CMR performance is limited by
direct coupling to the output when
the LED is off, pins 1 and 4 should
be left unconnected.
CMR with the LED Off
(CMRH)
A high CMR LED drive circuit must
keep the LED off (VF ≤ VF(OFF))
during common mode transients.
For example, during a +dVcm/dt
transient in Figure 24, the current
flowing through CLEDN is supplied
by the parallel combination of the
LED and series resistor. As long as
the voltage developed across the
resistor is less than VF(OFF) the LED
will remain off and no common
mode failure will occur. Even if the
LED momentarily turns on, the 100
pF capacitor from pins 6-5 will
keep the output from dipping below
the threshold. The recommended
LED drive circuit (Figure 19) provides about 10 V of margin between
the lowest optocoupler output
voltage and a 3 V IPM threshold
1-62
during a 15 kV/µs transient with
VCM = 1500 V. Additional margin
can be obtained by adding a diode
in parallel with the resistor, as
shown by the dashed line connection in Figure 24, to clamp the
voltage across the LED below
VF(OFF).
Since the open collector drive circuit, shown in Figure 25, cannot
keep the LED off during a +dVcm/
dt transient, it is not desirable for
applications requiring ultra high
CMRH performance. Figure 26 is
the AC equivalent circuit for Figure
25 during common mode
transients. Essentially all the
current flowing through CLEDN
during a +dVcm/dt transient must
be supplied by the LED. CMRH
failures can occur at dV/dt rates
where the current through the LED
and CLEDN exceeds the input
threshold. Figure 27 is an
alternative drive circuit which does
achieve ultra high CMR
performance by shunting the LED
in the off state.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-4506, HCPL-0466 and
HCNW4506 include a Propagation
Delay Difference specification
intended to help designers minimize
“dead time” in their power inverter
designs. Dead time is the time
period during which both the high
and low side power transistors (Q1
and Q2 in Figure 28) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents flowing
through the power devices between
the high and low voltage motor rails.
To minimize dead time the designer
must consider the propagation
delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay
characteristics of the optocoupler
(the characteristics of the IPM
IGBT gate drive circuit can be
analyzed in the same way) it is
important to know the minimum
and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay
specifications, preferably over the
desired operating temperature
range.
The limiting case of zero dead time
occurs when the input to Q1 turns
off at the same time that the input
to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
turn-on, which is related to the
worst case optocoupler propagation
delay waveforms, as shown in
Figure 29. A minimum dead time of
zero is achieved in Figure 29 when
the signal to turn on LED2 is
delayed by (tPLH max - tPHL min) from
the LED1 turn off. Note that the
propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under
consideration are typically mounted
in close proximity to each other.
(Specifically, tPLH max and tPHL min
in the previous equation are not the
same as the tPLH max and tPHL min,
over the full operating temperature
range, specified in the data sheet.)
This delay is the maximum value for
the propagation delay difference
specification which is specified at
450 ns for the HCPL-4506, HCPL0466 and HCNW4506 over an
operating temperature range of
-40°C to 100°C.
Delaying the LED signal by the
maximum propagation delay difference ensures that the minimum
dead time is zero, but it does not
tell a designer what the maximum
dead time will be. The maximum
dead time occurs in the highly
unlikely case where one optocoupler with the fastest tPLH and another
with the slowest tPHL are in the
same inverter leg. The maximum
dead time in this case becomes the
sum of the spread in the tPLH and
tPHL propagation delays as shown in
Figure 30. The maximum dead time
is also equivalent to the difference
between the maximum and minimum propagation delay difference
specifications. The maximum dead
time (due to the optocouplers) for
the HCPL-4506, HCPL-0466 and
HCNW4506 is 600 ns (= 450 ns (-150 ns)) over an operating
temperature range of -40°C to
100°C.