TI1 LM3642TLE-LT Synchronous boost led flash driver Datasheet

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LM3642
SNVS891H – SEPTEMBER 2012 – REVISED SEPTEMBER 2015
LM3642 1.5-A Synchronous Boost LED Flash Driver With High-Side Current Source
1 Features
3 Description
•
•
The LM3642 is a 4-MHz fixed-frequency synchronous
boost converter plus 1.5-A constant current driver for
a high-current white LED. The high-side current
source allows for grounded cathode LED operation
providing Flash current up to 1.5 A. An adaptive
regulation method ensures the current source
remains in regulation and maximizes efficiency.
1
•
•
•
•
•
•
•
•
•
1.5-A High-Side Current Source for Single LED
> 85% Efficiency in Torch Mode (at 100 mA) and
Flash Mode (at 1 A to 1.5 A)
Accurate Programmable Flash LED Current from
93 mA to 1.5 A
Accurate Programmable Torch LED Currents:
– 48.4 mA to 375 mA
– 24 mA to 187 mA (LT option)
Small Solution Size: < 20 mm2
Soft-Start Operation for Battery Protection
Hardware Strobe Enable
Synchronization Input for RF Power Amplifier
Pulse Events
VIN Flash Monitor Optimization
400-kHz I2C-Compatible Interface
0.5-mm Pitch, 9-Bump DSBGA
The LM3642 is controlled via an I2C-compatible
interface. Features include a hardware flash enable
(STROBE) allowing a logic input to trigger the flash
pulse as well as a TX input which forces the flash
pulse into a low-current Torch Mode, allowing for
synchronization to RF power amplifier events or other
high-current conditions.
The 4-MHz switching frequency, overvoltage
protection and adjustable current limit settings allow
the use of tiny, low-profile inductors and (10-µF)
ceramic capacitors. The device is available in a small
9-bump DSBGA package and operates over the
−40°C to 85°C temperature range.
2 Applications
Device Information(1)
Camera Phone LED Flash
PART NUMBER
LM3642
PACKAGE
BODY SIZE (MAX)
DSBGA (9)
1.69 mm × 1.64 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1 PH
IN
2.5V to 5.5V
SW
OUT
10 PF
10 PF
STROBE
TX/TORCH
SDA
SCL
LED
GND
Flash
LED
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3642
SNVS891H – SEPTEMBER 2012 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
7.5 Programming........................................................... 12
7.6 Register Map........................................................... 15
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Community Resources..........................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (December 2014) to Revision H
Page
•
Changed Handling Ratings table to ESD Ratings table per SDS format; move Storage Temp to Abs Max table ............... 4
•
Added "If an I2C command is used to terminate the flash event, TI recommends selecting a flash time-out level 100
ms above the desired flash duration ." to end of Flash Time-Out subsection...................................................................... 10
Changes from Revision F (December 2013) to Revision G
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Added updated full Thermal Information ............................................................................................................................... 4
Changes from Revision E (May 2013) to Revision F
•
2
Page
Deleted TX interrupt ............................................................................................................................................................... 9
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5 Pin Configuration and Functions
YZR Package
9-Pin DSBGA
Top View
Top View
A1
A2
A3
B1
B2
B3
C1
C2
C3
Pin Functions
PIN
NO.
NAME
A1
OUT
I/O
DESCRIPTION
Power
Step-up DC-DC converter output. Connect a 10-µF ceramic capacitor between this pin
and GND.
A2
SW
Power
Drain connection for internal NMOS and synchronous PMOS switches.
A3
GND
Ground
Ground
B1
LED
Output
High-side current source output for Flash LED.
B2
STROBE
Input
Active high hardware Flash enable. Drive STROBE high to turn on Flash pulse. Has an
internal pulldown resistor of 300 kΩ between STROBE and GND.
B3
IN
Power
Input voltage connection. Connect IN to the input supply, and bypass to GND with a 10µF or larger ceramic capacitor.
C1
TX/TORCH
Input
C2
SDA
Input/Output
C3
SCL
Input
Configurable power amplifier synchronization input or configurable active high Torch
enable. Has an internal pulldown resistor of 300 kΩ between TX and GND.
Serial data input/output.
Serial clock input.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
VIN, VSW,VOUT
MIN
MAX
UNIT
–0.3
6
V
–0.3
the lesser of (VIN+0.3) w/
Vmax
V
VSCL, VSDA, VSTROBE, VTX, VLED
Continuous power dissipation (4)
Internally limited
Junction temperature (TJ-MAX)
150
−65
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
°C
See (5)
Maximum lead temperature (soldering)
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typical) and
disengages at TJ = 135°C (typical). Thermal shutdown is verified by design.
For detailed soldering specifications and information, refer to Texas Instruments Application Note 1112: DSBGA Wafer Level Chip Scale
Package (SNVA009).
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
VALUE
UNIT
±2000
V
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
2.5
5.5
V
Junction temperature (TJ)
–40
125
°C
Ambient temperature (TA) (2)
–40
85
°C
(1)
(2)
UNIT
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
6.4 Thermal Information
LM3642
THERMAL METRIC (1)
YZR (DSBGA)
UNIT
9 PINS
RθJA
Junction-to-ambient thermal resistance
100.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.7
°C/W
RθJB
Junction-to-board thermal resistance
16.4
°C/W
ψJT
Junction-to-top characterization parameter
3.2
°C/W
ψJB
Junction-to-board characterization parameter
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
MIN and MAX limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C). Unless otherwise
specified, TA = 25°C, VIN = 3.6 V. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1-A flash, VOUT = 4 V
–6%
1.04
6%
A
1.5-A flash, VOUT = 4 V
–8%
1.5
8%
A
–10%
24
10%
mA
–10%
mA
CURRENT SOURCE SPECIFICATIONS
ILED
Current source accuracy
24-mA torch, VOUT = 4 V
(LM3642-LT)
48.4 mA Torch, VOUT = 4 V
48.4
10%
Flash
275
12%
ILED = 24 mA/48.4 mA
Torch
150
15%
VHR
Current source regulation
voltage
ILED = 1.5 A
VOVP
Output overvoltage protection
trip point
ON threshold
–2.8%
5
2.2%
OFF threshold
–2.7%
4.88
2.3%
mV
V
STEP-UP DC-DC CONVERTER SPECIFICATIONS
RPMOS
PMOS switch on-resistance
IPMOS = 1 A
120
RNMOS
NMOS switch on-resistance
INMOS = 1 A
90
ICL
Input current limit
VIVFM
Input voltage flash monitor trip
threshold
UVLO
Undervoltage threhold
ƒSW
Switching frequency
IQ
Quiescent supply current
Device not switching pass mode
ISB
Standby supply current
Device disabled 2.5 V ≤ VIN ≤ 5.5 V
tTX
Flash-to-torch LED current
settling time
TX low to high
ILED = 1.5 A to 24 mA/48.4 mA
Falling VIN
mΩ
–17%
1.6
15%
–17%
1.88
15%
–3.2%
2.9
3.2%
V
–4%
2.8
4%
V
4
9%
MHz
–9%
0.75
1.6
A
mA
4
4
µA
µs
STROBE, TX VOLTAGE SPECIFICATIONS
VIL
Input logic low
2.5 V ≤ VIN ≤ 5.5 V
0
0.4
VIH
Input logic high
2.5 V ≤ VIN ≤ 5.5 V
1.2
VIN
V
I2C-COMPATIBLE INTERFACE SPECIFICATIONS (SCL, SDA)
VIL
Input logic low
2.5 V ≤ VIN ≤ 5.5 V
0
0.4
VIH
Input logic high
2.5 V ≤ VIN ≤ 4.2 V
1.2
VIN
VOL
Output logic low
ILOAD = 3 mA
(1)
(2)
400
V
mV
All voltages are with respect to the potential at the GND pin.
Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but
do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = 3.6 V and TA = 25°C.
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6.6 Timing Requirements
See Figure 1.
MIN
NOM
MAX
UNIT
t1
SCL clock frequency
2.4
ns
t2
Data In setup time to SCL High
100
ns
t3
Data out stable after SCL Low
0
ns
t4
SDA low setup time to SCL low (start)
100
ns
t5
SDA high hold time after SCL high (stop)
100
ns
t1
SCL
t5
t4
SDA_IN
t2
SDA_OUT
t3
Figure 1. I2C-Compatible Interface Specifications
6
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1.50
0.400
1.45
0.393
1.40
0.386
LED CUURENT (A)
LED CURRENT (A)
6.7 Typical Characteristics
1.35
1.30
1.25
1.20
1.15
+25°C
+85°C
- 40°C
1.10
1.05
0.379
0.372
0.365
0.358
0.351
0.344
0.337
0.330
2.8 3.0 3.2 3.4 3.5 3.7 3.9 4.0 4.2 4.4 4.5
VIN(V)
1.00
2.5 2.7 2.9 3.1 3.2 3.4 3.6 3.7 3.9 4.1 4.2
VIN (V)
Figure 2. Flash LED Current vs. VIN
VLED = 3.8 V, ILED = 1.5 A
Figure 3. Torch LED Current vs. VIN
VLED = 3.7 V, ILED = 375 mA
0.40
1.60
0.38
1.5A
HEADROOM VOLTAGE (V)
1.54
LED CURRENT (A)
1.48
1.42
1.36
1.4A
1.31A
1.30
1.24
1.22A
1.18
1.12
1.06
0.35
0.33
0.30
0.28
0.25
0.23
0.20
0.18
1.1125A
1.00
2.8 3.1 3.4 3.7 3.9 4.2 4.5 4.7 5.0 5.3 5.5
VIN (V)
+25°C
+85°C
-40°C
0.15
2.8 3.0 3.1 3.3 3.4 3.5 3.7 3.8 4.0 4.1 4.2
VIN (V)
Figure 5. Flash Headroom Voltage vs. VIN
VLED = 3.8 V, ILED = 1 A
Figure 4. High Codes Flash LED Current vs. VIN
VLED = 3.8 V, Temp = 25°C
0.20
5.30
0.19
5.27
0.18
5.24
OUTPUT VOLTAGE (V)
HEADROOM VOLTAGE (V)
+25°C
+85°C
-40°C
0.17
0.16
0.15
0.15
0.13
0.12
5.21
5.18
5.15
5.12
5.09
5.06
+25°C
+85°C
-40°C
0.11
5.03
0.10
2.5 2.7 2.9 3.1 3.2 3.4 3.6 3.7 3.9 4.1 4.2
VIN (V)
5.00
2.7 3.0 3.3 3.6 3.9 4.1 4.4 4.7 5.0 5.3 5.5
VIN (V)
Figure 6. Torch Headroom Voltage vs. VIN
VLED = 3.7 V, ILED = 375 mA
Figure 7. Output Voltage vs. VIN
VLED = 3.8 V
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2.25
1.80
2.20
1.79
PEAK INPUT CURRENT (A)
PEAK INPUT CURRENT (A)
Typical Characteristics (continued)
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
+25°C
+85°C
- 40°C
1.77
1.76
1.74
1.73
1.72
1.71
1.68
2.6 2.8 3.0 3.1 3.3 3.4 3.6 3.8 3.9 4.1 4.2
VIN (V)
2.6 2.8 3.0 3.1 3.3 3.4 3.6 3.8 3.9 4.1 4.2
VIN (V)
Figure 8. Peak Input Current Limit vs. VIN
VLED = 3.8V, IIN Setting = 1.9 A
Figure 9. Peak Input Current Limit vs. VIN
VLED = 3.8 V, IIN Setting = 1.7 A
2.00
SWITCHING FREQUENCY (MHZ)
4.10
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
+25°C
+85°C
-40°C
1.50
2.8 3.0 3.1 3.3 3.4 3.5 3.7 3.8 4.0 4.1 4.2
VIN (V)
4.09
4.08
4.07
4.06
4.05
4.04
+25°C
+85°C
- 40°C
4.03
4.02
4.01
4.00
Figure 10. Average Input Current Limit vs. VIN
VLED = 3.8 V, IIN Setting = 1.9 A
8
+25°C
+85°C
- 40°C
1.70
1.75
AVERAGE INPUT CURRENT (A)
1.78
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2.7 2.9 3.1 3.3 3.5 3.6 3.8 4.0 4.2 4.4 4.5
VIN (V)
Figure 11. Switching Frequency vs. VIN
VLED = 3.8 V
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7 Detailed Description
7.1 Overview
The LM3642 is a high-power white LED flash driver capable of delivering up to 1.5 A into a single high-powered
LED. The device incorporates a 4-MHz constant frequency-synchronous current-mode PWM boost converter and
a single high-side current source to regulate the LED current over the 2.5-V to 5.5-V input voltage range.
The LM3642 PWM converter switches and maintains at least VHR across the current source (LED). This
minimum headroom voltage ensures that the current source remains in regulation. If the input voltage is above
the LED voltage + current source headroom voltage, the device does not switch and turns the PFET on
continuously (Pass Mode). In Pass Mode the difference between (VIN – ILED × RPMOS) and the voltage across the
LED is dropped across the current source.
The LM3642 has two logic inputs including a hardware Flash Enable (STROBE) and a Flash Interrupt input
(TX/TORCH) designed to interrupt the flash pulse during high battery current conditions. Both logic inputs have
internal 300-kΩ (typical) pulldown resistors to GND.
Control of the LM3642 is done via an I2C-compatible interface. This includes adjustment of the Flash and Torch
current levels, changing the Flash Timeout Duration and changing the switch current limit. Additionally, there are
flag and status bits that indicate flash current time-out, LED failure (open/short), device thermal shutdown, and
VIN undervoltage conditions.
7.2 Functional Block Diagram
SW
Over Voltage
Comparator
4 MHz
Oscillator
VREF
+
-
IN
80 m:
Input Voltage
Flash Monitor
UVLO
VOVP
OUT
ILED
+
-
+
-
PWM
Control
80 m:
Thermal
Shutdown
+150oC
+
-
LED
Error
Amplifier
+
-
OUT-VHR
Current Sense/
Current Limit
Slope
Compensation
Soft-Start
SDA
2
SCL
I C
Interface
Control
Logic/
Registers
TORCH/TX
STROBE
GND
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7.3 Feature Description
7.3.1 Power Amplifier Synchronization (TX/TORCH)
The TX pin is a Power Amplifier Synchronization input. This is designed to reduce the flash LED current and thus
limit the battery current during high battery current conditions such as PA transmit events. When the LM3642 is
engaged in a Flash event, and the TX pin is pulled high, the LED current is forced into Torch Mode at the
programmed Torch current setting. If the TX pin is then pulled low before the Flash pulse terminates, the LED
current will return to the previous Flash current level. At the end of the Flash time-out whether the TX pin is high
or low, the LED current will turn off.
7.3.2 Input Voltage Flash Monitor (IVFM)
The LM3642 has the ability to adjust the flash current based upon the voltage level present at the IN pin utilizing
an Input Voltage Flash Monitor. Upon an IVFM event, the set voltage threshold from the IVFM Mode Register
sets the input voltage boundary that forces the LM3642 to stop ramping the flash current during start-up (Stop
and Hold Mode).
7.3.3 Fault and Protections
7.3.3.1 Fault Operation
Upon entering a fault condition, the LM3642 will set the appropriate flag in the Flags Register.
7.3.3.2 Flash Time-Out
The Flash Time-Out period sets the amount of time that the Flash Current is being sourced from the current
source (LED). The LM3642 has 8 time-out levels ranging 100 ms to 800 ms in 100-ms steps. The Flash TimeOut period is controlled in the Flash Features Register (0x08). Flash Time-Out only applies to the Flash Mode
operation. The mode bits in the Enable Register (0x0A) are cleared upon a Flash Time-out.
If an I2C command is used to terminate the flash event, TI recommends selecting a flash time-out level 100 ms
above the desired flash duration.
7.3.3.3 Overvoltage Protection (OVP)
The output voltage is limited to typically 5 V (see VOVP in Electrical Characteristics). In situations such as an open
LED, the LM3642 will raise the output voltage in order to keep the LED current at its target value. When VOUT
reaches 5 V (typ.) the overvoltage comparator will trip and turn off the internal NFET. When VOUT falls below the
VOVP Off Threshold, the LM3642 begins switching again. The mode bits in the Enable Register are not cleared
upon an OVP.
7.3.3.4 Current Limit
The LM3642 features selectable inductor current limits that are programmable through the Flash Feature
Register of the I2C-compatible interface. When the inductor current limit is reached, the LM3642 will terminate
the charging phase of the switching cycle.
Since the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the device
operates in Pass Mode. In Boost Mode or Pass Mode if VOUT falls below 2.3 V, the part stops switching, and the
PFET operates as a current source limiting the current to 300 mA. This prevents damage to the LM3642 and
excessive current draw from the battery during output short-circuit conditions. The mode bits in the Enable
Register (0x0A) are not cleared upon a Current Limit event.
NOTE
Pulling additional current from the VOUT node during normal operation is not
recommended.
10
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Feature Description (continued)
7.3.3.5 Undervoltage Lockout (UVLO)
The LM3642 has an internal comparator that monitors the voltage at IN which will force the LM3642 into
shutdown if the input voltage drops to 2.8 V. If the UVLO monitor threshold is tripped, the UVLO flag bit will be
set in the Flags Register. If the input voltage rises above 2.8 V, the LM3642 will not be available for operation
until there is an I2C read command initiated for the Flags Register. Upon a read, the flag register will be cleared,
and normal operation can resume. This feature can be disabled by writing a ‘0’ to the UVLO EN bit in the Input
Voltage Flash Monitor Register. The mode bits in the Enable Register are cleared upon a UVLO event.
7.3.3.6 Thermal Shutdown (TSD)
When the LM3642 device’s die temperature reaches 150°C the boost converter shuts down, and the NFET and
PFET turn off, as does the current source (LED). When the thermal shutdown threshold is tripped, a '1' gets
written to the corresponding bit of the Flags Register (Thermal Shutdown bit), and the LM3642 will go into
standby. The LM3642 will only be allowed to restart after the Flags Register is read, clearing the fault flag. Upon
restart, if the die temperature is still above 150°C, the LM3642 will reset the fault flag and re-enter standby. The
mode bits in the Enable Register are cleared upon a TSD.
7.3.3.7 LED and/or VOUT Fault
The LED Fault flag in the Flags Register reads back a '1' if the part is active in Flash or Torch Mode and the LED
output or the VOUT node experiences short condition. The LM3642 determines an LED open condition if the OVP
threshold is crossed at the OUT pin while the device is in Flash or Torch Mode. An LED short condition is
determined if the voltage at LED goes below 500 mV (typ.) while the device is in Torch or Flash Mode. There is a
delay of 256-μs deglitch time before the LED flag is valid and 2.048 ms before the VOUT flag is valid. This delay is
the time between when the Flash or Torch current is triggered and when the LED voltage and the output voltage
is sampled. The LED flag can be reset by reading back the flags register. The mode bits in the Enable Register
are cleared upon an LED and/or VOUT fault.
7.4 Device Functional Modes
7.4.1 Start-up (Enabling the Device)
Turnon of the LM3642 Torch and Flash Modes can be done through the Enable Register. On start-up, when
VOUT is less than VIN the internal synchronous PFET turns on as a current source and delivers 350 mA (typ.) to
the output capacitor. During this time the current source (LED) is off. When the voltage across the output
capacitor reaches 2.2V (typ.), the current source will turn on. At turnon the current source will step through each
Flash or Torch level until the target LED current is reached. This gives the device a controlled turnon and limits
inrush current from the VIN supply.
7.4.2 Pass Mode
The LM3642 starts up in Pass Mode and stays there until Boost Mode is needed to maintain regulation. If the
voltage difference between VOUT and VLED falls below VHR, the device switches to Boost Mode. In Pass Mode the
boost converter does not switch and the synchronous PFET turns fully on bringing VOUT up to VIN – ILED × RPMOS.
In Pass Mode the inductor current is not limited by the peak current limit. In this situation the output current must
be limited to 2 A.
7.4.3 Flash Mode
In Flash Mode, the LED current source (LED) provides 16 target current levels from 93.75 mA to 1500 mA. The
Flash currents are adjusted via the Current Control Register. Flash Mode is activated by the Enable Register, or
by pulling the STROBE pin HIGH. Once the Flash sequence is activated the current source (LED) will ramp up to
the programmed Flash current by stepping through all current steps until the programmed current is reached.
When the part is enabled in the Flash Mode through the Enable Register, all mode bits in the Enable Register
are cleared after a flash time-out event.
Table 1 shows the I2C commands and the state of the mode bits, if the STROBE pin is used to enable the Flash
Mode.
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Device Functional Modes (continued)
Table 1. Status of Mode Bits
MODE CHANGE REQUIRED
STATUS OF MODE BITS IN THE ENABLE REGISTER AFTER A FLASH
Using Level Triggered STROBE to Flash
Mode bits are cleared after a single flash. To reflash, 0x23 will have to be written
to 0x0A.
7.4.4 Torch Mode
In Torch Mode, the current source (LED) is programmed via the Current Control Register. Torch Mode is
activated by the Enable Register and/or by Enabling the part in TX/Torch pin configuration. Once the Torch Mode
is enabled the current source will ramp up to the programmed Torch current level. The Ramp-Up and RampDown times are independently adjustable via the Torch Ramp Register. Torch Mode is not affected by Flash
Timeout. In the LM3642, the programmable torch current ranges from 48.4 mA to 375 mA. With the LM3642LT
option, the programmable torch current ranges from 24 mA to 187 mA.
7.4.5 Indicator Mode
This mode is activated by the Enable Register. The LM3642 can be programmed to a current level that is 1/8th
the torch current value in the Current Control Register. LM3642LT has only one setting of indicator current at 5
mA.
7.5 Programming
7.5.1 I2C-Compatible Interface
7.5.1.1 Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when SCL is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 12. Data Validity Diagram
A pullup resistor between the controller's VIO line and SDA must be greater than [(VIO – VOL) / 3 mA] to meet
the VOL requirement on SDA. Using a larger pullup resistor results in lower switching current with slower edges,
while using a smaller pullup results in higher switching currents with faster edges.
7.5.1.2 Start and Stop Conditions
START and STOP conditions classify the beginning and the end of the I2C session. A START condition is
defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as
the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and
STOP conditions. The I2C bus is considered to be busy after a START condition and free after a STOP condition.
During data transmission, the I2C master can generate repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
12
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Programming (continued)
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 13. Start and Stop Conditions
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each
byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3642 pulls down
the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3642 generates an acknowledge
after each byte is received. There is no acknowledge created after data is read from the LM3642.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LM3642 7-bit address is 0x63. For the eighth bit, a '0' indicates
a WRITE and a '1' indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
ack from slave
ack from slave
start
msb Chip Address lsb
w
ack
msb Register Add lsb
ack
start
Id = 63h
w
ack
addr = 0Ah
ack
ack from slave
msb
DATA
lsb
ack
stop
ack
stop
SCL
SDA
Data = 03h
w = write (SDA = "0")
r = read (SDA = "1")
ack = acknowledge (SDA pulled down by either master or slave)
id = chip address, 63h for LM3642
Figure 14. Write Cycle
7.5.1.4 I2C-Compatible Chip Address
The device address for the LM3642 is 1100011 (63). After the START condition, the I2C-compatible master
sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE, and R/W = 1
indicates a READ. The second byte following the device address selects the register address to which the data
will be written. The third byte contains the data for the selected register.
MSB
1
Bit 7
LSB
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1
Bit 2
1
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Figure 15. I2C-Compatible Device Address
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Programming (continued)
7.5.1.5 Transferring Data
Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte
of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is
generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3642 pulls down
SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has
been received.
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7.6 Register Map
7.6.1 Register Descriptions
Internal Hex Address
Power On/RESET Value
Enable Register
Register Name
0x0A
00
Flags Register
0x0B
00
Flash Features Register
0x08
52
Current Control Register
0x09
0F
IVFM Mode Register
0x01
80
Torch Ramp Time Register
0x06
00
Silicon Revision Register (LM3642)
0x00
00
Silicon Revision Register (LM3642LT)
0x00
01
7.6.1.1 Enable Register (0x0A)
Bit 7
Bit 6
Bit 5
Bit 4
IVFM
0 = Disabled
(default)
1 = Stop and
Hold Mode
TX Pin Enable
0 = Disabled
(default)
1 = Enabled
Strobe Pin
Enable
0 = Disabled
(default)
1 = Enabled
Torch Pin
Enable
0 = Disabled
(default)
1 = Enabled
Bit 3
Bit 2
Bit 1
Bit 0
RFU
RFU
Mode Bits: M1, M0
00 = Standby (default)
01 = Indicator
10 = Torch
11 = Flash
7.6.1.2 Flags Register (0x0B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFU
RFU
IVFM
UVLO Flag
OVP Flag
LED or VOUT
Short Flag
Thermal
Shutdown Fault
Timeout Flag
IVFM
IVFM down threshold crossed.
UVLO Fault
UVLO Threshold crossed.
OVP Flag
Over-voltage Protection tripped. Open Output cap or open LED.
LED Short Fault
LED Short detected.
Thermal Shutdown Fault
LM3642 die temperature reached thermal shutdown value.
Time-Out Flag
Flash Timer tripped.
NOTE
Faults require a read-back of the “Flags Register” to resume operation. Flags report an
event occurred, but do not inhibit future functionality. A read-back of the Flags Register
will only get updated again if the fault or flags is still present upon a restart.
7.6.1.3 Flash Features Register (0x08)
Bit 7
RFU
Bit 6
Inductor
Current Limit
0 = 1.6 A
1 = 1.88 A
(default)
Bit 5
Bit 4
Bit 3
Flash Ramp Time
000 = 256 µs
001 = 512 µs
010 = 1.024 ms (default)
011 = 2.048 ms
100 = 4.096 ms
101 = 8.192 ms
110 = 16.384 ms
111 = 32.768 ms
Bit 2
Bit 1
Bit 0
Flash Time-Out Time
000 = 100 ms
001 = 200 ms
010 = 300 ms (default)
011 = 400 ms
100 = 500 ms
101 =600 ms
110 = 700 ms
111 = 800 ms
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7.6.1.4 Current Control Register (0x09)
Bit 7
RFU
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Flash Current
0000 = 93.75 mA
0001 = 187.5 mA
0010 = 281.25 mA
0011 = 375 mA
0100 = 468.75 mA
0101 = 562.5 mA
0110 = 656.25 mA
0111 = 750 mA
1000 = 843.75 mA
1001 = 937.5 mA
1010 = 1031.25 mA
1011 = 1125 mA
1100 = 1218.75 mA
1101 = 1312.5 mA
1110 = 1406.25 mA
1111 = 1500 mA (default)
Torch Current (LM3642LT)
000 = 48.4 mA (default) (24 mA)
001 =93.74 mA (46.87 mA)
010 =140.63 mA (70.315 mA)
011 = 187.5 mA (93.25 mA)
100 =234.38 mA (117.19 mA)
101 = 281.25 mA (140.625 mA)
110 = 328.13 mA (164.075 mA)
111 = 375 mA (187.5 mA)
7.6.1.5 Input Voltage Flash Monitor (IVFM) Mode Register (0x01)
Bit 7
Bit 6
UVLO
0 = Disabled
1= Enabled
(default)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IVM-D (Down) Threshold
000 = 2.9 V (default)
001 = 3.0 V
010 =3.1 V
011 = 3.2 V
100 = 3.3 V
101 = 3.4 V
110 = 3.5 V
111 = 3.6 V
RFU
Bit 0
RFU
Stop and Hold Mode: Stops Current Ramp and Holds the level for the remaining flash if VIN crosses IVM-D Line.
Sets IVFM Flag in Flags Register upon crossing IVM-D Line.
UVLO EN:
If enabled and VIN drops below 2.8 V, the LM3642 will enter standby and set the UVLO flag in the
Flags Register. Enabled = ‘1’, Disabled = ‘0’
IFLASH
ILED
0 mA
VIN
IVM-D
Deglitch
time
t
Figure 16. Stop and Hold Mode
16
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7.6.1.6 Torch Ramp Time Register (0x06)
Bit 7
RFU
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Torch Ramp-Up Time
000 = 16 ms (default)
001 = 32 ms
010 = 64 ms
011 = 128 ms
100 = 256 ms
101 = 512 ms
110 = 1.024s
111 = 2.048s
RFU
Bit 1)
Bit 0
Torch Ramp-Down Time
000 = 16 ms (default)
001 = 32 ms
010 = 64 ms
011 = 128 ms
100 = 256 ms
101 = 512 ms
110 = 1.024s
111 = 2.048s
7.6.1.7 Silicon Revision Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RFU
Bit 2
Bit 1
Bit 0
000 = LM3642
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3642 can drive one flash LED at currents up to 1.5 A. The 4-MHz DC-DC boost regulator allows for the
use of small value discrete external components.
8.2 Typical Application
1 PH
IN
2.5V to 5.5V
SW
OUT
10 PF
10 PF
LED
STROBE
TX/TORCH
SDA
SCL
Flash
LED
GND
Figure 17. Typical Application Circuit
8.2.1 Design Requirements
Example requirements based on default register values:
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 5.5 V
Brightness control
I2C Register
LED configuration
1 Flash LED
Boost switching frequency
4 MHz
Flash brightness
1.5 A maximum
Table 3. Application Circuit Component List
COMPONENT
L
COUT
CIN
LED
18
MANUFACTUR
ER
TOKO
Murata
VALUE
1 µH
10 µF
Lumiled
SIZE
CURRENT/VOLTAGE
RATING (RESISTANCE)
2 mm × 1.6 mm × 1 mm
2.5 A
1.6 mm × 0.8 mm × 0.8 mm
(0603)
6.3 V
PART NUMBER
DFE201610C
GRM188R60J106M
PWF-4
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Capacitor Selection
The LM3642 is designed to operate with at least a 10-µF ceramic output capacitor. When the boost converter is
running the output capacitor supplies the load current during the boost converter's on-time. When the NMOS
switch turns off the inductor energy is discharged through the internal PMOS switch, supplying power to the load
and restoring charge to the output capacitor. This causes a sag in the output voltage during the on-time and a
rise in the output voltage during the off-time. The output capacitor is therefore chosen to limit the output ripple to
an acceptable level depending on load current and input/output voltage differentials and also to ensure the
converter remains stable.
For proper operation the output capacitor must be at least a 10-µF ceramic. Larger capacitors such as a 22-µF
capacitor or capacitors in parallel can be used if lower output voltage ripple is desired. To estimate the output
voltage ripple considering the ripple due to capacitor discharge (ΔVQ) and the ripple due to the capacitors ESR
(ΔVESR) use the following equations:
For continuous conduction mode, the output voltage ripple due to the capacitor discharge is:
ILED x (VOUT - VIN)
'VQ =
fSW x VOUT x COUT
(1)
The output voltage ripple due to the output capacitors ESR is found by:
'VESR = R ESR x §
©
where
'IL =
I LED x VOUT·
VIN
¹
+ 'I L
VIN x (VOUT - VIN )
2 x f SW x L x VOUT
(2)
In ceramic capacitors the ESR is very low so a close approximation is to assume that 80% of the output voltage
ripple is due to capacitor discharge and 20% from ESR. Table 4 lists different manufacturers for various output
capacitors and their case sizes suitable for use with the LM3642.
8.2.2.2 Input Capacitor Selection
Choosing the correct size and type of input capacitor helps minimize the voltage ripple caused by the switching
of the LM3642 device’s boost converter, and reduces noise on the boost converter's input terminal that can feed
through and disrupt internal analog signals. In the typical application circuit a 10-µF ceramic input capacitor
works well. It is important to place the input capacitor as close as possible to the LM3642 device’s input (IN) pin.
This reduces the series resistance and inductance that can inject noise into the device due to the input switching
currents. Table 4 lists various input capacitors that are recommended for use with the LM3642.
Table 4. Recommended Input and Output Capacitors (X5R/X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
VOLTAGE RATING
TDK Corporation
C1608JB0J106M
10 µF
0603 (1.6 mm × 0.8 mm × 0.8 mm)
6.3 V
TDK Corporation
C2012JB1A106M
10 µF
0805 (2 mm × 1.25 mm × 1.25 mm)
10 V
TDK Corporation
C2012JB0J226M
22 µF
0805 (2 mm × 1.25 mm × 1.25 mm)
6.3 V
Murata
GRM188R60J106M
10 µF
0603 (1.6 mm × 0.8 mm × 0.8 mm)
6.3 V
Murata
GRM21BR61A106KE19
10 µF
0805 (2 mm × 1.25 mm × 1.25 mm)
10 V
Murata
GRM21BR60J226ME39L
22 µF
0805 (2 mm × 1.25 mm × 1.25 mm)
6.3 V
8.2.2.3 Inductor Selection
The LM3642 is designed to use a 1-µH or 0.47-µH inductor. Table 5 lists various inductors and their
manufacturers that can work well with the LM3642. When the device is boosting (VOUT > VIN) the inductor will
typically be the largest area of efficiency loss in the circuit. Therefore, choosing an inductor with the lowest
possible series resistance is important. Additionally, the saturation rating of the inductor should be greater than
the maximum operating peak current of the LM3642. This prevents excess efficiency loss that can occur with
inductors that operate in saturation. For proper inductor operation and circuit performance, ensure that the
inductor saturation and the peak current limit setting of the LM3642 are greater than IPEAK in the following
calculation:
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IPEAK =
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I LOAD VOUT
V x (VOUT - VIN)
x
+ 'IL where 'IL = IN
K
VIN
2 x f SW x L x VOUT
(3)
where ƒSW = 4 MHz, and efficiency can be found in the Typical Characteristics plots.
Table 5. Recommended Inductors
MANUFACTURER
L
PART NUMBER
DIMENSIONS (L×W×H)
ISAT
RDC
TOKO
1 µH
TOKO
1 µH
DFE252010C
2.5 mm × 2 mm × 1 mm
2.7 A
78 mΩ
DFE252012C
2.5 mm × 2 mm × 1.2 mm
3A
TOKO
59 mΩ
0.47 µH
DFE201612C
2 mm × 1.6 mm × 1.2 mm
3.4 A
82 mΩ
TOKO
1 µH
DFE201610C
2 mm × 1.6 mm × 1 mm
2.5 A
79 mΩ
8.2.3 Application Curves
100
100
90
80
LED EFFICIENCY (%)
LED EFFICIENCY (%)
90
70
60
50
40
30
+25°C
+85°C
-40°C
70
60
50
40
20
10
3.5
80
+25°C
+85°C
-40°C
30
3.8
4.0
4.3
4.5
VIN (V)
4.8
5.0
2.8 3.0 3.1 3.3 3.4 3.5 3.7 3.8 4.0 4.1 4.2
VIN (V)
Figure 18. Flash LED Efficiency vs. VIN
VLED = 3.8 V, ILED = 1.5 A
VIN
200 mV/
DIV
500 mA/
DIV
Figure 19. Torch LED Efficiency vs. VIN
VLED = 3.7 V, ILED = 375 mA
VOUT
5V/DIV
IIN
500 mA/
DIV
ILED
500 mA/
DIV
ILED
200 ms/DIV
200 s/DIV
Figure 20. Input Voltage Flash Monitor Stop and Hold
Mode with Default Settings
20
Figure 21. Flash Mode to Torch Mode Transition
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VOUT
5V/DIV
VOUT
5V/DIV
IIN
500 mA/
DIV
IIN
500 mA/
DIV
ILED
500 mA/
DIV
ILED
500 mA/
DIV
200 ms/DIV
200 ms/DIV
Figure 22. Torch Mode to Flash Mode Transition
Figure 23. Indicator Mode - Torch Mode - Flash Mode
Transitions
IIN
IIN
VOUT
VOUT
5V/DIV
5V/DIV
500 mA/
DIV
ILED
500 mA/
DIV
ILED
500 mA/
DIV
500 mA/
DIV
2 ms/DIV
2 ms/DIV
Figure 25. VOUT Short Fault
Figure 24. VLED Short Fault
TX
2V/DIV
IIN
500 mA/
DIV
LED
500 mA/
DIV
CURRENT
100 ms/DIV
Figure 26. TX Transition Plot Behavior of LED Current Shown on Enabling the Part in a TX Event and Upon TX Interrupting
During a Flash
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9 Power Supply Recommendations
The LM3642 is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input
supply must be well regulated and capable to supply the required input current. If the input supply is located far
from the LM3642 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
The high switching frequency and large switching currents of the LM3642 make the choice of layout important.
The following steps should be used as a reference to ensure the device is stable and maintains proper LED
current regulation across its intended operating voltage and current range.
1. Place CIN on the top layer (same layer as the LM3642 and as close to the device as possible. The input
capacitor conducts the driver currents during the low side MOSFET turn-on and turn-off and can see current
spikes over 1 A in amplitude. Connecting the input capacitor through short wide traces to both the IN and
GND pins will reduce the inductive voltage spikes that occur during switching and which can corrupt the VIN
line.
2. Place COUT on the top layer (same layer as the LM3642) and as close as possible to the OUT and GND pin.
The returns for both CIN and COUT should come together at one point, and as close to the GND pin as
possible. Connecting COUT through short wide traces will reduce the series inductance on the OUT and GND
pins that can corrupt the VOUT and GND line and cause excessive noise in the device and surrounding
circuitry.
3. Connect the inductor on the top layer close to the SW pin. There should be a low-impedance connection
from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the
SW node should be small so as to reduce the capacitive coupling of the high dV/dt present at SW that can
couple into nearby traces.
4. Avoid routing logic traces near the SW node so as to avoid any capacitively coupled voltages from SW onto
any high-impedance logic lines such as STROBE, SDA, and SCL. A good approach is to insert an inner layer
GND plane underneath the SW node and between any nearby routed traces. This creates a shield from the
electric field generated at SW.
5. Terminate the Flash LED cathodes directly to the GND pin of the LM3642. If possible, route the LED returns
with a dedicated path so as to keep the high amplitude LED currents out of the GND plane. For Flash LEDs
that are routed relatively far away from the LM3642, a good approach is to sandwich the forward and return
current paths over the top of each other on two layers. This will help in reducing the inductance of the LED
current paths.
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10.2 Layout Example
SW
10 PF
OUT
OUT
SW
1 P+
VIAs to GND
Plane
GND
10 PF
LED
TX/
TORCH
LED
STROBE
IN
IN
TX/
TORCH
SDA
SCL
SCL
SDA
Figure 27. Typical Layout of LM3642
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments Application Note 1112: DSBGA Wafer Level Chip Scale Package (SNVA009).
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LM3642
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM3642TLE-LT/NOPB
ACTIVE
DSBGA
YZR
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(D2 ~ D4)
LM3642TLE/NOPB
ACTIVE
DSBGA
YZR
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
D2
LM3642TLX-LT/NOPB
ACTIVE
DSBGA
YZR
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(D2 ~ D4)
LM3642TLX/NOPB
ACTIVE
DSBGA
YZR
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM3642TLE-LT/NOPB
DSBGA
YZR
9
250
178.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.78
1.78
0.76
4.0
8.0
Q1
LM3642TLE/NOPB
DSBGA
YZR
9
250
178.0
8.4
1.78
1.78
0.76
4.0
8.0
Q1
LM3642TLX-LT/NOPB
DSBGA
YZR
9
3000
178.0
9.2
1.76
1.81
0.75
4.0
8.0
Q1
LM3642TLX-LT/NOPB
DSBGA
YZR
9
3000
178.0
8.4
1.78
1.78
0.76
4.0
8.0
Q1
LM3642TLX/NOPB
DSBGA
YZR
9
3000
178.0
8.4
1.78
1.78
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3642TLE-LT/NOPB
DSBGA
YZR
9
250
210.0
185.0
35.0
LM3642TLE/NOPB
DSBGA
YZR
9
250
210.0
185.0
35.0
LM3642TLX-LT/NOPB
DSBGA
YZR
9
3000
220.0
220.0
35.0
LM3642TLX-LT/NOPB
DSBGA
YZR
9
3000
210.0
185.0
35.0
LM3642TLX/NOPB
DSBGA
YZR
9
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0009xxx
D
0.600±0.075
E
TLA09XXX (Rev C)
D: Max = 1.69 mm, Min = 1.63 mm
E: Max = 1.64 mm, Min = 1.58 mm
4215046/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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