CY7S1041G CY7S1041GE 4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) 4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) Features Deep-Sleep input (DS) must be deasserted HIGH for normal operating mode. ■ High speed ❐ Access time (tAA) = 10 ns / 15 ns ■ Ultra-low power Deep-Sleep (DS) current ❐ IDS = 15 µA ■ Low active and standby currents ❐ Active Current ICC = 38-mA typical ❐ Standby Current ISB2 = 6-mA typical ■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V ■ Embedded ECC for single-bit error correction[1] ■ 1.0-V data retention ■ TTL- compatible inputs and outputs ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA Functional Description The CY7S1041G is a high-performance PowerSnooze™ static RAM organized as 256K words × 16 bits. This device features fast access times (10 ns) and a unique ultra-low power Deep-Sleep mode. With Deep-Sleep mode currents as low as 15 µA, the CY7S1041G/ CY7S1041GE devices combine the best features of fast and low- power SRAMs in industry-standard package options. The device also features embedded ECC. logic which can detect and correct single-bit errors in the accessed location. To perform data writes, assert the Chip Enable (CE) and Write Enable (WE) inputs LOW, and provide the data and address on device data pins (I/O0 through I/O15) and address pins (A0 through A17) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Chip Enable (CE) and Output Enable (OE) inputs LOW and provide the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location The device is placed in a low-power Deep-Sleep mode when the Deep-Sleep input (DS) is asserted LOW. In this state, the device is disabled for normal operation and is placed in a low power data retention mode. The device can be activated by deasserting the Deep-Sleep input (DS) to HIGH. The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA and 44-pin (400-mil) Molded SOJ. Product Portfolio Power Dissipation Product [2] Range CY7S1041G(E)18 CY7S1041G(E)30 VCC Range (V) 1.65 V–2.2 V Industrial Speed (ns) 15 Operating ICC, (mA) f = fmax Deep-Sleep current (µA) Typ [3] Max Typ [3] Max Typ [3] Max – 40 6 8 – 15 2.2 V–3.6 V 10 38 45 4.5–5.5 V 10 38 45 CY7S1041G(E) Standby, ISB2 (mA) Notes 1. This device does not support automatic write back on error detection. 2. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V), VCC = 3 V (for VCC range of 2.2 V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 001-92576 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 19, 2015 CY7S1041G CY7S1041GE Logic Block Diagram – CY7S1041G / CY7S1041GE MEMORY ARRAY ECC DECODER ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 INPUT BUFFER SENSE AMPLIFIERS ECC ENCODER ERR (Optional) I/O0‐I/O7 I/O8‐I/O15 A10 A11 A12 A13 A14 A15 A16 A17 COLUMN DECODER BHE WE DS POWER MANAGEMENT BLOCK Document Number: 001-92576 Rev. *E OE CE2 CE1 BLE Page 2 of 21 CY7S1041G CY7S1041GE Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Loads and Waveforms ....................................... 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 Deep-Sleep Mode Characteristics ................................... 9 AC Switching Characteristics ....................................... 10 Switching Waveforms .................................................... 11 Truth Table ...................................................................... 15 ERR Output – CY7S1041GE ........................................... 15 Document Number: 001-92576 Rev. *E Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 16 Package Diagrams .......................................................... 17 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC® Solutions ...................................................... 21 Cypress Developer Community ................................. 21 Technical Support ..................................................... 21 Page 3 of 21 CY7S1041G CY7S1041GE Pin Configurations Figure 1. 44-pin TSOP II pinout, CY7S1041G A0 A1 A2 A3 A4 /CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 /WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 /OE /BHE /BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 /DS A14 A13 A12 A11 A10 Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable without ERR, CY7S1041G [4], Package/Grade ID: BVJXI [6] with ERR, CY7S1041GE [4, 5], Package/Grade ID: BVJXI [6] 1 2 BLE OE I/O8 3 4 5 6 1 2 A0 A1 A2 DS A BLE OE BHE A3 A4 CE I/O0 B I/O8 I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC VCC I/O12 NC A16 I/O4 I/O14 I/O13 A14 A15 I/O15 NC A12 NC A8 A9 3 4 5 6 A0 A1 A2 DS A BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C D VSS I/O11 A17 A7 I/O3 VCC D VSS E VCC I/O12 ERR A16 I/O4 VSS E I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 G A10 A11 NC H NC A8 A9 A10 A11 NC H Notes 4. NC pins are not connected internally to the die. 5. ERR is an output pin. 6. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls are swapped. Document Number: 001-92576 Rev. *E Page 4 of 21 CY7S1041G CY7S1041GE Pin Configurations (continued) Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable without ERR, CY7S1041G [7], Package/Grade ID: BVXI [9] with ERR, CY7S1041GE [7, 8], Package/Grade ID: BVXI [9] 1 2 BLE OE I/O 0 3 4 5 6 A0 A1 A2 DS BHE A3 A4 CE I/O 1 I/O 2 A5 A6 VSS I/O 3 A 17 VCC I/O 4 I/O 6 1 2 A BLE OE I/O 8 B I/O0 I/O 10 I/O 9 C A7 I/O 11 VCC NC A 16 I/O 12 I/O 5 A 14 A 15 I/O 7 NC A 12 NC A8 A9 3 4 5 6 A0 A1 A2 DS A BHE A3 A4 CE I/O8 B I/O1 I/O2 A5 A6 I/O10 I/O9 C D VSS I/O3 A17 A7 I/O11 VCC D VSS E VCC I/O4 ERR A16 I/O12 VSS E I/O 13 I/O 14 F I/O6 I/O5 A14 A15 I/O13 I/O14 F A 13 WE I/O 15 G I/O7 NC A12 A13 WE I/O15 G A 10 A 11 NC H NC A8 A9 A10 A11 NC H Notes 7. NC pins are not connected internally to the die. 8. ERR is an output pin. 9. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls are swapped. Document Number: 001-92576 Rev. *E Page 5 of 21 CY7S1041G CY7S1041GE DC input voltage [10] ........................... –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Ambient temperature with power applied ................................... –55 C to +125 C Operating Range Supply voltage on VCC relative to GND [10] .........................–0.5 V to + 6.0 V Range Ambient Temperature VCC DC voltage applied to outputs in HI-Z State [10] .................................. –0.5 V to VCC + 0.5 V Industrial –40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the Operating Range of –40 C to +85 C Parameter VOH VOL VIH[10, 12] VIL [10, 12] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Test Conditions 10 ns/ 15 ns Min Typ[11] Max 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – – 2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.2 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC-0.5[13] – – 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 3.6 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4 1.65 V to 2.2 V 1.4 – VCC + 0.2 2.2 V to 2.7 V 2 – VCC + 0.3 2.7 V to 3.6 V 2 – VCC + 0.3 3.6 V to 5.5 V 2.2 – VCC + 0.5 Input LOW voltage 1.65 V to 2.2 V –0.2 – 0.4 2.2 V to 2.7 V –0.3 – 0.6 2.7 V to 3.6 V –0.3 – 0.8 3.6 V to 5.5 V Unit V V V V –0.5 – 0.8 IIX Input leakage current GND < VIN < VCC –1 – +1 A IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, CMOS levels f = 100 MHz – 38 45 f = 66.7 MHz – 40 40 mA ISB1 Standby current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – – 15 mA ISB2 Standby current – CMOS inputs Max VCC, CE > VCC – 0.2 V, DS > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 6 8 mA IDS Deep-Sleep current Max VCC, CE > VCC – 0.2 V, DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – – 15 µA Notes 10. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 2 ns. 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V), VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C. 12. For the DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V. 13. This parameter is guaranteed by design and not tested. Document Number: 001-92576 Rev. *E Page 6 of 21 CY7S1041G CY7S1041GE Capacitance Parameter [14] Description CIN Input capacitance COUT I/O capacitance Test Conditions All packages Unit 10 pF 10 pF TA = 25 C, f = 1 MHz, VCC(typ) Thermal Resistance Parameter [14] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA 44-pin TSOP II Unit Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 31.35 68.85 C/W 14.74 15.97 C/W AC Test Loads and Waveforms Figure 6. AC Test Loads and Waveforms [15] HI-Z Characteristics: VCC 50 Output VTH Z0 = 50 R1 Output 30 pF* * Including JIG and Scope (a) * Capacitive Load Consists of all Components of the Test Environment R2 5 pF* (b) All Input Pulses VHIGH GND 90% 90% 10% Rise Time: > 1 V/ns 10% (c) Fall Time: > 1 V/ns Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317 R2 1538 351 351 VTH VCC/2 1.5 1.5 V VHIGH 1.8 3.0 3.0 V Notes 14. Tested initially and after any design or process changes that may affect these parameters. 15. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) or 100-s wait time after VCC stabilization. Document Number: 001-92576 Rev. *E Page 7 of 21 CY7S1041G CY7S1041GE Data Retention Characteristics Over the Operating Range of –40C to +85 C Parameter Conditions[16] Description VDR VCC for data retention ICCDR Data retention current tCDR [17] Chip deselect to data retention time tR[17, 18] Operation recovery time Min Max Unit 1.0 – V – 8 mA 0 – ns 2.2 V < VCC < 5.5 V 10 – ns VCC < 2.2 V 15 – ns VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 7. Data Retention Waveform [18] VCC VCC(min) DATA RETENTION MODE VDR = 1.0 V tCDR VCC(min) tR CE Notes 16. DS signal must be HIGH during Data Retention Mode. 17. These parameters are guaranteed by design 18. Full-device operation requires linear VCC ramp from VDR to VCC(min) 100 s or stable at VCC(min) 100 s. Document Number: 001-92576 Rev. *E Page 8 of 21 CY7S1041G CY7S1041GE Deep-Sleep Mode Characteristics Over the Operating Range of –40 C to +85 C Parameter Description Conditions VCC = VCC (max), DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Max Unit – 15 µA IDS Deep-Sleep mode current tPDS[19] Minimum time for DS to be LOW for part to successfully exit Deep-Sleep mode 100 – ns tDS[20] DS assertion to Deep-Sleep mode transition time – 1 ms tDSCD[19] DS deassertion to chip disable If tPDS > tPDS(min) – 100 s If tPDS < tPDS(min) – 0 s tDSCA DS deassertion to chip access If tPDS > tPDS(min) (Active/Standby) If tPDS < tPDS(min) 300 – s Figure 8. Active, Standby, and Deep-Sleep Operation Modes Chip Access Allowed Not Allowed CE ENABLE/ DISABLE DON’T CARE Allowed DISABLE ENABLE/ DISABLE tPDS DS tDS Mode Active/Standby Mode Standby Mode tDSCD Deep Sleep Mode tDSCA Standby Mode Active/Standby Mode Note 19. CE must be pulled HIGH within tDSCD time of DS deassertion to avoid SRAM data loss. 20. After assertion of DS signal, device will take a maximum of tDS time to stabilize to Deep-Sleep current IDS. During this period, DS signal must continue to be asserted to logic level LOW to keep the device in Deep-Sleep mode. Document Number: 001-92576 Rev. *E Page 9 of 21 CY7S1041G CY7S1041GE AC Switching Characteristics Over the Operating Range of –40 C to +85 C Parameter [21] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tRC Read cycle time 10 – 15 – ns tAA Address to data valid – 10 – 15 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data valid – 10 – 15 ns tDOE OE LOW to data valid – 4.5 – 8 ns 0 – 0 – ns – 5 – 8 ns 3 – 3 – ns – 5 – 8 ns 0 – 0 – ns – 10 – 15 ns tLZOE OE LOW to low impedance tHZOE [22, 23, 24] OE HIGH to HI-Z tLZCE CE LOW to low impedance tHZCE CE HIGH to HI-Z [22, 23, 24] tPU CE LOW to power-up [22, 23, 24] [22, 23, 24] [ 24] [ 24] tPD CE HIGH to power-down tDBE Byte enable to data valid – 4.5 – 8 ns tLZBE Byte enable to low impedance [22, 23, 24] 0 – 0 – ns – 6 – 8 ns tHZBE Write Cycle Byte disable to HI-Z [22, 23, 24] [25, 26] tWC Write cycle time 10 – 15 – ns tSCE CE LOW to write end 7 – 12 – ns tAW Address setup to write end 7 – 12 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns [22, 23, 24] tLZWE WE HIGH to low impedance 3 – 3 – ns tHZWE WE LOW to HI-Z [22, 23, 24] – 5 – 8 ns tBW Byte Enable to End of Write 7 – 12 – ns Notes 21. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 6 on page 7, unless specified otherwise. 22. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 6 on page 7. Transition is measured 200 mV from steady state voltage. 23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 24. These parameters are guaranteed by design 25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and BHE or BLE = VIL. WE, CE, BHE and BLE signals must be LOW and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be the sum of tHZWE and tSD. Document Number: 001-92576 Rev. *E Page 10 of 21 CY7S1041G CY7S1041GE Switching Waveforms Figure 9. Read Cycle No. 1 of CY7S1041G (Address Transition Controlled) [27, 28, 29] tRC ADDRESS tAA tOHA PREVIOUS DATAOUT VALID DATA I/O DATAOUT VALID Figure 10. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [27, 28, 29] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 27. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL. 28. WE is HIGH for read cycle. 29. DS is HIGH for chip access. Document Number: 001-92576 Rev. *E Page 11 of 21 CY7S1041G CY7S1041GE Switching Waveforms (continued) Figure 11. Read Cycle No. 3 (OE Controlled) [30, 31, 32] ADDRESS tRC CE tPD t HZCE t ACE OE t HZOE t DOE t LZOE BHE / BLE DATA I /O t DBE t LZBE HIGH IMPEDANCE t HZBE DATA OUT VALID HIGH IMPEDANCE t LZCE tPU VCC SUPPLY CURRENT ISB Notes 30. WE is HIGH for read cycle. 31. Address valid prior to or coincident with CE LOW transition. 32. DS must be HIGH for chip access Document Number: 001-92576 Rev. *E Page 12 of 21 CY7S1041G CY7S1041GE Switching Waveforms (continued) Figure 12. Write Cycle No. 1 (CE Controlled) [33, 34, 35] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE/ BLE OE tHZOE tHD tSD DATA I/O DATAIN VALID Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [33, 34, 35, 36] tW C AD D R E S S tS C E CE tB W B H E/ BLE tS A tA W tH A tP W E WE t H ZW E D ATA I/O tS D t LZW E tH D D A TA IN V A LID Notes 33. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and BHE or BLE = VIL. WE, CE, BHE and BLE signals must be LOW and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 34. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 35. DS must be HIGH for chip access. 36. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 001-92576 Rev. *E Page 13 of 21 CY7S1041G CY7S1041GE Switching Waveforms (continued) Figure 14. Write Cycle No. 3 (WE Controlled) [37, 38, 39] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE tB W B H E /B L E OE tH Z O E D A T A I/O tH D tS D Note 40 D A T A IN V A L ID Figure 15. Write Cycle No. 4 (BLE or BHE Controlled) [37, 38, 39] tW C ADDRESS t SCE CE t AW t SA t HA tBW BHE/ BLE t PW E WE t HZW E DATA I/O Note 40 t SD t HD t LZW E DATA IN VALID Notes 37. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and BHE or BLE = VIL. WE, CE, BHE and BLE signals must be LOW and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 38. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or DS = VIL or BHE, and/or BLE = VIH. 39. DS must be HIGH for chip access. 40. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-92576 Rev. *E Page 14 of 21 CY7S1041G CY7S1041GE Truth Table DS CE OE [41] X WE BLE BHE [41] [41] [41] HIGH-Z HIGH-Z Standby Standby (ISB) X X X I/O0–I/O7 I/O8–I/O15 Mode Power H H H L L H L L Data out Data out Read all bits Active (ICC) H L L H L H Data out HI-Z Read lower bits only Active (ICC) H L L H H L HI-Z Data out Read upper bits only Active (ICC) H L X L L L Data in Data in Write all bits Active (ICC) H L X L L H Data in HI-Z Write lower bits only Active (ICC) H L X L H L HI-Z Data in Write upper bits only Active (ICC) H L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC) L[42] X X X X X HI-Z HI-Z Deep-Sleep Deep-Sleep Ultra Low Power (IDS) ERR Output – CY7S1041GE Output [43] Mode 0 Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. HI-Z Device deselected or outputs disabled or Write operation Notes 41. The input voltage levels on these pins should be either at VIH or VIL. 42. VIL on DS must be < 0.2 V. 43. ERR is an Output pin.If not used, this pin should be left floating. Document Number: 001-92576 Rev. *E Page 15 of 21 CY7S1041G CY7S1041GE Ordering Information Speed (ns) 10 Voltage Range 2.2 V–3.6 V 4.5 V–5.5 V Ordering Code Package Diagram Package Type (All Pb-free) CY7S1041GE30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output CY7S1041G30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm) CY7S1041G30-10ZSXI 51-85087 44-pin TSOP II CY7S1041G-10ZSXI 51-85087 44-pin TSOP II Operating Range Industrial Ordering Code Definitions CY 7 S 1 04 1 G E 30 - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = BV or ZS BV = 48-ball VFBGA; ZS = 44-pin TSOP II Speed: 10 ns Voltage Range: No digits or 30 or 18 No digits = 4.5 V to 5.5 V; 30 = 2.2 V to 3.6 V;18 = 1.65 V to 2.2 V ERR output Process Technology: Revision Code “G” = 65 nm Technology Data Width: 1 = × 16-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family S = Deep-Sleep feature Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-92576 Rev. *E Page 16 of 21 CY7S1041G CY7S1041GE Package Diagrams Figure 16. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-92576 Rev. *E Page 17 of 21 CY7S1041G CY7S1041GE Package Diagrams (continued) Figure 17. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-92576 Rev. *E Page 18 of 21 CY7S1041G CY7S1041GE Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degrees Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere ECC Error Correcting Code s microsecond I/O Input/Output mA milliampere OE Output Enable mm millimeter SRAM Static Random Access Memory ns nanosecond TSOP Thin Small Outline Package ohm TTL Transistor-Transistor Logic % percent VFBGA Very Fine-Pitch Ball Grid Array pF picofarad WE Write Enable V volt W watt Document Number: 001-92576 Rev. *E Symbol Unit of Measure Page 19 of 21 CY7S1041G CY7S1041GE Document History Page Document Title: CY7S1041G/CY7S1041GE, 4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) Document Number: 001-92576 Rev. ECN No. Orig. of Change Submission Date *D 4867081 NILE 07/31/2015 Changed status from Preliminary to Final. *E 5020880 VINI 11/19/2015 Updated Pin Configurations: Removed 44-pin SOJ package related information. Updated Thermal Resistance: Removed 44-pin SOJ package related information. Added 48-ball VFBGA package related information. Updated Ordering Information: Updated part numbers. Updated Ordering Code Definitions. Updated Package Diagrams: Removed spec 51-85082 *E. Document Number: 001-92576 Rev. *E Description of Change Page 20 of 21 CY7S1041G CY7S1041GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2014-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-92576 Rev. *E Revised November 19, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21