Cypress CY7C1311JV18-300BZXC 18-mbit qdr ii sram 4-word burst architecture Datasheet

CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
®
18-Mbit QDR II SRAM 4-Word
Burst Architecture
Features
Configurations
■
Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
CY7C1311JV18 – 2M x 8
■
300 MHz Clock for High Bandwidth
CY7C1313JV18 – 1M x 18
■
4-word Burst for reducing Address Bus Frequency
CY7C1315JV18 – 512K x 36
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
Functional Description
■
Two Input Clocks (K and K) for Precise DDR Timing
❐ SRAM uses rising edges only
■
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
■
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■
Single Multiplexed Address Input Bus latches Address Inputs
for both Read and Write Ports
■
Separate Port Selects for Depth Expansion
■
Synchronous Internally Self-timed Writes
■
QDR® II Operates with 1.5 Cycle Read Latency when the Delay
Lock Loop (DLL) is enabled
■
Operates like a QDR I device with 1 Cycle Read Latency in
DLL Off Mode
■
Available in x8, x9, x18, and x36 configurations
■
Full Data Coherency, providing most current Data
■
Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD
The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and
CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR II architecture. QDR II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR II architecture has
separate data inputs and data outputs to eliminate the need to
‘turnaround’ the data bus required with common IO devices.
Access to each port is accomplished through a common address
bus. Addresses for read and write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
QDR II read and write ports are completely independent of one
another. In order to maximize data throughput, both read and
write ports are provided with DDR interfaces. Each address
location is associated with four 8-bit words (CY7C1311JV18) or
9-bit words (CY7C1911JV18) or 18-bit words (CY7C1313JV18)
or 36-bit words (CY7C1315JV18) that burst sequentially into or
out of the device. Because data is transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus ‘turnarounds’.
■
Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable Drive HSTL Output Buffers
■
JTAG 1149.1 Compatible Test Access Port
■
Delay Lock Loop (DLL) for Accurate Data Placement
CY7C1911JV18 – 2M x 9
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
250 MHz
Unit
300
250
MHz
x8
730
665
mA
Maximum Operating Frequency
Maximum Operating Current
Cypress Semiconductor Corporation
Document Number: 001-12562 Rev. *D
•
x9
735
675
x18
790
705
x36
895
830
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 04, 2009
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Logic Block Diagram (CY7C1311JV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
512K x 8 Array
K
CLK
Gen.
Write
Reg
512K x 8 Array
K
Write
Reg
512K x 8 Array
Address
Register
Write
Reg
512K x 8 Array
A(18:0)
19
8
Write Add. Decode
D[7:0]
19
A(18:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
32
VREF
WPS
16
Control
Logic
Reg.
16
NWS[1:0]
Reg.
CQ
Reg. 8
8
8
8
8
Q[7:0]
Logic Block Diagram (CY7C1911JV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
512K x 9 Array
K
CLK
Gen.
Write
Reg
512K x 9 Array
K
Write
Reg
512K x 9 Array
Address
Register
Write
Reg
512K x 9 Array
A(18:0)
19
9
Write Add. Decode
D[8:0]
19
A(18:0)
RPS
Control
Logic
Read Data Reg.
C
C
CQ
36
VREF
WPS
18
Control
Logic
BWS[0]
Document Number: 001-12562 Rev. *D
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q[8:0]
Page 2 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Logic Block Diagram (CY7C1313JV18)
DOFF
Address
Register
Read Add. Decode
Write
Reg
256K x 18 Array
K
CLK
Gen.
Write
Reg
256K x 18 Array
K
Write
Reg
256K x 18 Array
Address
Register
Write
Reg
256K x 18 Array
A(17:0)
18
18
Write Add. Decode
D[17:0]
18
A(17:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
72
VREF
WPS
36
Control
Logic
Reg.
36
BWS[1:0]
Reg.
CQ
Reg. 18
18
18
18
18
Q[17:0]
Logic Block Diagram (CY7C1315JV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
128K x 36 Array
K
CLK
Gen.
Write
Reg
128K x 36 Array
K
Write
Reg
128K x 36 Array
Address
Register
Write
Reg
128K x 36 Array
A(16:0)
17
36
Write Add. Decode
D[35:0]
17
A(16:0)
RPS
Control
Logic
Read Data Reg.
C
C
CQ
144
VREF
WPS
72
Control
Logic
BWS[3:0]
Document Number: 001-12562 Rev. *D
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q[35:0]
Page 3 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Pin Configuration
The pin configuration for CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 follow. [1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1311JV18 (2M x 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NWS1
K
NC/144M
RPS
A
NC/36M
CQ
B
NC
NC
NC
A
NC/288M
K
NWS0
A
NC
NC
Q3
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1911JV18 (2M x 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NC
K
NC/144M
RPS
A
NC/36M
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D4
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
D2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D1
N
NC
D8
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q8
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Note
1. NC/36M, NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-12562 Rev. *D
Page 4 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Pin Configuration
The pin configuration for CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 follow. [1] (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1313JV18 (1M x 18)
1
2
3
NC/144M NC/36M
4
5
6
7
8
9
10
11
WPS
BWS1
K
NC/288M
RPS
A
NC/72M
CQ
A
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
9
10
CY7C1315JV18 (512K x 36)
1
2
4
5
6
7
8
WPS
BWS2
K
BWS1
RPS
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
Q28
D19
VSS
A
NC
A
VSS
D16
Q7
D8
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
A
CQ
B
Q27
Q18
C
D27
D
E
F
3
NC/288M NC/72M
Document Number: 001-12562 Rev. *D
11
NC/36M NC/144M
CQ
Page 5 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C1311JV18 − D[7:0]
CY7C1911JV18 − D[8:0]
CY7C1313JV18 − D[17:0]
CY7C1315JV18 − D[35:0]
WPS
InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1
InputNibble Write Select 0, 1 − Active LOW (CY7C1311JV18 Only). Sampled on the rising edge of the K
Synchronous and K clocks during write operations. Used to select which nibble is written into the device during the
current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1911JV18 − BWS0 controls D[8:0]
CY7C1313JV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315JV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M x 8 (4 arrays each of 512K x 8) for CY7C1311JV18, 2M x 9 (4 arrays each of 512K x 9) for
CY7C1911JV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313JV18 and 512K x 36 (4 arrays each
of 128K x 36) for CY7C1315JV18. Therefore, only 19 address inputs are needed to access the entire
memory array of CY7C1311JV18 and CY7C1911JV18, 18 address inputs for CY7C1313JV18 and 17
address inputs for CY7C1315JV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
OutputData Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1311JV18 − Q[7:0]
CY7C1911JV18 − Q[8:0]
CY7C1313JV18 − Q[17:0]
CY7C1315JV18 − Q[35:0]
RPS
InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of four sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See Application Example on page 10 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See Application Example on page 10 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
Document Number: 001-12562 Rev. *D
Page 6 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Pin Definitions
Pin Name
(continued)
IO
Pin Description
CQ
Echo Clock
CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 23.
CQ
Echo Clock
CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 23.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off differs from those listed in this data sheet. For normal operation, this pin is
connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR I mode when
the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR
I timing.
TDO
Output
TCK
Input
TDO for JTAG.
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
InputReference
VDD
Supply
Power Supply Inputs to the Core of the Device.
VSS
Ground
Ground for the Device.
VDDQ
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-12562 Rev. *D
Page 7 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Functional Overview
The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18,
CY7C1315JV18 are synchronous pipelined Burst SRAMs with a
read port and a write port. The read port is dedicated to read
operations and the write port is dedicated to write operations.
Data flows into the SRAM through the write port and flows out
through the read port. These devices multiplex the address
inputs in order to minimize the number of address pins required.
By having separate read and write ports, the QDR II completely
eliminates the need to ‘turnaround’ the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1311JV18, four 9-bit data transfers in the case of
CY7C1911JV18, four 18-bit data transfers in the case of
CY7C1313JV18, and four 36-bit data transfers in the case of
CY7C1315JV18 in two clock cycles.
This device operates with a read latency of one and a half cycles
when the DOFF pin is tied HIGH. When the DOFF pin is set LOW
or connected to VSS the device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single
clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1313JV18 is described in the following sections. The same
basic descriptions apply to CY7C1311JV18, CY7C1911JV18,
and CY7C1315JV18.
Read Operations
The CY7C1313JV18 is organized internally as four arrays of
256K x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the read
address register. Following the next K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the output clock (C or C, or
K or K when in single clock mode). In order to maintain the
internal logic, enable each read access to complete. Each read
access consists of four 18-bit data words and takes two clock
cycles to complete. Therefore, read accesses to the device
Document Number: 001-12562 Rev. *D
cannot be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second read request. Read
accesses are initiated on every other K clock rise. Doing so
pipelines the data flow such that data is transferred out of the
device on every rising edge of the output clocks (C and C, or K
and K when in single clock mode).
When the read port is deselected, the CY7C1311JV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive output clock (C). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
in the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses are
initiated on every other rising edge of the positive input clock (K).
Doing so pipelines the data flow such that 18 bits of data are
transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1311JV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the byte write select input during the data portion of a
write latches the data being presented and writes it into the
device. Deasserting the byte write select input during the data
portion of a write enables the data stored in the device for that
byte to remain unaltered. This feature is used to simplify read,
modify, or write operations to a byte write operation.
Single Clock Mode
The CY7C1311JV18 is used with a single clock that controls both
the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both
the input and output registers. This operation is identical to the
operation if the device had zero skew between the K/K and C/C
clocks. All timing parameters remain the same in this mode. To
use this mode of operation, tie C and C HIGH at power on. This
function is a strap option and not alterable during device
operation.
Page 8 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Concurrent Transactions
Programmable Impedance
The read and write ports on the CY7C1311JV18 operate independently of one another. As each port latches the address inputs on
different clock edges, the user reads or writes to any location,
regardless of the transaction on the other port. If the ports access
the same location when a read follows a write in successive clock
cycles, the SRAM delivers the most recent information
associated with the specified address location. This includes
forwarding data from a write cycle that was initiated on the
previous K clock rise.
Connect an external resistor, RQ, between the ZQ pin on the
SRAM and VSS to enable the SRAM to adjust its output driver
impedance. The value of RQ is five times the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15 percent is between 175Ω and 350Ω, with VDDQ = 1.5V.
The output impedance is adjusted every 1024 cycles upon power
up to account for drifts in supply voltage and temperature.
Schedule read accesses and write access such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations cannot be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
cannot be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in
alternating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C1311JV18 has a port select input for each port. This
enables easy depth expansion. Both port selects are sampled on
the rising edge of the positive input clock only (K). Each port
select input deselects the specified port. Deselecting a port does
not affect the other port. All pending transactions (read and write)
are completed before the device is deselected.
Document Number: 001-12562 Rev. *D
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the QDR II. In single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in the
Switching Characteristics on page 23.
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the DLL is locked after 1024
cycles of stable clock. The DLL is also reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. Disable the DLL by
applying ground to the DOFF pin. When the DLL is turned off,
the device behaves in QDR I mode (with one cycle latency and
a longer access time). For information refer to the application
note DLL Considerations in QDRII/DDRII.
Page 9 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Application Example
Figure 1 shows four QDR II used in an application.
Figure 1. Application Example
SRAM #1
R
P
S
#
Vt
D
A
R
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
C C# K K#
R = 250ohms
SRAM #4
R
P
S
#
D
A
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
R
W
P
S
#
B
W
S
#
ZQ R = 250ohms
CQ/CQ#
Q
C C# K K#
Vt
Vt
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
Truth Table
The truth table for CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
[8]
[9]
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the rising
edge of K; write data on
two consecutive K and K
rising edges.
L-H
H
Read Cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
L-H
L [9]
X
Q(A) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3)↑
NOP: No Operation
L-H
H
H
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
Standby: Clock Stopped
L
D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 001-12562 Rev. *D
Page 10 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Write Cycle Descriptions
The write cycle description table for CY7C1311JV18 and CY7C1313JV18 follows. [2, 10]
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence:
CY7C1311JV18 − both nibbles (D[7:0]) are written into the device.
CY7C1313JV18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence:
CY7C1311JV18 − both nibbles (D[7:0]) are written into the device.
CY7C1313JV18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence:
CY7C1311JV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1313JV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1311JV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1313JV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence:
CY7C1311JV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1313JV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1311JV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1313JV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1911JV18 follows. [2, 10]
BWS0
K
K
Comments
L
L–H
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Note
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-12562 Rev. *D
Page 11 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Write Cycle Descriptions
The write cycle description table for CY7C1315JV18 follows. [2, 10]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document Number: 001-12562 Rev. *D
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 12 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent clocking of the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternatively be
connected to VDD through a pull up resistor. Leave TDO unconnected. Upon power up, the device comes up in a reset state,
which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin is left unconnected if the TAP is not used. The pin is pulled up internally,
resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and is connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information on loading the
instruction register, see the TAP Controller State Diagram on
page 15. TDI is internally pulled up and is unconnected if the TAP
is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and is performed while the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
is selected at a time through the instruction registers. Data is
serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, skip
certain chips. The bypass register is a single-bit register that is
placed between TDI and TDO pins. This enables shifting of data
through the SRAM with minimal delay. The bypass register is set
LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
The Boundary Scan Order on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page
18.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Do not use three of these instructions that
are listed as RESERVED. The other five instructions are
described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, move the TAP controller into
the Update-IR state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
Document Number: 001-12562 Rev. *D
Page 13 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is given a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is given during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock only operates at a frequency up to 20
MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP then tries to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, stabilize the SRAM signal long enough
to meet the TAP controller's capture setup plus hold times (tCS
and tCH). The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CK and CK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
Document Number: 001-12562 Rev. *D
The shifting of data for the SAMPLE and PRELOAD phases
occurs concurrently when required, that is, while the data
captured is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit 47.
When this scan cell, called the ‘extest output bus tri-state’, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is pre-set HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 14 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [11]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
0
0
1
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-12562 Rev. *D
Page 15 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
106
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [12, 13, 14]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 μA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
μA
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
13. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
14. All Voltage referenced to Ground.
Document Number: 001-12562 Rev. *D
Page 16 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
TAP AC Switching Characteristics
Over the Operating Range [15, 16]
Parameter
Description
Min
Max
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [16]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50Ω
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-12562 Rev. *D
Page 17 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Identification Register Definitions
Instruction Field
Value
CY7C1311JV18
CY7C1911JV18
CY7C1313JV18
CY7C1315JV18
000
000
000
000
Revision Number
(31:29)
Description
Version number.
Cypress Device ID 11010011011000101 11010011011001101 11010011011010101 11010011011100101 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
1
1
1
1
ID Register
Presence (0)
Allows unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-12562 Rev. *D
Page 18 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
2J
1
6P
29
9G
57
5B
85
3K
2
6N
30
11F
58
5A
86
3J
3
7P
31
11G
59
4A
87
2K
4
7N
32
9F
60
5C
88
1K
5
7R
33
10F
61
4B
89
2L
6
8R
34
11E
62
3A
90
3L
7
8P
35
10E
63
1H
91
1M
8
9R
36
10D
64
1A
92
1L
9
11P
37
9E
65
2B
93
3N
10
10P
38
10C
66
3B
94
3M
11
10N
39
11D
67
1C
95
1N
12
9P
40
9C
68
1B
96
2M
13
10M
41
9D
69
3D
97
3P
14
11N
42
11B
70
3C
98
2N
15
9M
43
11C
71
1D
99
2P
16
9N
44
9B
72
2C
100
1P
17
11L
45
10B
73
3E
101
3R
18
11M
46
11A
74
2D
102
4R
19
9L
47
Internal
75
2E
103
4P
20
10L
48
9A
76
1E
104
5P
21
11K
49
8B
77
2F
105
5N
22
10K
50
7C
78
3F
106
5R
1G
23
9J
51
6C
79
24
9K
52
8A
80
1F
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1J
Document Number: 001-12562 Rev. *D
Page 19 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Power Up Sequence in QDR II SRAM
Power up and initialize QDR II SRAMs in a predefined manner
to prevent undefined operations.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other
inputs are HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
DLL Constraints
■
DLL uses K clock as its synchronizing input. The input has low
phase jitter, which is specified as tKC Var.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
~
~
Figure 3. Power Up Waveforms
K
K
~
~
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document Number: 001-12562 Rev. *D
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tie to VDDQ)
Page 20 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch-up Current ................................................... > 200 mA
Operating Range
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Range
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Commercial
DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V
Industrial
DC Input Voltage
[13]
Ambient
Temperature (TA)
VDD [17]
VDDQ [17]
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
.............................. –0.5V to VDD + 0.3V
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [14]
Parameter
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
IX
IOZ
VREF
IDD [21]
Description
Power Supply Voltage
IO Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Input Reference Voltage [20]
VDD Operating Supply
Test Conditions
Note 18
Note 19
IOH = −0.1 mA, Nominal Impedance
IOL = 0.1 mA, Nominal Impedance
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
VDD = Max,
300 MHz
IOUT = 0 mA,
f = fMAX = 1/tCYC
250 MHz
ISB1
Automatic Power down
Current
Max VDD,
300 MHz
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC, Inputs
Static
250 MHz
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
Min
Typ
Max
Unit
1.7
1.8
1.9
V
1.4
1.5
VDD
V
VDDQ/2 – 0.12
VDDQ/2 + 0.12 V
VDDQ/2 – 0.12
VDDQ/2 + 0.12 V
VDDQ – 0.2
VDDQ
V
VSS
0.2
V
VREF + 0.1
VDDQ + 0.3
V
–0.3
VREF – 0.1
V
−5
5
μA
−5
5
μA
0.68
0.75
0.95
V
730
mA
735
790
895
665
mA
675
705
830
265
mA
275
325
435
250
mA
250
290
(x36)
325
Notes
17. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
19. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
20. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
21. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-12562 Rev. *D
Page 21 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
AC Electrical Characteristics
Over the Operating Range [13]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
–
V
VIL
Input LOW Voltage
–
–
VREF – 0.2
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Max
Unit
5
pF
Clock Input Capacitance
6
pF
Output Capacitance
7
pF
165 FBGA
Package
Unit
18.7
°C/W
4.5
°C/W
CIN
Input Capacitance
CCLK
CO
Test Conditions
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Figure 4. AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
RL = 50Ω
VREF = 0.75V
ZQ
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250Ω
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[22]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(b)
Notes
22. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 001-12562 Rev. *D
Page 22 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Switching Characteristics
Over the Operating Range [22, 23]
Cypress Consortium
Parameter Parameter
300 MHz
Description
Min Max Min Max
VDD(Typical) to the First Access [24]
tPOWER
250 MHz
1
1
Unit
ms
tCYC
tKHKH
K Clock and C Clock Cycle Time
3.3
8.4
4.0
8.4
ns
tKH
tKHKL
Input Clock (K/K; C/C) HIGH
1.32
–
1.6
–
ns
tKL
tKLKH
Input Clock (K/K; C/C) LOW
1.32
–
1.6
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.49
–
1.8
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
0
1.45
0
1.8
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.5
–
ns
tSC
tIVKH
Control Setup to Clock (K, K) Rise (RPS, WPS)
0.4
–
0.5
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K, K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.3
–
0.35
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.3
–
0.35
–
ns
Hold Times
tHA
tKHAX
Address Hold after Clock (K/K) Rise
0.4
–
0.5
–
ns
tHC
tKHIX
Control Hold after Clock (K /K) Rise (RPS, WPS)
0.4
–
0.5
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.3
–
0.35
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.3
–
0.35
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active to Active)
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
tCQH
tCQHCQH
tCHZ
tCLZ
tCQHCQL
tCQHCQH
tCHQZ
tCHQX1
Output Clock (CQ/CQ) HIGH
0.27
[25]
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)
Clock (C and C) Rise to High-Z (Active to High-Z)
Clock (C and C) Rise to Low-Z
[26, 27]
[26, 27]
[25]
0.30
ns
–0.27
–
–0.30
–
ns
1.24
–
1.55
–
ns
1.24
–
1.55
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–
0.20
–
0.20
ns
–
1024
–
Cycles
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
tKC Reset
tKC Reset
K Static to DLL Reset
30
30
ns
Notes
23. When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
24. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
25. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) ia already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production
26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
27. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 001-12562 Rev. *D
Page 23 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence [28, 29, 30]
NOP
1
WRITE
3
READ
2
READ
4
NOP
6
WRITE
5
7
K
t KH
t
tKL
t KHKH
CYC
K
RPS
t SC
tHC
t SC
t HC
WPS
A0
A
tSA
A1
A3
A2
t HD
t HA
t
t SD
SD
D
D10
D11
Q00
Q
t KHCH
t KHCH
t HD
D13
D12
Q01
Q02
tCO
Q03
D30
D31
Q20
D33
D32
Q22
Q21
Q23
t CHZ
tCQDOH
t CLZ
t DOH
t CQD
C
t CYC
t KHKH
t KH
t KL
C
t CCQO
t CQOH
CQ
t CQH
t CQHCQH
t CQOH
t CCQO
CQ
DON’T CARE
UNDEFINED
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-12562 Rev. *D
Page 24 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
300
Ordering Code
CY7C1311JV18-300BZC
Package
Diagram
Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Operating
Range
Commercial
CY7C1911JV18-300BZC
CY7C1313JV18-300BZC
CY7C1315JV18-300BZC
CY7C1311JV18-300BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1911JV18-300BZXC
CY7C1313JV18-300BZXC
CY7C1315JV18-300BZXC
CY7C1311JV18-300BZI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1911JV18-300BZI
CY7C1313JV18-300BZI
CY7C1315JV18-300BZI
CY7C1311JV18-300BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1911JV18-300BZXI
CY7C1313JV18-300BZXI
CY7C1315JV18-300BZXI
250
CY7C1311JV18-250BZC
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1911JV18-250BZC
CY7C1313JV18-250BZC
CY7C1315JV18-250BZC
CY7C1311JV18-250BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1911JV18-250BZXC
CY7C1313JV18-250BZXC
CY7C1315JV18-250BZXC
CY7C1311JV18-250BZI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1911JV18-250BZI
CY7C1313JV18-250BZI
CY7C1315JV18-250BZI
CY7C1311JV18-250BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1911JV18-250BZXI
CY7C1313JV18-250BZXI
CY7C1315JV18-250BZXI
Document Number: 001-12562 Rev. *D
Page 25 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Package Diagram
Figure 6. 165-Ball FBGA (13 x 15 x 1.40 mm), 51-85180
51-85180 *B
Document Number: 001-12562 Rev. *D
Page 26 of 27
[+] Feedback
CY7C1311JV18/CY7C1911JV18
CY7C1313JV18/CY7C1315JV18
Document History Page
Document Title: CY7C1311JV18/CY7C1911JV18/CY7C1313JV18/CY7C1315JV18, 18-Mbit QDR® II SRAM 4-Word
Burst Architecture
Document Number: 001-12562
REVISION
ECN
**
808457
*A
ORIG. OF SUBMISSION DESCRIPTION OF CHANGE
CHANGE
DATE
VKN
See ECN
New data sheet
1423164 VKN/AESA
See ECN
Converted from preliminary to final
Removed 250MHz and 200MHz
Updated IDD/ISB specs
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed tCYC max spec to 8.4ns
*B
2189567 VKN/AESA
See ECN
Minor Change-Moved to the external web
*C
2561974 VKN/PYRS
09/04/08
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings “ on page 21,
Updated power up sequence waveform and its description,
Added footnote #21 related to IDD,
Changed ΘJA spec from 28.51 to 18.7, Changed ΘJC spec from 5.91 to 4.5,
Changed JTAG ID [31:29] from 001 to 000, Added 250MHz speed bin.
*D
2748221
08/04/09
Updated package diagram
Post to external web
NJY
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
Wireless
wireless.cypress.com
Memories
memory.cypress.com
Image Sensors
image.cypress.com
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12562 Rev. *D
Revised August 04, 2009
Page 27 of 27
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
[+] Feedback