ALSC AS7C33128PFD36A-150TQI 3.3v 128k x 32/36 pipeline burst synchronous sram Datasheet

March 2001
AS7C33128PFD32A
AS7C33128PFD36A
®
3.3V 128K × 32/36 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Dual-cycle deselect
- Single-cycle deselect also available (AS7C33128PFS32A/
AS7C33128PFS36A)
• Pentium®* compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• NTD™* pipeline architecture available
(AS7C33128KNTD32A/ AS7C33128NTD36A)
Logic block diagram
Pin arrangement
17
A[16:0]
GWE
BWE
BWd
D
CE Address
register
CLK
D
DQd Q
Byte write
registers
CLK
15
128K × 32/36
Memory
array
17
DQPc/NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd/NC
36/32
36/32
D
DQc Q
Byte write
registers
CLK
BWc
D
DQb Q
Byte write
registers
CLK
BWa
D
DQa Q
Byte write
registers
CLK
CE0
CE1
CE2
D
Q
Enable
CE register
CLK
Power
down
ZZ
4
OE
Output
registers
CLK
Input
registers
CLK
D Enable Q
delay
register
CLK
TQFP 14 × 20 mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa/NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
BWb
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Q0
Burst logic
Q1
17
Q
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CLK
CE
CLR
A6
A7
CE0
CE1
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
LBO
CLK
ADV
ADSC
ADSP
Note: Pins 1,30,51,80 are NC for ×32
OE
FT
DATA [35:0]
DATA [31:0]
Selection guide
–166
–150
–133
–100
Units
6
6.7
7.5
10
ns
Maximum clock frequency
166
150
133
100
MHz
Maximum pipelined clock access time
3.5
3.8
4
5
ns
Maximum operating current
475
450
425
325
mA
Maximum standby current
130
110
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
mA
Minimum cycle time
*
®
Pentium is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are
the property of their respective owners.
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P. 1 of 11
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128PFD32A
AS7C33128PFD36A
®
Functional description
The AS7C33128PFD32A and AS7C33128PFD36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any
given technology.
Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC™*-based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus
frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst
addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address
strobes are High. Burst operation is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium®
count sequence. With LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by
asserting BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented
internally to the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33128PFD32A and AS7C33128PFD36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can
operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.
*PowerPC™ is a tradenark International Business Machines Corporation.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
Address and control pins
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O pins
VIN = VOUT = 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
L
X
X
T
H
L
L
T
H
H
X
F*
H
L
H
F*
Key:
X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
3/22/01; v.1.0
Alliance Semiconductor
P. 2 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Signal descriptions
Signal
I/O Properties
CLK
I
CLOCK
A0–A16
I
SYNC
DQ[a,b,c,d] I/O SYNC
CE0
I
SYNC
CE1, CE2
I
SYNC
ADSP
I
SYNC
ADSC
ADV
I
I
SYNC
SYNC
GWE
I
SYNC
BWE
I
SYNC
BW[a,b,c,d] I
SYNC
OE
I
ASYNC
LBO
I
STATIC
default =
HIGH
FT
I
STATIC
ZZ
I
ASYNC
Description
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.18
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
VDD, VDDQ
VIN
VIN
PD
IOUT
Tstg
Tbias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
VDD + 0.5
VDDQ + 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
o
C
o
C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
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P. 3 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Synchronous truth table
CE0
CE1
CE2
ADSP
ADSC
ADV
WEn1
OE
Address accessed
CLK
Operation
DQ
H
X
X
X
L
X
X
X
NA
L to H
Deselect
Hi−Z
L
L
X
L
X
X
X
X
NA
L to H
Deselect
Hi−Z
L
L
X
H
L
X
X
X
NA
L to H
Deselect
Hi−Z
L
X
H
L
X
X
X
X
NA
L to H
Deselect
Hi−Z
L
X
H
H
L
X
X
X
NA
L to H
Deselect
Hi−Z
L
H
L
L
X
X
X
L
External
L to H
Begin read
Hi−Z2
L
H
L
L
X
X
X
H
External
L to H
Begin read
Hi−Z
L
H
L
H
L
X
F
L
External
L to H
Begin read
Hi−Z2
L
H
L
H
L
X
F
H
External
L to H
Begin read
Hi−Z
X
X
X
H
H
L
F
L
Next
L to H
Cont. read
Q
X
X
X
H
H
L
F
H
Next
L to H
Cont. read
Hi−Z
X
X
X
H
H
H
F
L
Current
L to H
Suspend read
Q
X
X
X
H
H
H
F
H
Current
L to H
Suspend read
Hi−Z
H
X
X
X
H
L
F
L
Next
L to H
Cont. read
Q
H
X
X
X
H
L
F
H
Next
L to H
Cont. read
Hi−Z
H
X
X
X
H
H
F
L
Current
L to H
Suspend read
Q
H
X
X
X
H
H
F
H
Current
L to H
Suspend read
Hi−Z
L
H
L
H
L
X
T
X
External
L to H
Begin write
D3
X
X
X
H
H
L
T
X
Next
L to H
Cont. write
D
H
X
X
X
H
L
T
X
Next
L to H
Cont. write
D
X
X
X
H
H
H
T
X
Current
L to H
Suspend write
D
H
X
X
X
H
H
T
X
Current
L to H
Suspend write
D
Key: X = Don’t Care, L = Low, H = High.
1
See “Write enable truth table”on page 2 for more information.
2 Q in flow through mode.
3
For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
VDD
3.135
3.3
3.6
VSS
0.0
0.0
0.0
3.3V I/O supply
voltage
VDDQ
3.135
3.3
3.6
VSSQ
0.0
0.0
0.0
2.5V I/O supply
voltage
VDDQ
2.35
2.5
2.9
VSSQ
0.0
0.0
0.0
Supply voltage
Input
voltages†
Address and
control pins
I/O pins
Ambient operating temperature
Unit
V
V
V
VIH
2.0
–
VDD + 0.3
VIL
–0.5*
–
0.8
VIH
2.0
–
VDDQ + 0.3
*
VIL
–0.5
–
0.8
TA
0
–
70
V
V
°C
* VIL min = –2.0V for pulse width less than 0.2 × tRC.
† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
3/22/01; v.1.0
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P. 4 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
TQFP thermal resistance
Description
Conditions
Thermal resistance
(junction to ambient)*
Symbol
Typical
Units
θJA
40
°C/W
θJC
8
°C/W
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Thermal resistance
(junction to top of case)*
* This parameter is sampled.
DC electrical characteristics
–166
Parameter
–150
–133
–100
Symbol
Test conditions
Input leakage
current*
|ILI|
VDD = Max, VIN = GND to VDD
–
2
–
2
–
2
–
2
µA
Output leakage
current
|ILO|
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
–
2
–
2
–
2
–
2
µA
ICC
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
–
475
–
450
–
425
–
325
mA
ISB
Deselected, f = fMax, ZZ ≤ VIL
–
130
–
110
–
100
–
90
ISB1
Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V
–
30
–
30
–
30
–
30
ISB2
Deselected, f = fMax, ZZ ≥ VDD – 0.2V
All VIN ≤ VIL or ≥ VIH
–
30
–
30
–
30
–
30
VOL
IOL = 8 mA, VDDQ = 3.465V
–
0.4
–
0.4
–
0.4
–
0.4
VOH
IOH = –4 mA, VDDQ = 3.135V
2.4
–
2.4
–
2.4
–
2.4
–
Operating power
supply current
Standby power
supply current
Output voltage
Min Max Min Max Min Max Min Max Unit
mA
V
* LBO pin has an internal pull-up and input leakage = ±10 µa.
Note: ICC given with no output loading. ICC increases with faster cycles times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
–166
Parameter
Output leakage
current
Output voltage
3/22/01; v.1.0
–150
–133
–100
Symbol
Test conditions
Min Max Min Max Min Max Min Max Unit
|ILO|
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
–1
1
–1
1
–1
1
–1
1
VOL
IOL = 2 mA, VDDQ = 2.65V
–
0.7
–
0.7
–
0.7
–
0.7
VOH
IOH = –2 mA, VDDQ = 2.35V
1.7
–
1.7
–
1.7
–
1.7
–
Alliance Semiconductor
µA
V
P. 5 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Timing characteristics over operating range
–166
Parameter
Symbol Min
–150
–133
–100
Max
Min
Max
Min
Max
Min
Max
Unit
Notes*
Clock frequency
fMax
–
166
–
150
–
133
–
100
MHz
Cycle time (pipelined mode)
tCYC
6
–
6.6
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
tCYCF
10
–
10
–
12
–
12
–
ns
Clock access time (pipelined mode)
tCD
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock access time (flow-through
mode)
tCDF
–
9
–
10
–
10
–
12
ns
Output enable LOW to data valid
tOE
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock HIGH to output Low Z
tLZC
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
tOH
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
tLZOE
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
tHZOE
–
3.5
–
3.8
–
4.0
–
4.5
ns
2,3,4
Clock HIGH to output High Z
tHZC
–
3.5
–
3.8
–
4.0
–
5.0
ns
2,3,4
Output enable HIGH to invalid output
tOHOE
0
–
0
–
0
–
0
–
ns
Clock HIGH pulse width
tCH
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
tCL
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
tAS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
tDS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
tWS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
tCSS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,8
Address hold from clock HIGH
tAH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
tDH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
tWH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
tCSH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
tADVS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSP setup to clock HIGH
tADSPS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSC setup to clock HIGH
tADSCS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADV hold from clock HIGH
tADVH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold fromclock HIGH
tADSPH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
tADSCH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
*See “Notes” on page 10.
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P. 6 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Timing waveform of read cycle
tCH
tCYC
tCL
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
tAS
LOAD NEW ADDRESS
tAH
Address
A1
A2
A3
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tCD
tHZOE
tOH
DOUT
(pipelined mode) t
OE
Q(A1)
Q(A2)
ADV INSERTS WAIT STATES
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
tHZC
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tLZOE
DOUT
(flow-through mode)
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tHZC
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:d] is don’t care.
Key to switching waveform
Rising input
3/22/01; v.1.0
Falling input
Alliance Semiconductor
Undefined/don’t care
P. 7 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Timing waveform of write cycle
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
Address
A1
A2
A3
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
tADVS
ADV SUSPENDS BURST
tADVH
ADV
OE
tDS
tDH
Data In
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
D(A3Ý01)
D(A3Ý10)
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
3/22/01; v.1.0
Alliance Semiconductor
P. 8 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Timing waveform of read/write cycle
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
Address
A2
A1
A3
tWS
tWH
GWE
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDS
tDH
DIN
D(A2)
tHZOE
tLZC
tCD
DOUT
(pipeline mode)
tOH
tLZOE
tOE
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tCDF
DOUT
(flow-through mode)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
3/22/01; v.1.0
Alliance Semiconductor
P. 9 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
Thevenin equivalent:
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
• Input and output timing reference levels: 1.5V.
+3.0V
Z0 = 50Ω
90%
10%
GND
90%
10%
50Ω
DOUT
Figure A: Input waveform
VL = 1.5V
for 3.3V I/O;
30 pF* = V
DDQ/2
for 2.5V I/O
Figure B: Output load (A)
DOUT
351Ω
317Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load(B)
Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to GWE, BWE, BW[a:d].
8 Chip select refers to CE0, CE1, CE2.
Package Dimensions
100-pin quad flat pack (TQFP)
A1
A2
b
c
D
E
e
Hd
He
L
L1
α
TQFP
Min
Max
0.05
0.15
1.35
1.45
0.22
0.38
0.09
0.20
13.90
14.10
19.90
20.10
0.65 nominal
15.90
16.10
21.90
22.10
0.45
0.75
1.00 nominal
0°
7°
Hd
D
b
e
He E
Dimensions in millimeters
c
L1
L
3/22/01; v.1.0
A1 A2
Alliance Semiconductor
α
P. 10 of 11
AS7C33128PFD32A
AS7C33128PFD36A
®
Ordering information
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C33128PFD32A-166TQC
AS7C33128PFD32A-150TQC
AS7C33128PFD32A-133TQC
AS7C33128PFD32A-100TQC
AS7C33128PFD32A-166TQI
AS7C33128PFD32A-150TQI
AS7C33128PFD32A-133TQI
AS7C33128PFD32A-100TQI
AS7C33128PFD36A-166TQC
AS7C33128PFD36A-150TQC
AS7C33128PFD36A-133TQC
AS7C33128PFD36A-100TQC
AS7C33128PFD36A-166TQI
AS7C33128PFD36A-150TQI
AS7C33128PFD36A-133TQI
AS7C33128PFD36A-100TQI
Part numbering guide
AS7C
33
128
PF
D
32/36
A
–XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 128=128K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: D=Dual cycle deselect
6.Organization: 32=x32; 36=x36
7.Production version: A=first production version
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
3/22/01; v.1.0
Alliance Semiconductor
P. 11 of 11
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