Kersemi IRFI640G Power mosfet Datasheet

IRFI640G, SiHFI640G
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Isolated Package
• High Voltage Isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
• Sink to Lead Creepage Distance = 4.8 mm
• Dynamic dV/dt Rating
• Low Thermal Resistance
• Lead (Pb)-free Available
200
RDS(on) (Ω)
VGS = 10 V
0.18
Qg (Max.) (nC)
70
Qgs (nC)
13
Qgd (nC)
39
Configuration
Single
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-220 FULLPAK eliminates the need for additional
insulating hardware in commercial-industrial applications.
The molding compound used provides a high isolation
capability and a low thermal resistance between the tab and
external heatsink. The isolation is equivalent to using a 100
micron mica barrier with standard TO-220 product. The
FULLPAK is mounted to a heatsink using a single clip or by
a single screw fixing.
G
G D S
COMPLIANT
DESCRIPTION
D
TO-220 FULLPAK
Available
RoHS*
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-220 FULLPAK
IRFI640GPbF
SiHFI640G-E3
IRFI640G
SiHFI640G
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
VGS at 10 V
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
TC = 25 °C
TC = 100 °C
SYMBOL
LIMIT
VDS
VGS
200
± 20
9.8
6.2
39
0.32
430
9.8
4.0
40
5.0
- 55 to + 150
300d
10
1.1
ID
IDM
TC = 25 °C
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
for 10 s
6-32 or M3 screw
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a.
b.
c.
d.
Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
VDD = 50 V, starting TJ = 25 °C, L = 6.7 mH, RG = 25 Ω, IAS = 9.8 A (see fig. 12).
ISD ≤ 18 A, dI/dt ≤ 150 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
1.6 mm from case.
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1
IRFI640G, SiHFI640G
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
3.1
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 µA
200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.29
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
IGSS
IDSS
RDS(on)
gfs
VGS = ± 20 V
-
-
± 100
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
0.18
Ω
5.2
-
-
S
ID = 5.9 Ab
VGS = 10 V
VDS = 50 V, ID = 5.9
Ab
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Drain to Sink Capacitance
C
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
tr
td(off)
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1300
-
-
400
-
-
130
-
f = 1.0 MHz
-
12
-
-
-
70
-
-
13
-
-
39
-
14
-
-
51
-
-
45
-
-
36
-
-
4.5
-
VGS = 10 V
ID = 18 A, VDS = 160 V,
see fig. 6 and 13b
VDD = 100 V, ID = 18 A,
RG = 9.1 Ω, RD= 5.4 Ω,
see fig. 10b
tf
LD
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
-
7.5
-
-
-
9.8
-
-
39
-
-
2.0
V
-
300
610
ns
-
3.4
7.1
µC
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = 18 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2
2
S
TJ = 25 °C, IS = 9.8 A, VGS = 0 Vb
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IRFI640G, SiHFI640G
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC= 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC= 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFI640G, SiHFI640G
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
4
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
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IRFI640G, SiHFI640G
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
RG
+
-
I AS
V DD
VDS
10 V
tp
0.01 Ω
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
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IRFI640G, SiHFI640G
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
6
Fig. 13b - Gate Charge Test Circuit
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IRFI640G, SiHFI640G
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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