IXYS CPC7583 Line card access switch Datasheet

CPC7583
Line Card Access Switch
INTEGRATED CIRCUITS DIVISION
Features
Description
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The CPC7583 is a monolithic 10-pole line card access
switch in a 28-pin SOIC package. It provides the
necessary functions to replace three 2-Form-C
electromechanical relays on analog line cards and
combined voice and data line cards found in central
office, access, and PBX equipment. The device
contains solid state switches for tip and ring line break,
ringing injection/ringing return, and test access. The
CPC7583 requires only a +5 V supply and offers
break-before-make or make-before-break switch
operation.
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•
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•
Monolithic IC reliability
Low, matched, RON
Eliminates the need for zero-cross switching
Flexible switch timing for transition from ringing
mode to talk mode.
Clean, bounce-free switching
SLIC tertiary protection via integrated current
limiting, voltage clamping and thermal shutdown
5V operation with power consumption < 10.5 mW
Intelligent battery monitor
Logic-level inputs, no external drive circuitry required
Compatible with Legerity 7583/8583 family
Small 28-pin SOIC
Ordering Information
Applications
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Part #
Central office (CO)
Digital Loop Carrier (DLC)
PBX Systems
Digitally Added Main Line (DAML)
Hybrid Fiber Coax (HFC)
Fiber in the Loop (FITL)
Pair Gain System
Channel Banks
Description
CPC7583BA
CPC7583BATR
28-Pin SOIC, 29/Tube
28-Pin SOIC, 1000/Reel
Not for New Designs
TTESTIN (TCHANTEST)
+5 Vdc
TTESTOUT (TDROPTEST)
8 TRING
10
5
12 VDD
SW7
CPC7583
X
Tip
TLINE
7
X SW5
X SW3
X
X SW9
6 TBAT
SW1
Ring
Secondary
Protection
SLIC
SW2
RLINE 22
X
X SW10
X SW6 X SW4
SCR
and
Trip
Circuit
X
VREF
Switch
Control
Logic
SW8
19
RTESTOUT (RDROPTEST)
20
300Ω (min.)
24
1
FGND
28
L
A
T
C
H
23 RBAT
17
16
15
18
14 13
DGND
INTESTIN
INRINGING
INTESTOUT
LATCH
TSD
VBAT
VBAT
RINGING
RTESTIN (RCHANTEST)
Pb
DS-CPC7583-R07
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1
CPC7583
INTEGRATED CIRCUITS DIVISION
1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6.4 TESTOUT Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.5 Ringing Test Return Switch, SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6.6 Ringing Test Switch, SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6.7 TESTIn Switches, SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.1 Truth Table for CPC7583xA and CPC7583xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9.2 Truth Table for CPC7583xC and CPC7583xD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 TSD Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
15
15
15
16
16
16
16
16
16
16
17
17
17
3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 CPC7583BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 CPC7583BATR Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
19
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R07
CPC7583
INTEGRATED CIRCUITS DIVISION
1. Specifications
1.1 Package Pinout
Pin#
Name
28 VBAT
1
FGND
NC 2
27 NC
2
NC
No connection.
NC 3
26 NC
3
NC
No connection.
4
NC
No connection.
NC 4
25 NC
5
TTESTin
24 RTESTin
6
TBAT
Tip lead of the SLIC.
TBAT 6
23 RBAT
7
TLINE
Tip lead of the line side.
TLINE 7
22 RLINE
8
FGND 1
TTESTin 5
TRINGING 8
21 NC
9
10
Description
Fault ground.
Tip lead of the TESTin bus.
TRINGING Ringing generator return.
NC
Not connected.
TTESTout Tip lead of the TESTout bus.
20 RRINGING
11
NC
No connection.
TTESTout 10
19 RTESTout
12
VDD
+5 V supply.
NC 11
18 LATCH
13
TSD
Temperature shutdown pin.
VDD 12
17 IN TESTin
14
DGND
TSD 13
16 INRINGING
DGND 14
15 INTESTout
NC 9
R07
1.2 Pinout Description
Digital ground.
15
INTESTout Logic control input.
16
INRINGING Logic control input.
17
INTESTin Logic control input.
18
LATCH
19
RTESTout Ring lead of the TESTout bus.
20
RRINGING Ringing generator source.
Data latch enable control input.
21
NC
22
RLINE
Ring lead of the line side.
23
RBAT
Ring lead of the SLIC.
24
RTESTin
25
NC
No connection.
26
NC
No connection.
27
NC
No connection.
28
VBAT
Battery supply.
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No connection.
Ring lead of the TESTin bus.
3
CPC7583
INTEGRATED CIRCUITS DIVISION
1.3 Absolute Maximum Ratings
Parameter
1.4 ESD Rating
Minimum Maximum
Unit
Operating temperature
-40
+110
°C
Storage temperature
-40
+150
°C
5
95
%
-0.3
7
V
Battery Supply
-
-85
V
DGND to FGND
separation
-5
+5
V
Logic input voltage
-0.3
VDD +0.3
V
Logic input to switch output
isolation
-
320
V
Switch open contact
isolation (SW1, SW2, SW3,
SW5, SW6, SW7, SW9,
SW10)
-
320
V
Switch open contact
isolation (SW4)
-
465
V
Switch open contact
isolation (SW8)
-
235
V
Operating relative humidity
+5 V power supply (VDD)
ESD Rating (Human Body Model)
1000 V
1.5 General Conditions
Unless otherwise specified, minimum and maximum
values are production testing requirements.
Typical values are characteristic of the device at 25°C
and are the result of engineering evaluations. They are
provided for informational purposes only and are not
part of the manufacturing testing requirements.
Specifications cover the operating temperature range
TA = -40°C to +85°C. Also, unless otherwise specified
all testing is performed with VDD = +5Vdc, logic low
input voltage is 0Vdc and logic high input voltage is
+5Vdc.
Absolute maximum electrical ratings are at 25°C
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
4
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R07
CPC7583
INTEGRATED CIRCUITS DIVISION
1.6 Switch Specifications
1.6.1 Break Switches, SW1 and SW2
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
Off-state leakage current
+25° C
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85° C
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
-40° C
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
ISW
-
0.3
0.1
RON
+25° C
+85° C
-40° C
RON match
ISW(on) = ±10 mA, ±40 mA,
RBAT and TBAT = -2 V
RON
-
Per on-resistance test condition of SW1
& SW2
RON
14.5
-
20.5
28
10.5
-
0.15
0.8

DC current limit
+25° C
+85° C
VSW (on) = ±10 V
-40° C
Dynamic current limit
(t 0.5 s)
ISW
Break switches on, ringing switches off,
apply ±1 kV 10x1000 s pulse, with
appropriate protection in place.
-
225
80
150
-
400
425
-
2.5
-
A
-
0.1
-
0.3
1
A
-
0.1
-
200
-
V/s
-
mA
Logic input to switch output isolation
+25° C
VSW (TLINE, RLINE) = ±320 V, logic
inputs = gnd
+85° C
VSW (TLINE, RLINE) = ±330 V, logic
inputs = gnd
-40° C
VSW (TLINE, RLINE) = ±310 V, logic
inputs = gnd
dv/dt sensitivity
R07
-
ISW
-
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5
CPC7583
INTEGRATED CIRCUITS DIVISION
1.6.2 Ringing Return Switch, SW3
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
Off-state leakage current
+25° C
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85° C
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
-40° C
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
ISW
-
0.3
0.1
RON
+25° C
+85° C
ISW(on) = ±0 mA, ±10 mA
RON
-
-40° C
60
-
85
110
45
-

DC current limit
+25° C
+85° C
VSW (on) = ± 10 V
-40° C
Dynamic current limit
(t 0.5 s)
-
120
70
85
210
ISW
Break switches off, ringing switches on,
apply ±1 kV 10x1000 s pulse, with
appropriate protection in place.
-
mA
-
2.5
A
Logic input to switch output isolation
+25° C
VSW (TRING, TLINE) = ±320 V, logic
inputs = gnd
+85° C
VSW (TRING, TLINE) = ±330 V, logic
inputs = gnd
-40° C
VSW (TRING, TLINE) = ±310 V, logic
inputs = gnd
dv/dt sensitivity
6
-
0.1
ISW
-
0.3
1
A
-
V/s
0.1
-
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-
200
R07
CPC7583
INTEGRATED CIRCUITS DIVISION
1.6.3 Ringing Switch, SW4
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
0.05
1
0.1
1
0.05
1
1.5
3
V
Off-state leakage current
+25° C
VSW (differential) = -255 V to +210 V
VSW (differential) = +255 V to -210 V
+85° C
VSW (differential) = -270 V to +210 V
VSW (differential) = +270 V to -210 V
-40° C
VSW (differential) = -245 V to +210 V
VSW (differential) = +245 V to -210 V
On Voltage
ISW (on) = ± 1 mA
ISW
-
-
A
Ringing generator
current to ground during Inputs set for ringing mode
ringing
IRINGING
0.1
0.25
mA
On steady-state current* Inputs set for ringing mode
ISW
-
150
mA
Surge current*
-
-
-
2
A
Release current
-
IRINGING
450
-
A
RON
10
15

1
A
-
V/s
RON
ISW (on) = ±70 mA, ±80 mA
Logic input to switch output isolation
+25° C
VSW (RRING, RLINE) = ±320 V, logic
inputs = gnd
+85° C
VSW (RRING, RLINE) = ±330 V, logic
inputs = gnd
-40° C
VSW (RRING, RLINE) = ±310 V, logic
inputs = gnd
dv/dt sensitivity
-
0.1
ISW
-
0.3
0.1
-
200
*Secondary protection and ringing source current limiting must prevent exceeding this parameter.
R07
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7
CPC7583
INTEGRATED CIRCUITS DIVISION
1.6.4 TESTOUT Switches, SW5 and SW6
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
Off-state leakage current
+25° C
VSW (differential) = -320 V to gnd
VSW (differential) = +260 V to -60 V
+85° C
VSW (differential) = -330 V to gnd
VSW (differential) = +260 V to -60 V
-40° C
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
ISW
-
0.3
0.1
RON
+25° C
+85° C
ISW(on) = ±10 mA, ±40 mA
RON
35
-
50
70
26
-
-
140
-
80
100
-
-
210
250
-
2.5
-
A
-
-40° C

DC current limit
+25° C
+85° C
VSW (on) = ±10 V
-40° C
Dynamic current limit
(t 0.5 s)
Break switches in on state, ringing
switches off, apply ±1 kV at
10x1000 s pulse, with appropriate
secondary protection in place.
mA
ISW
Logic input to switch output isolation
+25° C
VSW (TTESTout, TLINE, RTESTout, RLINE)
= ±320 V, logic inputs = gnd
ISW
-
0.1
1
A
+85° C
VSW (TTESTout, TLINE, RTESTout, RLINE)
= ±330 V, logic inputs = gnd
ISW
-
0.3
1
A
-40° C
VSW (TTESTout, TLINE, RTESTout, RLINE)
= ±310 V, logic inputs = gnd
ISW
-
0.1
1
A
-
-
200
-
V/s
dv/dt sensitivity
8
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R07
CPC7583
INTEGRATED CIRCUITS DIVISION
1.6.5 Ringing Test Return Switch, SW7
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
Off-state leakage current
+25° C
VSW (differential) = -320 V to gnd
VSW (differential) = +260 to -60 V
+85° C
VSW (differential) = -330 V to gnd
VSW (differential) = +270 V to -60 V
-40° C
VSW (differential) = -310 V to gnd
VSW (differential) = +250 V to -60 V
0.1
ISW
-
0.3
0.1
RON
+25° C
+85° C
ISW(on) = ±10 mA, ±40 mA
RON
-
-40° C
60
-
85
100
45
-

DC current limit
+25° C
+85° C
120
VSW (on) = ±10 V
ISW
70
-40° C
80
-
mA
1
A
-
V/s
210
Logic input to switch output isolation
+25° C
VSW (TRING, TTESTin) = ±320 V, logic
inputs = gnd
+85° C
VSW (TRING, TTESTin) = ±330 V, logic
inputs = gnd
-40° C
VSW (TRING, TTESTin) = ±310 V, logic
inputs = gnd
dv/dt sensitivity
R07
-
0.1
ISW
-
0.3
0.1
-
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9
CPC7583
INTEGRATED CIRCUITS DIVISION
1.6.6 Ringing Test Switch, SW8
Parameter
Test Conditions
Symbol
Off-state leakage current
+25° C
VSW (differential) = -60 V to +175 V
+85° C
-40° C
ISW(ON) = ±1 mA
On Voltage
ISW(ON) = ±70 mA, ±80 mA
RON
Release Current
Logic input to switch output isolation
VSW (RRING, RTESTin) = ±320 V, logic
+25° C
inputs = gnd
VSW (RRING, RTESTin) = ±330 V, logic
+85° C
inputs = gnd
VSW (RRING, RTESTin) = ±310 V, logic
-40° C
inputs = gnd
dv/dt sensitivity
-
Minimum
Typical
Maximum
Unit
0.05
0.1
0.05
1
A
0.75
1.5
V
RON
35
-

-
450
-
A
1
A
200
-
V/s
Typical
Maximum
Unit
1
A
ISW
-
-
0.1
ISW
-
0.3
0.1
-
1.6.7 TESTIn Switches, SW9 and SW10
Parameter
Test Conditions
Symbol
Minimum
Off-state leakage current
VSW (differential) = -320 V to gnd
+25° C
VSW (differential) = -60 V to +260 V
+85° C
VSW (differential) = -330 V to gnd
VSW (differential) = -60 V to +270 V
-40° C
VSW (differential) = -310 V to gnd
VSW (differential) = -60 V to +250 V
0.1
ISW
-
0.3
0.1
RON
+25° C
ISW(on) = ±10 mA, ±40 mA
+85° C
-40° C
DC current limit
+25° C
VSW (on) = ±10 V
+85° C
-40° C
Logic input to switch output isolation
VSW (TTESTin, RTESTin) = ±320 V, logic
+25° C
inputs = gnd
VSW (TTESTin, RTESTin) = ±330 V, logic
+85° C
inputs = gnd
VSW (TTESTin, RTESTin) = ±310 V, logic
-40° C
inputs = gnd
dv/dt sensitivity
10
RON
-
35
50
26
70
-

ISW
80
-
160
110
210
250
mA
1
A
-
V/s
0.1
ISW
-
0.3
0.1
-
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CPC7583
INTEGRATED CIRCUITS DIVISION
1.7 Additional Electrical Characteristics
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Input low voltage
-
VIL
-
-
1.5
Input high voltage
-
VIH
3.5
-
-
Unit
Digital Inputs
Input leakage current
(high)
VDD = 5.5 V, VBAT = -75 V, VIH = 5 V
IIH
-
0.1
1
Input leakage current
(low)
VDD = 5.5 V, VBAT = -75 V, VIL = 0 V
IIL
-
0.1
1
V
A
Voltage Requirements
VDD
-
VDD
4.5
5.0
5.5
V
VBAT1
-
VBAT
-19
-
-72
V
1
VBAT is used only for internal protection circuitry. If VBAT goes more positive than -10 V, the device will enter the all-off state and will remain in the all-off state until
the battery goes more negative than -15 V
Power Requirements
Power consumption in
talk and all-off states
VDD = 5 V, VBAT = -48 V, measure IDD
and IBAT
P
Power consumption in
any other state
VDD = 5 V, VBAT = -48 V, measure IDD
and IBAT
P
VDD current in talk and
all-off states
VDD current in any other
state
-
Shutdown circuit
hysteresis
R07
7.5
mW
IDD
-
5.0
10.5
0.7
1.5
VDD = 5 V, VBAT = -48 V
mA
IDD
-
IBAT
VBAT current in any state VDD = 5V, VBAT = -48 V
Temperature Shutdown Requirements (temperature shutdown flag is active low)
Shutdown activation
temperature
3.5
Not production tested - limits are
guaranteed by design and Quality
Control sampling audits.
1.0
1.9
4
10
A
TSD_on
110
125
150
°C
TSD_off
10
-
25
°C
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11
CPC7583
INTEGRATED CIRCUITS DIVISION
1.8 Protection Circuitry Electrical Specifications
Parameter
Conditions
Symbol
Parameters Related to the Diodes in the Diode Bridge
Voltage drop at
Apply ± dc current limit of break
Forward
continuous current
switches
Voltage
(50/60 Hz)
Voltage drop at surge Apply ± dynamic current limit of break
Forward
current
switches
Voltage
Parameters Related to the Protection SCR (CPC7583xA and CPC7583xC)
Surge current
I
+25° C
TRIG
Trigger current
I
+85° C
TRIG
I
+25° C
HOLD
Hold current
I
+85° C
HOLD
V
TBAT or
Gate trigger voltage
IGATE = ITRIGGER§
VRBAT
Reverse leakage current VBAT = -48 V
0.5 A, t = 0.5 s
On-state voltage
2.0 A, t = 0.5 s
Minimum
Typical
Maximum
-
2.8
3.5
Unit
V
-
5
-
-
200
*
-
-
120
-
265
-
100
170
-
VBAT -4
-
VBAT -2
V
-
-3
-5
1.0
-
A
V
V
IVBAT
VTBAT or
VRBAT
A
mA
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
§
VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.
1.9 Truth Tables
1.9.1 Truth Table for CPC7583xA and CPC7583xB
TESTIN
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TESTOUT
Switches
0
Off
On
Off
Off
Off
0
1
Off
Off
Off
Off
On
On
Off
Off
Off
Off
On
Off
Off
Off
On
Off
Off
Off
On
Off
Off
Off
On
Off
Off
State
INRINGING
INTESTIN
INTESTOUT
Talk
0
0
TESTout
0
Latch
TSD
TESTin
0
1
0
Simultaneous
TESTin and
TESTout
0
1
1
Ringing
1
0
0
Ringing
Generator
Test
1
1
0
Latched
X
X
X
1
1
0
1
0
Off
Off
Off
Off
Off
1
1
1
0
Off
Off
Off
Off
Off
X
X
X
X
Off
Off
Off
Off
Off
All Off
0
1 or
Floating 1
Unchanged Unchanged Unchanged Unchanged Unchanged
02
1
If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally.
2
Forcing TSD to ground overrides the logic input pins and forces an all off state.
12
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CPC7583
INTEGRATED CIRCUITS DIVISION
1.9.2 Truth Table for CPC7583xC and CPC7583xD
TESTIN
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TESTOUT
Switches
0
Off
On
Off
Off
Off
0
1
Off
Off
Off
Off
On
0
1
0
On
Off
Off
Off
Off
Simultaneous
TESTin and
TESTout
0
1
1
On
Off
Off
Off
On
Ringing
1
0
0
Off
Off
Off
On
Off
Ringing
Generator
Test
1
1
0
Off
Off
On
Off
Off
Simultaneous
TESTout and
Ringing
Generator
Test
1
1
1
Off
Off
On
Off
On
Latched
X
X
X
1
1
0
1
0
X
X
X
X
State
INRINGING
INTESTIN
INTESTOUT
Talk
0
0
TESTout
0
TESTin
All Off
Latch
0
TSD
1 or
Floating 1
Unchanged Unchanged Unchanged Unchanged Unchanged
02
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
1
If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally.
2
Forcing TSD to ground overrides the logic input pins and forces an all off state.
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13
CPC7583
INTEGRATED CIRCUITS DIVISION
2. Functional Description
2.1 Introduction
The CPC7583 has the following states:
• Talk. Loop break switches SW1, and SW2 closed, all
other switches open.
• Ringing. Ringing switches SW3, SW4 closed, all
other switches open.
• TESTout. Testout switches SW5, SW6 closed, all
other switches open.
• Ringing generator test. SW7, SW8 closed, all
other switches open.
• TESTin. Testin switches SW9 and SW10 closed.
• Simultaneous TESTin and TESTout. SW9, SW10,
SW5, and SW6 closed, all other switches open.
• Simultaneous test out and ringing generator
test. SW5, SW6, SW7, and SW8 closed, all other
switches open (only on the xC and xD versions).
• All Off. All switches open.
To protect the CPC7583 from an overvoltage fault
condition, the use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the TLINE and RLINE terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
recommended. With proper selection of the secondary
protector, a line card using the CPC7583 will meet all
relevant ITU, LSSGR, TIA/EIA and IEC protection
requirements.
The CPC7583 operates from a +5 V supply only. This
gives the device extremely low idle and active power
consumption and allows use with virtually any range of
battery voltage. The battery voltage is also used by the
CPC7583 as a reference for the integrated protection
circuit. In the event of a loss of battery voltage, the
CPC7583 enters the all-off state.
See “Truth Tables” on page 12 for more information.
The CPC7583 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple logic level input control.
Solid-state switch construction means no impulse
noise is generated when switching during ringing
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via
logic-level input so no additional driver circuitry is
required. The linear line break switches SW1 and
SW2 have exceptionally low RON and excellent
matching characteristics. The ringing switch SW4 has
a minimum open contact breakdown voltage of 465 V.
This is sufficiently high, with proper protection, to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
Integrated into the CPC7583 is an over voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC device during a fault condition. Positive and
negative surges are reduced by the current limiting
circuitry and hazardous potentials are diverted to
ground via diodes and the integrated SCR.
Power-cross potentials are also reduced by the current
limiting and thermal shutdown circuits.
14
2.2 Switch Logic
The CPC7583 provides, when switching from the
ringing state to the talk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the loop break switches SW1
and SW2 using simple logic-level input. This is
referred to as a make-before-break or
break-before-make operation. When the line break
switch contacts (SW1 and SW2) are closed (or made)
before the ringing access switch contacts (SW3 and
SW4) are opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing access contacts
(SW3 and SW4) are opened (broken) before the line
break switch contacts (SW1 and SW2) are closed
(made). With the CPC7583, the make-before-break
and break-before-make operations can easily be
selected by applying the proper sequence of logic
inputs to INTESTout, INRINGING, and INTESTin.
The logic sequences for either mode of operation are
given in “Make-Before-Break Operation (Ringing to Talk
Transition)” on page 15 and “Break-Before-Make Operation
(Ringing to Talk Transition)” on page 15. Logic states and
explanations are given in “Truth Tables” on page 12.
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CPC7583
INTEGRATED CIRCUITS DIVISION
Break-before-make operation can also be achieved
using the TSD pin as an input. In “Break-Before-Make
Operation (Ringing to Talk Transition)” on page 15, lines 2
and 3, it is possible to induce the switches to the all-off
state by grounding TSD instead of applying input to the
logic pins. This has the effect of overriding the logic
inputs and forcing the device to the all-off state. For
20 Hz ringing hold this input state for 25 ms. During
this hold period, toggle the inputs from the ringing
state to the talk state. After the 25 ms, release TSD to
return switch control to the input pins INTESTout,
INRINGING, INTESTin and the latch control pin.
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition)
State
Ringing
INRINGING INTESTIN INTESTOUT
1
0
TSD
Timing
0
Floating
-
SW4 waiting for next
zero-current crossing to turn
off. Maximum time is one-half
of ringing. In this transition
Floating state, current that is limited to
the dc break switch current
limit value will be sourced
from the ring node of the
SLIC.
Makebeforebreak
0
0
0
Talk
0
0
0
Latch
0
Zero-cross current has
occurred
Floating
Break
Ring
Ring All Other
Switches Return Access
Test
1 and 2 Switch 3 Switch 4 Switches
Off
On
On
Off
On
Off
On
Off
On
Off
Off
Off
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition)
State
INRINGING INTESTIN INTESTOUT
Latch
TSD
Timing
-
Ringing
1
0
0
Floating
All off
1
0
1
Hold this state for one-half of
Floating ringing cycle. SW4 waiting for
zero current to turn off.
0
Break
Ring
Ring All Other
Switches Return Access
Test
1 and 2 Switch 3 Switch 4 Switches
Off
On
On
Off
Off
Off
On
Off
All off
1
0
1
Floating
Zero current has occurred.
SW4 has opened
Off
Off
Off
Off
Talk
0
0
0
Floating
Close break switches
On
Off
Off
Off
2.3 Alternate Break-Before-Make Operation
Note that break-before-make operation can also be
achieved using TSD as an input. In lines 2 and 3 of the
table “Break-Before-Make Operation (Ringing to Talk
Transition)” on page 15, instead of using the logic input
pins to force the all-off state, force TSD to ground. This
overrides the logic inputs and also forces the all off
state. Hold this state for one-half of the ringing cycle.
During this TSD forced all-off state, change the inputs
R07
from the power ringing state (INRING = 1, INTESTIN = 0,
INTESTOUT = 0) to the talk state (INRING = 0,
INTESTIN = 0, INTESTOUT = 0). After the hold period,
release TSD to return switch control to the input pins
which will set the talk state.
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15
CPC7583
INTEGRATED CIRCUITS DIVISION
2.4 Data Latch
The CPC7583 has an integrated data latch. The latch
operation is controlled by logic-level input at the
LATCH pin. The data input of the latch are the input
pins, while the output of the data latch is an internal
node used for state control. When the LATCH control
pin is at logic 0, the data latch is transparent and data
control signals flow directly through to state control. A
change in input will be reflected by a change in switch
state. When the LATCH control pin is at logic 1, the
data latch is active and a change in input control will
not affect switch state. The switches will remain in the
position they were in when the LATCH changed from
logic 0 to logic 1 and will not respond to changes in
input as long as the latch is at logic 1. The TSD input is
not tied to the data latch. Therefore, TSD is not
affected by the LATCH input and the TSD input will
override state control.
2.5 TSD Behavior
Setting TSD to +5V allows switch control using the
logic inputs. This setting, however, also disables the
thermal shutdown circuit and is therefore not
recommended. When using logic control via the input
pins, TSD should be allowed to float. As a result, the
two recommended states when using TSD as a control
are 0, which forces the device to an all-off state, or
float, which allows logic inputs to remain active. This
requires the use of an open-collector type buffer.
2.6 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See IXYS Integrated Circuits
Division’s application note AN-144, Impulse Noise
Benefits of Line Card Access Switches for more
information. The attributes of ringing switch SW4 may
make it possible to eliminate the need for a zero-cross
switching scheme. A minimum impedance of 300 in
series with the ringing generator is recommended.
16
2.7 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7583. Switch state control is powered
exclusively by the +5 V supply. As a result, the
CPC7583 exhibits extremely low power consumption
during both active and idle states.
The battery voltage is not used for switch control but
rather as a supply for the integrated secondary
protection circuitry. The integrated SCR is designed to
trigger when the voltage at TBAT or RBAT drops 2 to
4 V below the applied voltage on the VBAT pin. This
trigger prevents a fault induced overvoltage event at
the TBAT or RBAT nodes.
2.8 Battery Voltage Monitor
The CPC7583 also uses the VBAT voltage to monitor
battery voltage. If battery voltage is lost, the CPC7583
immediately enters the all-off state. It remains in this
state until the battery voltage is restored. The device
also enters the all-off state if the system battery
voltage goes more positive than –10 V, and remains in
the all-off state until the battery voltage goes more
negative than –15 V. This battery monitor feature
draws a small current from the battery (less than 1 A
typical) and will add slightly to the device’s overall
power dissipation.
2.9 Protection
2.9.1 Diode Bridge/SCR
The CPC7583 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
conducted through the diode bridge to ground via
FGND. Voltage is clamped to a diode drop above
ground. During a negative transient of 2V to 4V more
negative than the voltage source at VBAT, the SCR
conducts and faults are shunted to FGND via the SCR
or the diode bridge.
In order for the SCR to crowbar or foldback, the on
voltage (see “Protection Circuitry Electrical
Specifications” on page 12) of the SCR must be less
negative than the VBAT voltage. If the VBAT voltage is
less negative than the SCR on voltage, or if the VBAT
supply is unable to source the trigger current, the SCR
will not crowbar.
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CPC7583
INTEGRATED CIRCUITS DIVISION
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
VBAT reference voltage by two to four volts, steering
the fault current to ground.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During the talk state when a 1000V 10x1000 S pulse
(GR-1089-CORE lightning) is applied to the line
though a properly clamped external protector, the
current into TLINE or RLINE will be a pulse with a typical
magnitude of 2.5 A and a duration of less than 0.5 s.
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
and is limited by the dynamic DC current limit
response of the two break switches. The DC current
limit, specified over temperature, is between 80 mA
and 425 mA, and the circuitry has a negative
temperature coefficient. As a result, if the device is
subjected to extended heating due to power cross
fault, the measured current at TLINE or RLINE will
decrease as the device temperature increases. If the
device temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
enter the all-off state.
the deactivation level of the thermal shutdown circuit.
This will permit the device to return to normal
operation. If the transient has not passed, current will
flow up to the value allowed by the dynamic DC
current limiting of the switches and heating will begin
again, reactivating the thermal shutdown mechanism.
This cycle of entering and exiting the thermal
shutdown mode will continue as long as the fault
condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector could activate and shunt all current to
ground.
2.11 External Protection Elements
The CPC7583 requires only over-voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional protection on the SLIC side.
The secondary protector must limit voltage transients
to levels that do not exceed the breakdown voltage or
input-output isolation barrier of the CPC7583. A
foldback or crowbar type protector is recommended to
minimize stresses on the CPC7583.
Consult IXYS Integrated Circuits Division’s application
note, AN-100, “Designing Surge and Power Fault
Protection Circuits for Solid State Subscriber
Line Interfaces” for equations related to the
specifications of external secondary protectors, fused
resistors and PTCs.
2.10 Temperature Shutdown
The thermal shutdown mechanism will activate when
the device temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, the
voltage out of the TSD pin will read 0 V. Normal output
of TSD is VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
transient, the device temperature will rise and the
thermal shutdown will activate forcing the switches to
the all-off state. At this point the current measured into
TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the device drops below
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17
CPC7583
INTEGRATED CIRCUITS DIVISION
3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC7583BA
MSL 1
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC7583BA
260°C for 30 seconds
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Pb
18
e3
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INTEGRATED CIRCUITS DIVISION
3.5 Mechanical Dimensions
3.5.1 CPC7583BA
0.2311 / 0.3175
(0.0091 / 0.0125)
PCB Land Pattern
17.983 / 18.085
(0.708 / 0.712)
10.109 / 10.516
(0.398 / 0.414)
7.391 / 7.595
(0.291 / 0.299)
Pin 1
0.508 / 1.016
(0.020 / 0.040)
1.80
(0.071)
9.50
(0.374)
0.254 / 0.737 x 45º
(0.010 / 0.029 x 45º)
2.438 / 2.642
(0.096 / 0.104)
0.366 / 0.467
(0.014/ 0.018)
1.27 TYP
(0.050 TYP)
1.27
(0.05)
2.235 / 2.438
(0.088 / 0.096)
0.60
(0.024)
Dimensions
mm MIN / mm MAX
(inches MIN / inches MAX)
0.660 ± 0.102
(0.026 ± 0.004)
3.5.2 CPC7583BATR Tape and Reel Specifications
P=12.00
(0.472)
330.2 DIA.
(13.00 DIA)
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
A0=10.90
(0.429)
B0=18.30
(0.720)
W=24.00+0.03/-0
(0.945+0.001/-0.0
K0=3.20
(0.126)
K1=2.70
(0.106)
Embossed Carrier
Embossment
Dimensions
mm
(inches)
Notes:
1. Unless otherwise specified, all dimensional tolerances per EIA standard 481
2. Unless otherwise specified, all dimensions ±0.10 (0.004)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specifications: DS-CPC7583-R07
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/18/2012
R07
www.ixysic.com
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