TI1 LMK01801 Dual clock divider buffer Datasheet

LMK01801
Dual Clock Divider Buffer
1.0 General Description
3.0 Features
The LMK01801 is a very low noise solution for clocking systems that require distribution and frequency division of precision clocks.
The LMK01801 features extremely low residual noise, frequency division, digital and analog delay adjustments, and
fourteen (14) programmable differential outputs: LVPECL,
LVDS and LVCMOS (2 outputs per differential output).
The LMK01801 features two independent inputs that can be
driven differentially (LVDS, LVPECL) or in single-ended mode
(LVCMOS, RF Sinewave). The first input drives output Bank
A consisting of eight (8) outputs. The second input drives output Bank B consisting of six (6) outputs.
■
■
■
■
2.0 Target Applications
•
•
•
•
•
•
High performance clock distribution and division
Wireless infrastructure
Datacom and telecom clock distribution
Medical imaging
Test and measurement
Military / Aerospace
■
■
■
■
■
■
Pin control mode or MICROWIRE (SPI)
Input and Output Frequency Range 1 kHz to 3.1 GHz
Separate Input for Clock Output Banks A & B.
14 Differential Clock Outputs in Two Banks (A & B)
— Output Bank A
■ 8 Differential, programmable outputs (Up to 8 as
LVCMOS)
■ Divider Values of 1 to 8, Even and Odd.
— Output Bank B
■ 6 Differential Outputs (or up to 12 as LVCMOS)
■ Divides values of 1 to 1045 or 1 to 8, even and odd
■ Analog and Digital Delays
50% duty cycle on all outputs for all divides
Separate Synchronization of Bank A and B.
RMS Additive jitter 50 fs at 800 MHz
— 50 fs RMS Additive jitter (12 kHz to 20 MHz)
Industrial Temperature Range: -40 to 85 °C
3.15 V to 3.45 V operation
Package: 48-pin LLP (7.0 x 7.0 x 0.8 mm)
30148701
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301487 SNAS573
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LMK01801 Dual Clock Distribution
January 16, 2012
LMK01801 Dual Clock Distribution
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Target Applications .......................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
4.0 Functional Configurations ................................................................................................................. 4
5.0 Connection Diagram ........................................................................................................................ 5
6.0 Pin Descriptions .............................................................................................................................. 6
7.0 Absolute Maximum Ratings .............................................................................................................. 8
8.0 Package Thermal Resistance ............................................................................................................ 8
9.0 Recommended Operating Conditions ................................................................................................ 8
10.0 Electrical Characteristics ................................................................................................................. 9
11.0 Typical Performance Characteristics .............................................................................................. 13
12.0 Serial MICROWIRE Timing Diagram .............................................................................................. 14
13.0 Measurement Definitions .............................................................................................................. 15
13.1 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY ................................................. 15
14.0 Features ..................................................................................................................................... 16
14.1 SYSTEM ARCHITECTURE ................................................................................................... 16
14.2 HIGH SPEED CLOCK INPUTS (CLKin0/CLKin0* and CLKin1/CLKin1*) ....................................... 16
14.3 CLOCK DISTRIBUTION ....................................................................................................... 16
14.4 SMALL DIVIDER (1 to 8) ....................................................................................................... 16
14.5 LARGE DIVIDER (1 to 1045 ) ................................................................................................ 16
14.6 CLKout ANALOG DELAY ...................................................................................................... 16
14.7 CLKout12 & CLKout13 DIGITAL DELAY .................................................................................. 16
14.8 PROGRAMMABLE OUTPUTS ............................................................................................... 16
14.9 CLOCK OUTPUT SYNCHRONIZATION .................................................................................. 16
14.10 DEFAULT CLOCK OUTPUTS .............................................................................................. 16
15.0 Functional Description .................................................................................................................. 17
15.1 PROGRAMMABLE MODE ..................................................................................................... 17
15.2 PIN CONTROL MODE .......................................................................................................... 17
15.3 INPUTS / OUTPUTS ............................................................................................................. 17
15.3.1 CLKin0 and CLKin1 .................................................................................................... 17
15.4 INPUT AND OUTPUT DIVIDERS ........................................................................................... 17
15.5 FIXED DIGITAL DELAY ........................................................................................................ 17
15.5.1 Fixed Digital Delay - Example ....................................................................................... 17
15.6 CLOCK OUTPUT SYNCHRONIZATION (SYNC) ...................................................................... 18
15.6.1 Dynamically Programming Digital Delay ......................................................................... 20
15.6.1.1 RELATIVE DYNAMIC DIGITAL DELAY ............................................................... 21
15.6.1.2 RELATIVE DYNAMIC DIGITAL DELAY - EXAMPLE ............................................. 21
16.0 General Programming Information ................................................................................................. 23
16.1 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 23
16.1.1 Overview ................................................................................................................... 23
16.2 REGISTER MAP .................................................................................................................. 23
16.3 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET .................................... 25
16.4 REGISTER R0 ..................................................................................................................... 27
16.4.1 RESET ...................................................................................................................... 27
16.4.2 POWERDOWN .......................................................................................................... 27
16.4.3 CLKoutX_Y_PD ......................................................................................................... 27
16.4.3.1 CLKinX_BUF_TYPE ......................................................................................... 27
16.4.3.2 CLKinX_DIV ..................................................................................................... 27
16.4.3.3 CLKinX_MUX ................................................................................................... 27
16.5 REGISTER R1 AND R2 ........................................................................................................ 27
16.5.1 CLKoutX_TYPE ......................................................................................................... 27
16.6 REGISTER R3 ..................................................................................................................... 28
16.6.1 CLKout12_13_ADLY ................................................................................................... 28
16.6.2 CLKout12_13_HS, Digital Delay Half Shift ..................................................................... 28
16.6.3 SYNC1_QUAL ........................................................................................................... 29
16.6.4 SYNCX_POL_INV ...................................................................................................... 29
16.6.5 NO_SYNC_CLKoutX_Y ............................................................................................... 29
16.6.6 SYNCX_FAST ........................................................................................................... 29
16.6.7 SYNCX_AUTO ........................................................................................................... 29
16.7 REGISTER R4 ..................................................................................................................... 29
16.7.1 CLKout12_13_DDLY, Clock Channel Digital Delay .......................................................... 29
16.8 REGISTER R5 ..................................................................................................................... 30
16.8.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay ...................... 30
16.8.2 CLKoutX_Y_DIV. Clock Output Divide ........................................................................... 30
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3
30
30
31
31
31
33
33
33
33
33
33
33
34
34
34
34
35
35
35
37
37
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LMK01801 Dual Clock Distribution
16.9 REGISTER 15 .....................................................................................................................
16.9.1 uWireLock .................................................................................................................
17.0 Application Information .................................................................................................................
17.1 POWER SUPPLY .................................................................................................................
17.1.1 Current Consumption ..................................................................................................
17.2 PIN CONNECTION RECOMMENDATIONS .............................................................................
17.2.1 Vcc Pins and Decoupling .............................................................................................
17.2.2 Unused clock outputs ..................................................................................................
17.2.3 Unused clock inputs ....................................................................................................
17.2.4 Bias ..........................................................................................................................
17.2.5 In MICROWIRE Mode .................................................................................................
17.3 THERMAL MANAGEMENT ...................................................................................................
17.4 DRIVING CLKin INPUTS .......................................................................................................
17.4.1 Driving CLKin Pins with a Differential Source ..................................................................
17.4.2 Driving CLKin Pins with a Single-Ended Source ..............................................................
17.5 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) .....................................................
17.5.1 Termination for DC Coupled Differential Operation ..........................................................
17.5.2 Termination for AC Coupled Differential Operation ..........................................................
17.5.3 Termination for Single-Ended Operation ........................................................................
18.0 Physical Dimensions ....................................................................................................................
19.0 Ordering Information ....................................................................................................................
LMK01801 Dual Clock Distribution
4.0 Functional Configurations
TABLE 1. Clock Output Configurations
Bank
Input
CLKin0/
CLKin0*
A
Clock Group
Output
CLKoutX/
CLKoutX*
Output Type
Outputs in
Divider
Group
Divider
Ratios
Delay
CG1
0 to 3
LVDS/
LVPECL
0 to 3
1 to 8
No
CG2
4 to 7
LVDS/
LVPECL/
LVCMOS
4 to 7
1 to 8
No
CG3
8 to 11
LVDS/
LVPECL/
LVCMOS
8 to 11
1 to 8
No
CG4
12 and 13
LVDS/
LVPECL/
LVCMOS
12 and 13
1 to 1045
(Note 1)
Digital and
Analog
(Note 2)
CLKin1/
CLKin1*
B
TABLE 2. Pin Control Mode for EN_PIN_CTRL = Low
Pin
Output Groups
Pin=Low
Pin=Middle
Pin=High
CLKoutTYPE_0
CLKout0 to CLKout3
CLKoutTYPE_1
CLKout4 to CLKout7
LVDS
Powerdown
LVPECL
LVDS
LVCOMS (Norm/Inv)
CLKoutTYPE_2
LVPECL
CLKout8 to CLKout13
LVDS
LVCMOS (Norm/Inv)
LVPECL
CLKoutDIV_0
CLKout0 to
CLKout3 Divider
÷1
÷4
÷2
CLKoutDIV_1
CLKout4 to
CLKout7 Divider
÷1
÷4
÷2
CLKout8 to
CLKout11 Divider
÷1
÷4
÷2
CLKout12 to
CLKout13 Divider
÷8
÷ 512
÷ 16
CLKoutDIV_2
TABLE 3. Pin Control Mode for EN_PIN_CTRL = High
Pin
CLKoutTYPE_0
Output Groups
Pin=Low
CLKout0 to CLKout3
LVDS
CLKout4 to CLkout7
Pin=Middle
LVPECL
LVCMOS (Norm/Inv)
Pin=High
LVPECL
CLKoutTYPE_1
CLKout8 to CLKout11
LVDS
LVCMOS (Norm/Inv)
LVPECL
CLKoutTYPE_2
CLKout12 to CLKout13
LVDS
LVCMOS (Norm/Inv)
LVPECL
CLKoutDIV_0
CLKout0 to
CLKout7 Dividers
÷1
÷4
÷2
CLKoutDIV_1
CLKout8 to
CLKout11 Divider
÷1
÷4
÷2
CLKoutDIV_2
CLKout12 to
CLKout13 Divider
÷4
÷ 512
÷ 16
Note 1: Digital Delay will not work if CLKout12_13_DIV = 1.
Note 2: See Section 10.0 Electrical Characteristics
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4
LMK01801 Dual Clock Distribution
5.0 Connection Diagram
48-Pin LLP Package
30148702
5
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LMK01801 Dual Clock Distribution
6.0 Pin Descriptions
(Note 3)
Pin Number
Name(s)
I/O
Type
1
LEuWire/
CLKoutDIV_2
Description
I
CMOS / 3-State
MICROWIRE Latch Enable Input /
Pin control mode: clock divider 2
2, 3
CLKout0
CLKout0*
O
Programmable
Clock output 0: LVDS or LVPECL
4, 5
CLKout1
CLKout1*
O
Programmable
Clock output 1: LVDS or LVPECL
6
Vcc1_CLKout
0_1_2_3
I
PWR
7, 8
CLKout2,
CLKout2*
O
Programmable
Clock output 2: LVDS or LVPECL
9. 10
CLKout3,
CLKout3*
O
Programmable
Clock output 3: LVDS or LVPECL
11
Test/
CLKoutTYPE_0
I
CMOS / 3-State
Reserved Test Pin /
Pin control mode: clock output type select 0
12
SYNC0/
CLKoutTYPE_1
I
CMOS / 3-State
SYNC0 / Pin control mode: clock output type select
1
13, 14
CLKin0/
CLKin0*
I
ANLG
Clock input 0. Supports clocking types including but
not limited to LVDS, LVPECL, and LVCMOS
15
Vcc2_CLKin0
I
PWR
Power supply for clock input 0
16, 17
CLKout4/
CLKout4*
O
Programmable
Clock output 4: LVDS, LVPECL, or LVCMOS
18, 19
CLKout5*/
CLKout5
O
Programmable
Clock output 5: LVDS, LVPECL, or LVCMOS
20
Vcc3_CLKout
4_5_6_7
I
PWR
Power supply for clock outputs 4, 5, 6, and 7
21, 22
CLKout6/
CLKout6*
O
Programmable
Clock output 6: LVDS, LVPECL, or LVCMOS
23, 24
CLKout7*/
CLKout7
O
Programmable
Clock output 7: LVDS, LVPECL, or LVCMOS
25
Vcc4_Bias
I
26
Bias
27
EN_PIN_CTRL
28, 29
Power supply for clock outputs 0, 1, 2, and 3
PWR
Power supply for Bias
ANLG
Bias bypass pin
I
3-State
Select MICROWIRE or pin control mode
CLKout8/
CLKout8*
O
Programmable
Clock output 8: LVDS, LVPECL, or LVCMOS
30, 31
CLKout9*/
CLKout9
O
Programmable
Clock output 9: LVDS, LVPECL, or LVCMOS
32
Vcc5_CLKout
8_9_10_11
I
PWR
Power supply for clock outputs 8, 9, 10, and 11
33, 34
CLKout10/
CLKout10*
O
Programmable
Clock output 10: LVDS, LVPECL, or LVCMOS
35, 36
CLKout11*/
CLKout11
O
Programmable
Clock output 11: LVDS, LVPECL, or LVCMOS
37
Vcc6_CLKin1
I
PWR
Power supply for clock input 1
38, 39
CLKin1/
CLKin1*
I
ANLG
Clock input 1. Supports clocking types including but
not limited to LVDS, LVPECL, and LVCMOS
40
SYNC1/
CLKoutTYPE_2
I
CMOS / 3-State
41
Vcc7_CLKout
12_13
I
PWR
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6
SYNC pin for CLKin1 and bank B.
Pin control mode: Clock output type select 2
Power supply for clock outputs 12, and 13
Name(s)
I/O
Type
42, 43
CLKout12/
CLKout12*
O
Programmable
Clock output 12: LVDS, LVPECL, or LVCMOS
44, 45
CLKout13*/
CLKout13
O
Programmable
Clock output 13: LVDS, LVPECL, or LVCMOS
46
Vcc8_DIG
I
PWR
47
DATAuWire/
CLKoutDIV_0
I
CMOS / 3-State
MICROWIRE DATA Pin / Pin control mode: Clock
divider 0
48
CLKuWire/
CLKoutDIV_1
I
CMOS / 3-State
MICROWIRE CLK Pin / Pin control mode: Clock
divider 1
DAP
DAP
GND
Description
Power supply for digital
DIE ATTACH PAD, connect to GND
Note 3: See Application Information section Section 17.2 PIN CONNECTION RECOMMENDATIONS for recommended connections.
7
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LMK01801 Dual Clock Distribution
Pin Number
LMK01801 Dual Clock Distribution
7.0 Absolute Maximum Ratings (Note 4, Note 5, Note 6)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Symbol
VCC
Ratings
Units
Supply Voltage (Note 7)
Parameter
-0.3 to 3.6
V
Input Voltage
VIN
-0.3 to (VCC + 0.3)
V
Storage Temperature Range
TSTG
-65 to 150
°C
Lead Temperature (solder 4 seconds)
TL
+260
°C
Differential Input Current (CLKinX/X*)
IIN
±5
mA
Moisture Sensitivty Level
MSL
3
Note 4: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only to the test conditions listed.
Note 5: This device is a high performance RF integrated circuit with an ESD rating up to 2.5 kV Human Body Model, up to 250 V Machine Model and up to 1,250
V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.
Note 6: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.
Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure
to absolute maximum ratings for extended periods can adversely affect device reliability.
Note 7: Never to exceed 3.6 V.
8.0 Package Thermal Resistance
48-Lead LLP
Parameter
Symbol
Ratings
Units
Thermal resistance from junction to ambient on
4-layer JEDEC board (Note 8)
θJA
26
°C/W
Thermal resistance from junction to case
(Note 9)
θJC
3
°C/W
Note 8: Specification assumes 9 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role
in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
Note 9: Case is defined as the DAP (die attach pad).
9.0 Recommended Operating Conditions
Parameter
Ambient
Temperature
Supply Voltage
Junction
Temperature
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Symbol
Condition
Min
Typical
Max
Unit
TA
VCC = 3.3 V
-40
25
85
°C
3.15
3.3
3.45
V
125
°C
VCC
TJ
8
(3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C,
at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Current Consumption
ICC_PD
ICC_CLKS
Power Down Supply Current
Supply Current with all clocks
enabled (Note 11)
1
All clock delays disabled,
CLKoutX_Y_DIV = 1,
CLKoutX_TYPE = 1 (LVDS),
313
mA
390
mA
CLKin0/0* and CLKin1/1* Input Clock Specifications
fCLKinX
Clock 0 or 1 Input Frequency
SLEWCLKin
Slew Rate on CLKin
(Note 12)
DUTYCLKin
Clock input duty cycle
VCLKin
VIDCLKin
VSSCLKin
VIDCLKin
VSSCLKin
Clock Input,
Single-ended Input Voltage
Clock Input
Differential Input Voltage
(Note 10)
(Note 18)
VCLKinX-offset
DC offset voltage between
CLKinX/CLKinX*
CLKinX* - CLKinX
VCLKin- VIH
Maximum input voltage
VCLKin- VIL
Minimum input voltage
VCLKinX-offset
DC offset voltage between
CLKinX/CLKinX*
CLKinX* - CLKinX
CLKinX_MUX = Bypassed
CLKoutX_Y_DIV = 1
0.001
3100
MHz
CLKinX_MUX = Bypassed
CLKoutX_Y_DIV = 2 to 8
.001
1600
MHz
CLKin_MUX = Divide
CLKinX_DIV = 1 to 8
.001
3100
MHz
20% to 80%
0.15
0.5
V/ns
50
%
AC coupled to CLKinX; CLKinX* AC
coupled to Ground
(CLKinX_BUF_TYPE = Bipolar
0.25
2.4
Vpp
AC coupled to CLKinX; CLKinX* AC
coupled to Ground
(CLKinX_BUF_TYPE = MOS
0.25
2.4
Vpp
AC coupled
(CLKinX_BUF_TYPE = Bipolar
0.25
1.55
|V|
0.5
3.1
Vpp
AC coupled
(CLKinX_BUF_TYPE = MOS
0.25
1.55
|V|
0.5
3.1
Vpp
Each pin AC coupled
CLKinX_BUF_TYPE = Bipolar
DC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = MOS
Each pin AC coupled
CLKinX_BUF_TYPE = MOS
9
0
mV
0
mV
2.0
VCC
V
0.0
0.4
V
55
mV
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LMK01801 Dual Clock Distribution
10.0 Electrical Characteristics
LMK01801 Dual Clock Distribution
Symbol
Parameter
VIH
High-Level Input Voltage
Conditions
Min
Typ
Max
Units
VCC
V
Digital Inputs (CLKuWire, DATAuWire, LEuWire) for EN_PIN_CTRL = MIDDLE
1.2
VIL
Low-Level Input Voltage
0.4
V
IIH
High-Level Input Current
VIH = VCC
-5
5
µA
IIL
Low-Level Input Current
VIL = 0
-5
5
µA
VCC
V
0.4
V
Digital Inputs (SYNC0, SYNC1) for EN_PIN_CTRL = MIDDLE
VIH
High-Level Input Voltage
1.2
VIL
Low-Level Input Voltage
IIH
High-Level Input Current
VIH = VCC
VIH = VCC
-5
5
µA
IIL
Low-Level Input Current
VIL = 0 V
VIL = 0
-40
-5
µA
Digital Inputs (CLKuWire, DATAuWire, LEuWire, SYNC0, SYNC1) for EN_PIN_CTRL= Low or High
VIH
High-Level Input Voltage
2.6
VCC
V
VIM
Mid-Level Input Voltage
1.3
1.85
V
VIL
Low-Level Input Voltage
0.7
V
100
µA
10
µA
IIH
High-Level Input Current
IIM
Mid-Level Input Current
IIL
Low-Level Input Current
VIH = VCC
-10
VIL= 0
-100
µA
Clock Skew and Delay
CLKoutX to CLKoutY
(Note 13), (Note 14)
TSKEW
LVDS-to-LVDS, T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
AC coupled, Within same Divider
3
LVPECL-to-LVPECL, T = 25 °C
FCLK = 800 MHz, RL= 100 Ω
3
emitter resistors = 240 Ω to GND
AC coupled, Within same Divider
RL = 50 Ω, CL = 10 pF,
Skew between any two LVCMOS
outputs, same CLKout or different T = 25 °C, FCLK = 100 MHz, Within
CLKout (Note 13), (Note 14)
same Divider
LVPECL to LVDS skew
MixedTSKEW
CLKoutX CLKoutY
LVCMOS to LVPECL skew
FADLY
Maximum Analog
Delay Frequency
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LVDS to LVCMOS skew
50
32
Same device, T = 25 °C,
250 MHz, Within same Divider
830
ps
800
1536
10
ps
MHz
Parameter
Conditions
fCLKout
Maximum Clock Frequency
(Note 14, Note 15)
VOD
Differential Output Voltage
(Note 10)
(Note 18)
ΔVOD
Change in Magnitude of VOD for
complementary output states
Min
Typ
Max
Units
LVDS Clock Outputs (CLKoutX)
RL = 100 Ω
1600
MHz
225
T = 25 °C, DC measurement
AC coupled to receiver input
R = 100 Ω differential termination
400
-50
575
mV
50
mV
1.375
V
35
|mV|
VOS
Output Offset Voltage
ΔVOS
Change in VOS for complementary
output states
TR
Output Rise Time
20% to 80%, RL = 100 Ω
200
ps
TF
Output Fall Time
80% to 20%, RL = 100 Ω
300
ps
ISA
ISB
Output short circuit current - single
ended
Single-ended output shorted to
GND, T = 25 °C
-24
24
mA
ISAB
Output short circuit current differential
Complimentary outputs tied
together
-12
12
mA
1.125
1.25
LVPECL Clock Outputs (CLKoutX)
TR
Output Rise Time
TF
Output Fall Time
fCLKout
Maximum Clock Frequency
(Note 14, Note 15)
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
20% to 80%, RL = 100 Ω,
emitter resistors = 240 Ω to GND
80% to 20%, RL = 100 Ω,
emitter resistors = 240 Ω to GND
200
ps
200
ps
Low Common-Mode Voltage PECL (LCPECL) (Note 16), (Note 17)
RL = 100 Ω,
emitter resistors = 240 Ω to GND
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 0.6 V
3100
535
MHz
1.6
V
0.75
V
840
1145
mV
1600 mV LVPECL (LVPECL) Clock Outputs (CLKoutX)
fCLKout
Maximum Clock Frequency
(Note 14, Note 15)
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
RL = 100 Ω,
emitter resistors = 240 Ω to GND
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V
3100
585
MHz
VCC - 0.94
V
VCC - 1.9
V
925
1240
mV
2000 mV LVPECL (2VPECL) Clock Outputs (CLKoutX)
fCLKout
Maximum Clock Frequency
(Note 14, Note 15)
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
RL = 100 Ω,
emitter resistors = 240 Ω to GND
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.3 V
11
3100
MHz
VCC - 0.97
V
VCC - 1.95
705
1150
V
1585
mV
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LMK01801 Dual Clock Distribution
Symbol
LMK01801 Dual Clock Distribution
Symbol
Parameter
Conditions
Min
Typ
Max
Units
fCLKout
Maximum Clock Frequency
(Note 14, Note 15)
5 pF Load
250
MHz
VOH
Output High Voltage
1 mA Load
VCC - 0.1
V
LVCMOS Clock Outputs (CLKoutX)
VOL
Output Low Voltage
1 mA Load
IOH
Output High Current (Source)
VCC = 3.3 V, VO = 1.65 V
28
mA
IOL
Output Low Current (Sink)
VCC = 3.3 V, VO = 1.65 V
28
mA
DUTYCLK
Output Duty Cycle
(Note 14)
VCC/2 to VCC/2, FCLK = 100 MHz, T
= 25 °C
TR
Output Rise Time
20% to 80%, RL = 50 Ω,
CL = 5 pF
400
ps
TF
Output Fall Time
80% to 20%, RL = 50 Ω,
CL = 5 pF
400
ps
0.1
45
50
55
V
%
MICROWIRE Interface Timing
TECS
LE to Clock Set Up Time
See MICROWIRE Input Timing
25
ns
TDCS
Data to Clock Set Up Time
See MICROWIRE Input Timing
25
ns
TCDH
Clock to Data Hold Time
See MICROWIRE Input Timing
8
ns
TCWH
Clock Pulse Width High
See MICROWIRE Input Timing
25
ns
TCWL
Clock Pulse Width Low
See MICROWIRE Input Timing
25
ns
TCES
Clock to LE Set Up Time
See MICROWIRE Input Timing
25
ns
TEWH
LE Pulse Width
See MICROWIRE Input Timing
25
ns
TCR
Falling Clock to Readback Time
See MICROWIRE Readback
Timing
25
ns
Note 10: See applications section Section 13.1 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY for definition of VID and VOD voltages.
Note 11: For Icc for specific part configuration, see applications section Section 17.1.1 Current Consumption for calculating Icc.
Note 12: The minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin
to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode
noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the
device outputs.
Note 13: Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
Note 14: Guaranteed by characterization.
Note 15: Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.
Note 16: For LCPECL, the common mode voltage is regulated (VOH=1.6V, VOL=VOH-Vsw, Vcm=(VOH+VOL)/2 ) and is more stable against with PVT (process,
supply, temperature) variations than conventional LVPECL implementations..
Note 17: With proper selection of external emitter resistors, LCPECL can also be used for DC-coupling with devices with low common voltage such as 0.5V or
0,8V etc.
Note 18: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.
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12
LMK01801 Dual Clock Distribution
11.0 Typical Performance
Characteristics
Unless otherwise specified: Vdd=3.3V, TA=25 °C
LVDS VSS vs. Frequency (Note 19)
LVPECL VSS vs. Frequency (Note 19)
2.0
DIFFERENTIAL P-P VOLTAGE (V)
DIFFERENTIAL P-P VOLTAGE (V)
1.0
0.8
0.6
0.4
0.2
0.0
0
400
800
1200 1600
FREQUENCY (MHz)
LVPECL 2V Mode
1.5
LVPECL 1.6V Mode
1.0
LCPECL Mode
0.5
0.0
2000
0
500
1000 1500 2000 2500 3000
FREQUENCY (MHz)
30148779
30148776
LVCMOS Vpp vs. Frequency
Typical Dynamic ICC, CL = 5 pF
80
3.5
5 pF Load
3.0
60
2.5
ICC (mA)
SINGLE ENDED P-P VOLTAGE (V)
4.0
10 pF Load
2.0
22 pF Load
1.5
1.0
40
20
0.5
0.0
0
0
100
200
300
400
FREQUENCY (MHz)
500
0
50 100 150 200 250 300 350 400
FREQUENCY (MHz)
30148778
30148777
LVDS & LVCMOS Noise Floor vs. Frequency
-140
-145
-145
-150
LVPECL (differential)
-150 Re=240 Ω
NOISE FLOOR (dBc/Hz)
NOISE FLOOR (dBc/Hz)
LVPECL Noise Floor vs. Frequency
-155
-160
-165
-170
-175
LVPECL (differential)
Re=120 Ω
LVDS (differential)
-160
-165
-170
-175
-180
10
-155
LVCMOS
-180
100
1k
FREQUENCY (MHz)
10k
10
30148780
100
1k
FREQUENCY (MHz)
10k
30148781
13
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LMK01801 Dual Clock Distribution
Note 19: See Section 13.1 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY for a description of VSS.
12.0 Serial MICROWIRE Timing Diagram
30148703
FIGURE 1. MICROWIRE Timing Diagram
Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal.
On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A slew rate of at least
30 V/µs is recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should
be returned to a low state.
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14
13.1 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading
datasheets or communicating with other engineers. This section will address the measurement and description of a differential
signal so that the reader will be able to understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and
non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being
described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to
the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this
signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes
with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first section
Figure 2 illustrates the two different definitions side-by-side for inputs and Figure 3 illustrates the two different definitions side-byside for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between
with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference,
the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the
peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP).
30148775
30148774
FIGURE 2. Two Different Definitions for
Differential Input Signals
FIGURE 3. Two Different Definitions for
Differential Output Signals
15
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LMK01801 Dual Clock Distribution
13.0 Measurement Definitions
LMK01801 Dual Clock Distribution
14.0 Features
When adjusting analog delay, glitches may occur on the clock
outputs being adjusted.
14.1 SYSTEM ARCHITECTURE
The LMK01801 is a dual clock buffer which allows separate
clock domains on the same IC with options to divide and delay
signals.
The LMK01801 consists of two separate buffer banks, each
with its own input divider, output dividers and programmable
control of clock output channels.
• Bank A has two clock output groups, see the Section 4.0
Functional Configurations for more details.
• Bank B has two clock output groups, one of which has
analog and digital delay. See the Section 4.0 Functional
Configurations for more details.
Each bank has it own common input divider and is then divided into output groups which share an output divider.
The LMK01801 comes in a 48-pin LLP package.
14.7 CLKout12 & CLKout13 DIGITAL DELAY
CLKout12 and CLKout13 includes a coarse (digital) delay for
phase adjustment of the clock outputs.
The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in normal
mode, or from 12.5 to 522 clock cycles in extended mode. The
delay step can be as small as half the period of the clock distribution path by using the CLKout12_13_HS bit. e.g. 2 GHz
clock frequency without using CLKin1 input clock divider results in 250 ps coarse tuning steps.
The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.
There are 2 different ways to use the digital (coarse) delay.
1. Fixed Digital Delay
2. Relative Dynamic Digital Delay
These are further discussed in the Functional Description.
14.2 HIGH SPEED CLOCK INPUTS (CLKin0/CLKin0* and
CLKin1/CLKin1*)
The LMK01801 has two clock inputs, CLKin0 and CLKin1
which can be driven differentially or single-ended. See Section 17.4 DRIVING CLKin INPUTS for more information. Each
input has a 2 to 8 divider that may be enabled or bypassed.
14.8 PROGRAMMABLE OUTPUTS
The outputs of the LMK01801 are programmable in a combination of output types based on Table 1. Programming the
outputs is by MICROWIRE or by pin control mode based on
the state of EN_PIN_CTRL pin.
Any LVPECL output type can be programmed to LCPECL,
1600, or 2000 mVpp amplitude levels. The 2000 mVpp
LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000 mVpp differential swing for
compatibility with many data converters and is also known as
2VPECL.
14.3 CLOCK DISTRIBUTION
The LMK01801 features a total of 14 differential outputs.
CLKout0 through CLKout7 are driven from CLKin0 and CLKout8 through CLKout13 are driven from CLKin1.
14.4 SMALL DIVIDER (1 to 8)
There are three small dividers which drive CLKout0 to CLKout3, CLKout4 to CLKout7, and CLKout8 to CLKout 11. These
dividers support a divide range of 1 to 8 (even and odd).
14.9 CLOCK OUTPUT SYNCHRONIZATION
Using the SYNC input causes all active clock outputs to share
a rising edge. See Section 15.6 CLOCK OUTPUT SYNCHRONIZATION (SYNC) for more information.
The SYNC event also causes the digital delay value to take
effect.
14.5 LARGE DIVIDER (1 to 1045 )
The divider for CLKout12 and CLKout13 supports a divide
range of 1 to 1045 (even and odd). When divides of 26 or
greater are used, the divider/delay block uses extended
mode.
14.10 DEFAULT CLOCK OUTPUTS
The power on reset sets the device to operate with all outputs
active in bypass mode (no divide) with LVDS output type. In
this way the device can be used without programming for fanout purposes.
14.6 CLKout ANALOG DELAY
Clock outputs 12 and 13 include a fine (analog) delay for
phase adjustment of the clock outputs.
The fine (analog) delay allows a nominal 25 ps step size and
range from 0 to 475 ps of total delay. Enabling the analog
delay adds a nominal 500 ps of delay in addition to the programmed value.
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16
CLKout12_13_DDL CLKout12_13_HS
Y
15.1 PROGRAMMABLE MODE
When the EN_PIN_CTRL pin is floating (default by internal
pull-up/pull-down) then programming is via MICROWIRE.
See Table 1 for a description of available programming options for the LMK01801 in programmable mode.
15.2 PIN CONTROL MODE
The LMK01801 provides for an alternate function of the MICROWIRE (uWire) pins. This pin control mode is set by the
logic of the EN_PIN_CTRL pin to provide limited control of the
outputs and dividers.
When the EN_PIN_CTRL pin is set high or low (not open) then
the output states can be programmed by pins, eliminating the
need for an external FPGA or CPU.
If EN_PIN_CTRL is LOW then Table 2 in Section 4.0 Functional Configurations defines how the outputs and dividers are
configured.
If EN_PIN_CTRL is HIGH then Table 3 in Section 4.0 Functional Configurations defines how the outputs and dividers are
configured.
15.3.1 CLKin0 and CLKin1
There are two clock inputs CLKin0 and CLKin1. CLKin0 provides the input for output Bank A and CLKin1 provides the
input for the output Bank B. Each input has it's own divider (2
to 8) that may be bypassed.
15.4 INPUT AND OUTPUT DIVIDERS
This section discusses the recommended usage of input and
output dividers.
Clock inputs 0 and 1 each have an associated divider (2 to 8)
that may be enabled or bypassed.
Clock groups 1, 2 and 3 have small output dividers (1 to 8).
Clock group 4 (CLKout12 and CLKout13) has a large output
divider (1 to 1045).
While the input and output clock dividers may be used in any
combination the recommended operating frequency ranges
are shown in the table below to minimize the phase noise
floor:
Output Divider
Max Frequency
Divide = 1
3.1 GHz
Bypassed
Divide > 1
1.6 GHz
Divide = 2 to 8
Divide = 1 to 8
3.1 GHz
1
5
0
4.5
5
6
1
5.5
6
0
6
7
1
6.5
7
0
7
...
...
...
520
0
520
521
1
520.5
521
0
521
522
1
521.5
522
0
522
15.5.1 Fixed Digital Delay - Example
Given a CLKin1 clock frequency of 983.04 MHz as input to
CG4, by using digital delay the outputs can be adjusted in 1 /
(2 * 983.04 MHz) = ~509 ps steps (Assumes CLKin1_MUX =
bypass).
To achieve a quadrature (90 degree) phase shift on 122.88
MHz outputs between CLKout12 and CLKout11 from a clock
frequency of 983.04 MHz program:
• Clock output divider to 8. CLKout8_11 = 8 and
CLKout12_13_DIV = 8
• Set clock digital delay value. CLKout12_13_DDLY = 5,
CLKout12_13_HS = 0.
The frequency of 122.88 MHz has a period of ~8.14 ns. To
delay 90 degrees of a 122.88 MHz clock period requires a
~2.03 ns delay. Given a digital delay step of ~509 ps, this
requires a digital delay value of 4 steps (2.03 ns / 509 ps = 4).
Since the 4 steps are half period steps, CLKout12_13_DDLY
is programmed 2 full periods beyond 5 for a total of 7.
Table 5 shows some of the possible phase delays in degrees
achievable in the above example.
Input and Output Divider Input Frequency Ranges
Bypassed
5
The CLKout12_13_DDLY value only takes effect during a
SYNC event and if the NO_SYNC_CLKout12_13 bit is
cleared for this clock group. See Section 15.6 CLOCK OUTPUT SYNCHRONIZATION (SYNC) for more information.
The resolution of digital delay is related to the frequency at
the input to the Clock Group 4 (CG4) clock distribution path.
Digital Delay Resolution = 1 / (2 * Clock Frequency)
The digital delay between clock outputs can be dynamically
adjusted with minimum or no disruption of the output clocks.
See Section 15.6.1 Dynamically Programming Digital Delay
for more information.
15.3 INPUTS / OUTPUTS
Input Divider
Digital Delay
15.5 FIXED DIGITAL DELAY
This section discusses Fixed Digital Delay and associated
registers.
Clock outputs 12 and 13 may be delayed relative to CLKout8
to CLKout 11 by up to 517.5 clock distribution path periods if
divide is 1 and 518.5 clock distribution path periods if divide
is greater than 1. By programming a digital delay value from
4.5 to 522 clock distribution path periods, a relative clock output delay from 0 to 517.5 periods is achieved. The
CLKout12_13_DDLY register sets the digital delay as shown
in the table Table 4.
TABLE 5. Relative phase shift from
CLKout12 and CLKout13 to CLKout8 to CLKout11
CLKout12_ CLKout12_
13_DDLY
13_HS
17
Relative
Digital
Delay
Degrees of
122.88 MHz
5
1
-0.5
-23°
5
0
0.0
0°
6
1
0.5
23°
6
0
1.0
45°
7
1
1.5
68°
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LMK01801 Dual Clock Distribution
TABLE 4. Possible Digital Delay Values
15.0 Functional Description
LMK01801 Dual Clock Distribution
CLKout12_ CLKout12_
13_DDLY
13_HS
Relative
Digital
Delay
Degrees of
122.88 MHz
Refer to Section 15.6.1 Dynamically Programming Digital Delay for SYNC functionality when SYNC_QUAL = 1.
TABLE 6. Steady State Clock Output Condition
Given Specified Inputs
7
0
2.0
90°
8
1
2.5
113°
8
0
3.0
135°
SYNC_POL
_INV
SYNC Pin
Clock Steady
State
9
1
3.5
158°
0
0
Active
180°
0
1
Low
0
Low
1
Active
9
0
4.0
10
1
4.5
203°
1
10
0
5.0
225°
1
11
1
5.5
248°
11
0
6.0
270°
12
1
6.5
293°
12
0
7.0
315°
13
1
7.5
338°
13
0
8.0
360°
...
...
...
...
Methods of Generating SYNC
There are three methods to generate a SYNC event:
• Manual:
— Asserting the SYNC pin according to the polarity set by
SYNC_POL_INV.
— Toggling the SYNC_POL_INV bit though MICROWIRE
will cause a SYNC to be asserted.
• Automatic:
— Programming Register R4 when SYNC_EN_AUTO =
1 will generate a SYNC event for Bank B.
— Programming Register R5 when SYNC_EN_AUTO =
1 will generate a SYNC event for both Bank A and Bank
B.
Due to the high speed of the clock distribution path (as fast
as ~322 ps period) and the slow slew rate of the SYNC, the
exact clock cycle at which the SYNC is asserted or unasserted by the SYNC is undefined. The timing diagrams show a
sharp transition of the SYNC to clarify functionality.
Avoiding clock output interruption due to SYNC
If a clock output has the NO_SYNC_CLKoutX_Y bits set they
will be unaffected by the SYNC event. It is possible to perform
a SYNC operation with the NO_SYNC_CLKoutX_Y bit
cleared, set the NO_SYNC_CLKoutX_Y bits so that the selected clocks will not be affected by a future SYNC. Future
SYNC events will not effect these clocks but will still cause
the newly synchronized clocks to be resynchronized using the
currently programmed digital delay values. When this happens, the phase relationship between the first group of synchronized clocks and the second group of synchronized
clocks will be undefined. Except for CLKout12 and CLKout13
when synced using qualification mode. See Section 15.6.1
Dynamically Programming Digital Delay.
SYNC Timing
When discussing the timing of the SYNC function, one cycle
refers to one period of the clock distribution path.
Figure 5 illustrates clock outputs programmed with different
digital delay values during a SYNC event.
Refer to Section 15.6.1 Dynamically Programming Digital Delay for more information on dynamically adjusting digital delay.
15.6 CLOCK OUTPUT SYNCHRONIZATION (SYNC)
The purpose of the SYNC function is to synchronize the clock
outputs with a fixed and known phase relationship between
each clock output selected for SYNC. SYNC can also be used
to hold the outputs in a low or 0 state. The
NO_SYNC_CLKoutX_Y bits can be set to disable synchronization for a clock group.
The digital delay value set by CLKout12_13_DDLY takes effect only upon a SYNC event. The digital delay due to
CLKout12_13_HS takes effect immediately upon programming. See Section 15.6.1 Dynamically Programming Digital
Delay for more information on dynamically changing digital
delay.
It is necessary to ensure that the CLKin1 signal is stable before a sync event occurs when CLKout12_13_DIV is greater
than 1.
Effect of SYNC
When SYNC is asserted, the outputs to be synchronized are
held in a logic low state. When SYNC is unasserted, the clock
outputs to be synchronized are activated and will transition to
a high state simultaneously with one another except where
digital delay values have been programmed.
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18
LMK01801 Dual Clock Distribution
30148704
FIGURE 4. Clock Output synchronization using the SYNC1 pin (SYNC1 is Active Low, SYNC1_POL_INV=0)
CLKout8_11_DIV = 1
CLKout12_13_DIV = 2
The digital delay for clock outputs 12 and 13 is 5
The digital delay half step for all clock outputs is 0
SYNC1_QUAL = 0 (No qualification)
CLKout12_ADLY_SEL & CLKout13_ADLY_SEL is 0
Refer to Figure 4 during this discussion on the timing of
SYNC. SYNC must be asserted for greater than one clock
cycle of the clock distribution path to register the SYNC event.
After SYNC is asserted the SYNC event will begin on the following rising edge of the distribution path clock, at time A.
After this event has been registered, the outputs will not reflect
the low state for 4.5 cycles for CLKout0 - CLKout11 at time B
or 5.5 cycles for CLKout12 and CLKout 13 if divide = 1 or 6.5
cycles for CLKout12 and CLKout13 if divide > 1, at time C.
Due to the asynchronous nature of SYNC with respect to the
output clocks, it is possible that a runt pulse could be created
when the clock output goes low from the SYNC event. This is
shown by CLKout12-13. See Section 15.6.1.2 RELATIVE
DYNAMIC DIGITAL DELAY - EXAMPLE for more information
on synchronizing relative to an output clock to eliminate or
minimize this runt pulse for CLKout12 or CLKout13.
After SYNC becomes unasserted the event will be registered
on the following rising edge of the distribution path clock, time
D. Clock outputs 0 through 11 will rise at time E, coincident
with a rising distribution clock edge that occurs after 5 cycles
for CLKout0 to CLKout 11 and for CLKout12 to CLKout13 if
CLKout12_13_DIV = 1. If CLKout12_13_DIV > 1 then the rising edge of CLKout12-CLKout13 will occur after 6 cycles of
the distribution path at time F plus as many more cycles as
programmed by the digital delay for that clock output path.
The CLKout12 and CLKout13 will rise at time G, which is the
Digital Delay value plus 5 cycles when CLKout12_13_DIV =
1 or 6 cycles when CLKout12_13_DIV > 1.
See Figure 5 for further SYNC timing detail using different
digital delays.
19
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LMK01801 Dual Clock Distribution
30148705
FIGURE 5. Clock Output synchronization using the SYNC pin (SYNC is Active Low, SYNC_POL_INV=1)
Case 1: CLKout12_13_DIV = 2, CLKout12_13_DDLY = 5
Case 2: CLKout12_13_DIV = 2, CLKout12_13_DDLY = 7
Case 3: CLKout12_13_DIV = 2, CLKout12_13_DDLY = 8
Case 1: CLKout12_13_HS = 1
Case 2: CLKout12_13_HS = 0
Case 3: CLKout12_13_HS = 0
SYNC1_QUAL = 0 (No qualification)
CLKout12_ADLY_SEL & CLKout13_ADLY_SEL is 0
Figure 5 illustrates the timing with various digital delays programmed.
• Time A) SYNC assertion event is registered.
• Time B) SYNC unassertion registered.
• Time C) All outputs toggle and remain low. A runt pulse
can occur at this time as shown.
• Time D) After 6 + 4.5 = 10.5 cycles, in Case 1, CLKout12
rises.
• Time E) After 6 + 7 = 13 cycles, in Case 2, CLKout12 rises.
• Time F) After 6 + 8 = 14 cycles, Case 3, CLKout12 rises.
• Note: CLKout 12 and CLKout 13 are driven by the same
divider and delay circuit, therefore, their timing is always
the same except when analog delay is used.
same, then a relative dynamic digital delay adjust is performed. Clocks with NO_SYNC_CLKoutX_Y = 1 are defined
as clocks not being adjusted. These clocks operate without
interruption.
SYNC and Minimum Step Size
The minimum step size adjustment for digital delay is half a
clock distribution path cycle. This is achieved by using the
CLKout12_13_HS bit. The CLKout12_13_HS bit change effect is immediate without the need for SYNC. To shift digital
delay using CLKout12_13_DDLY, a SYNC signal must be
generated for the change to take effect.
Programming Overview
To dynamically adjust the digital delay with respect to an existing clock output the device should be programmed as
follows:
• Set SYNC1_QUAL = 3 for clock output qualification.
• Set NO_SYNC_CLKout12_13 = 0 to enable
synchronization on CLKout12 and CLKout13.
• Set CLKout12_ADLY_SEL = 0.
• Set NO_SYNC_CLKoutX_Y = 1 for the output clocks,
except CLKout12 and CLKout13, that will continue to
operate during the SYNC event. There is no interruption
of output on these clocks.
• The SYNC_EN_AUTO bit may be set to cause a SYNC
event to begin when register R4 is programmed. The auto
SYNC feature is a convenience since it does not require
the application to manually assert SYNC by toggling the
SYNC_POL_INV bit or the SYNC pin when changing
digital delay.
Internal Dynamic Digital Delay Timing
Once SYNC is qualified by an output clock, 1.5 cycles later
an internal one shot pulse will occur. The width of the one shot
pulse is 3 cycles. This internal one shot pulse will cause the
15.6.1 Dynamically Programming Digital Delay
To use dynamic digital delay synchronization qualification set SYNC1_QUAL = 3. This causes the SYNC pulse to
be qualified by a clock output so that the SYNC event occurs
after a specified time from a clock output transition. This allows the relative adjustment of clock output phase in real-time
with no or minimum interruption of clock outputs. Hence the
term dynamic digital delay.
Note that changing the phase of a clock output requires momentarily altering in the rate of change of the clock output
phase and therefore by definition results in a frequency distortion of the signal.
Without qualifying the SYNC with an output clock, the newly
synchronized clocks would have a random and unknown digital delay (or phase) with respect to clock outputs not currently
being synchronized. Only CLKout12 can be used as a qualifying clock.
Relative Dynamic Digital Delay
When the qualifying clock digital delay is being adjusted, because the qualifying clock and the adjusted clock are the
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20
CLKout12_13_HS
Odd
Must = 1 during SYNC event.
Even
Must = 0 during SYNC event.
Purpose
SYNC1_QUAL = 3
Use clock output for
qualifying the SYNC pulse for
dynamically adjusting digital
delay.
Clock output 8 (983.04 MHz)
won't be affected by SYNC. It
NO_SYNC_CLKout7_11 = 1
will operate without
interruption.
TABLE 7. Half Step programming requirement of
qualifying clock during SYNC event
CLKout12_13_DIV value
Register
SYNC1_AUTO = 0 (default)
Automatically generation of
SYNC is not allowed
because of the half step
requirement.
SYNC must be generated
manually by toggling the
SYNC_POL_INV bit or the
SYNC pin.
After the above registers have been programmed, the application may now dynamically adjust the digital delay of the
491.52 MHz clocks.
Step 3: Adjust digital delay of CLKout12 by one step.
Refer to Table 8 for the programming sequence to step one
half clock distribution period forward or backwards.
15.6.1.1 RELATIVE DYNAMIC DIGITAL DELAY
Relative dynamic digital delay can be used to program a clock
output to a specific phase offset from another clock output.
Pros:
• Direct phase adjustment with respect to same clock
output.
• Possible glitch pulses from clock output will always be the
same during digital delay adjustment transient.
TABLE 8. Programming sequence for one step adjust
Cons:
• For some clock divide values there may be a glitch pulse
due to SYNC assertion.
• Adjustments of digital delay requiring the half step bit
(CLKout12_13_HS) for finer digital delay adjust is
complicated due to the half step requirement in Table 7
above.
15.6.1.2 RELATIVE DYNAMIC DIGITAL DELAY EXAMPLE
To illustrate the relative dynamic digital delay adjust procedure, consider the following example.
System Requirements:
• CLKin1 Frequency = 983.04 MHz
• CLKout8 = 983.04 MHz (CLKout8_11_DIV = 1)
• CLKout12 = 491.52 MHz (CLKout12_13_DIV = 2)
• During initial programming:
— CLKout12_13_DDLY = 5
— CLKout12_13_HS = 0
— NO_SYNC_CLKoutX_Y = 0
Step direction and current
HS state
Programming Sequence
Adjust clock output one step
forward.
CLKout12_13_HS = 0.
1. CLKout12_13_HS = 1.
Adjust clock output one step
forward.
CLKout12_13_HS = 1.
1. CLKout12_13_DDLY = 9.
2. Perform SYNC event.
3. CLKout12_13_HS = 0.
Adjust clock output one step
backward.
CLKout12_13_HS = 0.
1. CLKout12_13_HS = 1.
2. CLKout12_13_DDLY = 5.
3. Perform SYNC event.
Adjust clock output one step
backward.
CLKout12_13_HS = 1.
1. CLKout12_13_HS = 0.
To fulfill the qualifying clock output half step requirement in
Table 7 when dynamically adjusting digital delay, the
CLKout12_13_HS bit must be set if CLKout12 or CLKout13
has an odd divide. So before any dynamic digital delay adjustment, CLKout12_13_HS must be set because the clock
divide value is odd. To achieve the final required digital delay
adjustment, the CLKout12_13_HS bit may cleared after
SYNC.
If a SYNC is to be generated this can be done by toggling the
SYNC pin or by toggling the SYNC_POL_INV bit. Because of
the internal one shot pulse, no strict timing of the SYNC pin
or SYNC_POL_INV bit is required. After the SYNC event, the
clock output will be at the specified phase. See Figure 6 for a
detailed view of the timing diagram. The timing diagram critical points are:
• Time A) SYNC assertion event is registered.
The application requires the 491.52 MHz clock to be stepped
in 90 degree steps (~508.6 ps), which is the minimum step
resolution allowable by the clock distribution path. That is 1 /
983.04 MHz / 2 = ~169.5 ps. During the stepping of the 491.52
MHz clocks the 983.04 MHz clock must not be interrupted.
Step 1: The device is programmed from register R0 to R5 with
values that result in the device operating as desired, see the
system requirements above. The phase of all the output
clocks are aligned because all the digital delay and half step
values were the same when the SYNC was generated by
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LMK01801 Dual Clock Distribution
programming register R5. The timing of this is as shown in
Figure 4.
Step 2: Now the registers will be programmed to prepare for
changing digital delay (or phase) dynamically.
outputs to turn off and then back on with a fixed delay with
respect to the falling edge of the qualification clock. This allows for dynamic adjustments of digital delay with respect to
an output clock.
The qualified SYNC timing is shown in Figure 6 for relative
dynamic digital delay.
Dynamic Digital Delay Conditions
To perform a dynamic digital delay adjustment, the analog
delay must be bypassed by setting CLKout12_ADLY_SEL to
0. If the analog delay is not bypassed the output synchronization may be inaccurate due to unknown analog delay
settings.
When adjusting digital delay dynamically, the falling edge of
the qualifying clock must coincide with the falling edge of the
clock distribution path. For this requirement to be met, program the CLKout12_13_HS value of the qualifying clock
group according to Table 7.
LMK01801 Dual Clock Distribution
•
•
•
•
•
•
•
•
•
Time B) First qualifying falling clock output edge.
Time C) Second qualifying falling clock output edge.
Time D) Internal one shot pulse begins. 5.5 cycles later
CLKout12 outputs will be forced low while 8.5 cycles later
CLKout8 outputs will be forced low.
Time E) Internal one shot pulse ends. 6 cycles + digital
delay cycles later CLKout12 or CLKout13 outputs rise. 10
cycles later CLKout8 to CLKout11 outputs rise.
Time F) CLKout12 to CLKout13 outputs are forced low.
Time G) Beginning of digital delay cycles.
Time H) CLKout8 to CLKout11 outputs are forced low.
Time I) CLKout8 to CLKout11 outputs rise now.
Time j) For CLKout12_13_DDLY = 5; the CLKout12 and
CLKout13 outputs rise now.
30148755
FIGURE 6. Relative Dynamic Digital Delay Programming Example, 2nd adjust. (SYNC1_QUAL = 1, Qualify with clock
output)
Starting condition is after half step is removed (CLKout12_13_HS = 0).
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22
R0 with the reset bit (b4) set to 1 to ensure the device is in a
default state. Then R0 is programmed again, the reset bit is
be cleared to 0 during the re-programming of R0.
LMK01801 devices are programmed using 32-bit registers.
Each register consists of a 4-bit address field and 23-bit data
field. The address field is formed by bits 0 through 3 (LSBs)
and the data field is formed by bits 4 through 31 (MSBs). The
contents of each register is clocked in MSB first (bit 31), and
the LSB (bit 0) last. During programming, the LE signal should
be held LOW. The serial data is clocked in on the rising edge
of the CLK signal. After the LSB (bit 0) is clocked in the LE
signal should be toggled LOW-to-HIGH-to-LOW to latch the
contents into the register selected in the address field. It is
recommended to program registers in numeric order, for example R0 to R5 and R15 to achieve proper device operation.
Figure 1 illustrates the serial data timing sequence.
16.1.1 Overview
• R0 (Init):
— Program R0 with RESET = 1. This ensures that the
device is configured with default settings. When
RESET =1, all other R0 bits are ignored.
• R0: Powerdown Controls and CLKin Dividers
— Program R0 with RESET = 0
• R1 and R2: Clock output types
• R3: SYNC Features and Analog Delay for CLKout12 and
CLKout13
• R4: Dynamic Digital Delay for CLKout12 and CLKout13
• R5: CLKout Dividers and Analog Delay Select
• R15: uWireLock
16.1 RECOMMENDED PROGRAMMING SEQUENCE
Registers are programmed in numeric order with R0 being the
first and R15 being the last register programmed. The recommended programming sequence involves programming
16.2 REGISTER MAP
Table 9 provides the register map for device programming:
23
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LMK01801 Dual Clock Distribution
16.0 General Programming
Information
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24
0
R15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLKout13_ADLY_SEL
0
0
CLKout12_13_DIV
0
0
0
0
0
1
1
0
0
0
0
0
1
CLKout0_3
_DIV
9
CLKout12_13_PD
10
CLKin0_BUF_TYPE
CLKin1_BUF_TYPE
0
1
0
1
1
CLKout4_7
_DIV
CLKout12_13_DDLY
CLKout8_11
_DIV
0
CLKout8_TYPE
1
1
CLKout12_13_ADLY
CLKout9_TYPE
CLKout0_
TYPE
8
CLKout8_11_PD
CLKout1_
TYPE
0
0
7
CLKout4_7_PD
1
1
1
0
0
1
1
0
0
Address [3:0]
6
CLKout0_3_PD
11
2
3
4
5
POWERDOWN
CLKout2_
TYPE
1
12
CLKout10_TYPE
CLKout3_
TYPE
1
13
SYNC0_POL_INV
0
0
1
14
CLKout12_ADLY_SEL
0
SYNC1_AUTO
0
SYNC0_AUTO
0
SYNC1_FAST
0
1
CLKout11_TYPE
0
15
CLKin0_DIV
16
CLKout12_TYPE
NO_SYNC_CLKout8_11
0
0
0
17
Data [31:4]
18
SYNC1_QUAL
0
0
1
19
SYNC0_FAST
NO_SYNC_CLKout4_7
0
0
0
CLKout13_TYPE
20
CLKin1_DIV
21
CLKout4_TYPE
22
CLKout5_TYPE
23
NO_SYNC_CLKout12_13
NO_SYNC_CLKout0_3
R5
0
0
0
0
24
SYNC1_POL_INV
0
0
R3
0
0
25
CLKin1_MUX
0
0
26
CLKin0_MUX
CLKout6_TYPE
1
27
uWireLock
CLKout12_13_HS
R4
0
0
R2
0
CLKout7_TYPE
1
R1
28
0
29
Register
R0
30
31
TABLE 9. Register Map
1
1
0
1
0
1
0
0
LMK01801 Dual Clock Distribution
RESET
The Default Device Register Settings after Power On/Reset Table below illustrates the default register settings programmed in
silicon for the LMK018xx after power on or asserting the reset bit. Capital X and Y represent numeric values.
Default Device Register Settings after Power On/Reset
Default
Value
(decimal)
Default State
RESET
0
Not in reset
POWERDOWN
0
CLKout0_3_PD
0
CLKout4_7_PD
0
CLKout8_11_PD
0
CLKout12_13_PD
0
CLKin0_BUF_TYPE
0
CLKin1_BUF_TYPE
0
CLKin0_DIV
2
Divide by 2
CLKin0_MUX
0
Bypass
CLKin1_DIV
2
Divide by 2
CLKin1_MUX
0
Bypass
CLKout0_TYPE
1
LVDS
CLKout1_TYPE
1
LVDS
CLKout2_TYPE
1
LVDS
CLKout3_TYPE
1
CLKout4_TYPE
CLKout5_TYPE
Field Name
Register
Bit Location
(MSB:LSB)
R0
4
R0
5
Power down the divider and clock outputs
0 through 3
R0
6
Disabled
Power down the divider and clock outputs
4 through 7
R0
7
Disabled
Power down the divider and clock outputs
8 through 11
R0
8
Disabled
Power down the divider and clock outputs
12 through 13
R0
9
Bipolar
Clock in buffer type
R0
10
Bipolar
Clock in buffer type
R0
11
Divider value for CLKin0
R0
14:16 [3]
Enables or bypasses the CLKin0 divider
R0
17:18 [2]
Divider value for CLKin1
R0
19:21 [3]
Enables or bypasses the CLKin1 divider
R0
22:23 [2]
R1
4:6 [3]
Field Description
Performs power on reset for device
Disabled (device
Device power down control
is active)
Disabled
R1
7:9 [3]
R1
10:12 [3]
LVDS
R1
13:15 [3]
1
LVDS
R1
16:19 [4]
1
LVDS
R1
20:23 [4]
CLKout6_TYPE
1
LVDS
R1
24:27 [4]
CLKout7_TYPE
1
LVDS
R1
28:31 [4]
CLKout8_TYPE
1
LVDS
CLKout9_TYPE
1
LVDS
CLKout10_TYPE
1
CLKout11_TYPE
1
CLKout12_TYPE
Individual clock output format. Select from
LVDS/LVPECL.
R2
4:7 [4]
R2
8:11 [4]
LVDS
R2
12:15 [4]
LVDS
R2
16:19 [4]
1
LVDS
R2
20:23 [4]
CLKout13_TYPE
1
LVDS
R2
24:27 [4]
CLKout12_13_ADLY
0
CLKout12_13_HS
0
Individual clock output format. Select
from LVDS/LVPECL/LVCMOS.
No delay
Analog delay setting for CLKout12 &
CLKout13.
R3
4:9 [6]
No Shift
Half shift for digital delay.
R3
10
Allows SYNC operations to be qualified by
a clock output
R3
11:12 [2]
R3
14
Not Qualified
SYNC1_QUAL
0
SYNC0_POL_INV
1
Logic Low
SYNC1_POL_INV
1
Logic Low
R3
15
NO_SYNC_CLKout0_3
0
Will sync
R3
16
NO_SYNC_CLKout4_7
0
Will sync
R3
17
R3
18
R3
19
NO_SYNC_CLKout8_1
1
0
NO_SYNC_CLKout12_
13
0
Will sync
Sets the polarity of the SYNC pin when
input
Disable individual clock groups from being
synchronized.
Will sync
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LMK01801 Dual Clock Distribution
16.3 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET
LMK01801 Dual Clock Distribution
Default
Value
(decimal)
Default State
SYNC0_FAST
0
Disabled
SYNC1_FAST
0
Field Name
Disabled
Enables synchronization circuitry.
Register
Bit Location
(MSB:LSB)
R3
23
R3
24
Automatic
SYNC is started by programming a
Register R5
R3
25
Automatic
SYNC is started by programming a
Register R4 or R5
R3
26
5 clock cycles
Digital Delay setting for CLKout12 &
CLKout13.
R4
4:13 [10]
R5
4:6 [3]
SYNC0_AUTO
1
SYNC1_AUTO
1
CLKout12_13_DDLY
5
CLKout0_3_DIV
1
Divide-by-1
CLKout4_7_DIV
1
Divide-by-1
CLKout8_11_DIV
1
Divide-by-1
CLKout12_ADLY_SEL
0
No Delay
CLKout13_ADLY_SEL
0
No Delay
CLKout12_13_DIV
1
Divide-by-1
uWireLock
0
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Field Description
Writeable
R5
7:9 [3]
R5
10:12 [3]
Enable Digital Delay for CLKout12
R5
13
Enable Digital Delay for CLKout 13
R5
14
Divider for clock output.
R5
17:27 [11]
The values of registers R0 to R5 are
lockable
R15
4
Divider for clock outputs.
26
CLKinX_BUF_TYPE Programming Addresses
16.4.1 RESET
Setting this bit will cause the silicon default values to be set
upon loading of R0 by a high LEuWire pin. When programming register R0 with the RESET bit set, all other programmed values are ignored.
The RESET bit is automatically cleared upon writing any other
register. For instance, when R0 is written to again with default
values.
If the user reprograms the R0, after the initial programming
then set RESET = 0.
State
0
Normal operation
1
Reset (automatically cleared)
0
Normal operation
1
Powerdown
CLKoutX_Y_PD Programming Addresses
Programming Address
CLKout0_3_PD
R0[6]
CLKout4_7_PD
R0[7]
CLKout8_11_PD
R0[8]
CLKout12_13_PD
R0[9]
State
0
Power up clock group
1
Power down clock group
R0[10]
CLKinX Buffer Type
0
Bipolar
1
CMOS
CLKinX_DIV
Programming Address
CLKin0_DIV
R0[16:14]
CLKin1_DIV
R0[21:19]
R0[21:19, 16:14]
Divide Value
0 (0x00)
8
1 (0x01)
2
2 (0x02)
2
3 (0x03)
3
4 (0x04)
4
5 (0x05)
5
6 (0x06)
6
7 (0x07)
7
16.4.3.3 CLKinX_MUX
These bits select whether or not the CLKin divider is bypassed
or enabled.
CLKinX_MUX Programming Address
CLKoutX_Y_PD
R0[6,7,8,9]
R0[11]
CLKinX_DIV
16.4.3 CLKoutX_Y_PD
This bit powers down the clock outputs as specified by CLKoutX to CLKoutY. This includes the divider and output buffers.
CLKoutX_Y_PD
R0[10]
CLKin1_BUF_TYPE
CLKinX_DIV Programming Address
POWERDOWN
State
CLKin0_BUF_TYPE
16.4.3.2 CLKinX_DIV
These set the CLKin divide value, from 2-8.
16.4.2 POWERDOWN
Setting this bit causes the device to enter powerdown mode.
Normal operation is resumed by clearing this bit with MICROWIRE. All other MICROWIRE settings are preserved
during POWERDOWN.
R1[5]
Programming Address
CLKinX_BUF_TYPE
RESET
R0[4]
CLKinX_BUF_TYPE
CLKinX_MUX
Programming Address
CLKin0_MUX
R0[18:17]
CLKin1_MUX
R0[23:22]
CLKinX_MUX
16.4.3.1 CLKinX_BUF_TYPE
There are two input buffer types for CLKin0 and CLKin1: bipolar or CMOS. Bipolar is recommended for differential inputs
such as LVDS and LVPECL. CMOS is recommended for DC
coupled single ended inputs.
When using bipolar, CLKinX and CLKinX* input pins must be
AC coupled when using differential or single ended input.
When using CMOS, CLKinX and CLKinX* input pins may be
AC or DC coupled with a differential input.
When using CMOS in a single ended mode, the used clock
input pin (CLKinX or CLKinX*) may be AC or DC coupled to
R0[23:22, 18:17]
State
0 (0x00)
Bypass
1(0x01)
Divide
16.5 REGISTER R1 AND R2
Registers R1 and R2 set the clock output types.
16.5.1 CLKoutX_TYPE
The clock output types of the LMK01801 are individually programmable. The CLKoutX_TYPE registers set the output
type of an individual clock output to LVDS, LVPECL, LVCMOS, or powers down the output buffer. Note that LVPECL
supports three different amplitude levels and LVCMOS sup-
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LMK01801 Dual Clock Distribution
the signal source. The unused CLKin shouLd be AC coupled
to ground.
The programming address table shows at what register the
specified CLKinX_BUF_TYPE is located.
The CLKinX_BUF_TYPE table shows the programming definition for these registers.
16.4 REGISTER R0
The R0 register controls reset, global power down, the power
down functions for the channel dividers and their corresponding outputs, CLKinX divider value and CLKinX divide select.
The X, Y in CLKoutX_Y_PD denote the actually clock output
which may be from 0 to 13 where X is the first CLKout and Y
is the last CLKout.
LMK01801 Dual Clock Distribution
ports single LVCMOS outputs, inverted, and normal polarity
of each output pin for maximum flexibility.
The programming addresses table shows at what register and
address the specified clock output CLKoutX_TYPE register is
located.
The CLKoutX_TYPE table shows the programming definition
for these registers.
16.6 REGISTER R3
Register R3 sets the analog delay, digital delay half-shift and
SYNC controls.
16.6.1 CLKout12_13_ADLY
This registers controls the analog delay of the clock outputs
12 and 13. Adding analog delay to the output will increase the
noise floor of the output. For this analog delay to be active for
a clock output, it must be selected with ADLY12_SEL or
ADLY13_SEL. If neither clock output selects the analog delay, then the analog delay block is powered down.
In addition to the programmed delay, a fixed 500 ps of delay
will be added by engaging the delay block.
The CLKout12_13_ADLY table shows the programming definition for these registers.
CLKoutX_TYPE Programming Addresses
CLKoutX
Programming Address
CLKout0
R1[4:6]
CLKout1
R1[7:9]
CLKout2
R1[10:12]
CLKout3
R1[13:15]
CLKout4
R1[16:19]
CLKout5
R1[20:23]
R3[4:9]
Definition
CLKout6
R1[24:27]
0 (0x00)
500 ps + No delay
CLKout7
R1[28:31]
1 (0x01)
500 ps + 25 ps
CLKout8
R2[4:7]
2 (0x02)
500 ps + 50 ps
CLKout9
R2[8:11]
3 (0x03)
500 ps + 75 ps
CLKout10
R2[12:15]
4 (0x04)
500 ps + 100 ps
CLKout11
R2[16:19]
5 (0x05)
500 ps + 125 ps
CLKout12
R2[20:23]
6 (0x06)
500 ps + 150 ps
CLKout13
R2[24:27]
7 (0x07)
500 ps + 175 ps
8 (0x08)
500 ps + 200 ps
9 (0x09)
500 ps + 225 ps
10 (0x0A)
500 ps + 250 ps
11 (0x0B)
500 ps + 275 ps
CLKout12_13_ADLY, 6bits
CLKoutX_TYPE, 4 bits
R1[31:28,27:24,23:20,19:16],
R2
[27:24,23:20,19:16,15:12,11:8,7:4]
Definition
0 (0x00)
Powerdown
12 (0x0C)
500 ps + 300 ps
1 (0x01)
LVDS
13 (0x0D)
500 ps + 325 ps
2 (0x02)
LCPECL
14 (0x0E)
500 ps + 350 ps
3 (0x03)
Reserved
15 (0x0F)
500 ps + 375 ps
4 (0x04)
LVPECL (1600
mVpp)
16 (0x10)
500 ps + 400 ps
17 (0x11)
500 ps + 425 ps
5 (0x05)
LVPECL (2000
mVpp)
18 (0x12)
500 ps + 450 ps
19 (0x13)
500 ps + 475 ps
LVCMOS (Norm/
Inv)
20 (0x14)
500 ps + 500 ps
7 (0x07)
LVCMOS (Inv/
Norm)
21 (0x15)
500 ps + 525 ps
22 (0x16)
500 ps + 550 ps
8 (0x08)
LVCMOS (Norm/
Norm)
23 (0x17)
500 ps + 575 ps
9 (0x09)
LVCMOS (Inv/Inv)
10 (0x0A)
LVCMOS (Off/
Norm)
6 (0x06)
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11 (0x0A)
LVCMOS (Off/Inv)
12 (0x0C)
LVCMOS (Norm/
Off)
13 (0x0D)
LVCMOS (Inv/Off)
14 (0x0E)
LVCMOS (Off/Off)
16.6.2 CLKout12_13_HS, Digital Delay Half Shift
This bit subtracts a half clock cycle of the clock distribution
path period to the digital delay of CLKout12 and CLKout13.
CLKout12_13_HS is used together with CLKout12_13_DDLY
to set the digital delay value.
The state of this bit does not affect the power mode of the
clock output group.
When changing CLKout12_13_HS, the digital delay immediately takes effect without a SYNC event.
28
State
NO_SYNC_CLKoutX_Y
Programming Address
0
Normal
CLKout0 toCLKout3
R3[16]
1
Subtract half of a clock
distribution path period from
the total digital delay
CLKout4 to CLKout7
R3[17]
CLKout8 to CLKout11
R3[18]
CLKout12 to CLKout13
R3[19]
16.6.3 SYNC1_QUAL
When SYNC1_QUAL is set clock outputs on Bank B will be
synchronized.
CLKout12 will be used as the SYNC qualification clock.
Only CLKout12 and CLKout13 support dynamic digital delay.
However, this permits the relative phase relationship between
CLKout 12 and CLKout13 to be dynamically adjusted with respect
to
all
other
clock
outputs.
When
NO_SYNC_CLKoutX_Y = 1, the corresponding clock outputs
will not be interrupted during the SYNC event.
Qualifying the SYNC means that the pulse which turns the
clock outputs off and on will have a fixed time relationship with
the phase of the other clock outputs.
See Section 14.9 CLOCK OUTPUT SYNCHRONIZATION for
more information.
NO_SYNC_CLKoutX_Y
R3[19, 18, 17, 16]
Definition
0
CLKoutX_Y will synchronize
1
CLKoutX_Y will not synchronize
16.6.6 SYNCX_FAST
SYNC1_FAST must be set to 1 when using SYNC1_QUAL
16.6.7 SYNCX_AUTO
When set, causes a SYNC event to occur when programming
R4 to adjust digital delay values (this will cause a SYNC event
for Bank B only) or R5 when adjusting divide values (this will
cause a SYNC event for both Bank A and B).
The SYNC event will coincide with the LE uWire pin falling
edge.
SYNC1_QUAL
R3[11]
Mode
0 (0x00)
No Qualification
1 (0x01)
Reserved
2 (0x10)
Reserved
3 (0x11)
Qualification Enabled
SYNCX_AUTO
R3[26, 25]
Polarity
SYNC is active high
1
SYNC is active low
Manual SYNC
1
SYNC internally generated
16.7.1 CLKout12_13_DDLY, Clock Channel Digital Delay
CLKout12_13_DDLY and CLKout12_13_HS sets the digital
delay
used
for
CLKout12
and
CLKout13.
CLKout12_13_DDLY only takes effect during a SYNC event
and if the NO_SYNC_CLKout12_13 bit is cleared for this
clock group.
Programming CLKout12_13_DDLY can require special attention. See section Section 15.6.1 Dynamically Programming Digital Delay for more details.
Using a CLKout12_13_DDLY value of 13 or greater will cause
the clock outputs to operate in extended mode regardless of
the clock group's divide value or the half step value.
One clock cycle is equal to the period of the clock distribution
path. The period of the clock distribution path is equal to clock
divider value divided by the CLKin1 frequency.
tclock distribution path = CLKout divide value / fCLKin
SYNCX_POL_INV
0
0
16.7 REGISTER R4
16.6.4 SYNCX_POL_INV
Sets the polarity of a SYNCX input pin. When SYNC is asserted the clock outputs will transition to a low state.
A pull-up on the SYNCX pin results in normal operation when
the SYNCX_POL_INV = 1 and the SYNCX input is a no connect.
See Section 15.6 CLOCK OUTPUT SYNCHRONIZATION
(SYNC) for more information on SYNC. A SYNC event can
be generated by toggling this bit through the MICROWIRE
interface.
R3[14, 15]
Mode
16.6.5 NO_SYNC_CLKoutX_Y
The NO_SYNC_CLKoutX_Y bits prevent individual clock
groups from becoming synchronized during a SYNC event. A
reason to prevent individual clock groups from becoming synchronized is that during synchronization, the clock output is
in a fixed low state or can have a glitch pulse.
By disabling SYNC on a clock group, it will continue to operate
normally during a SYNC event.
Digital delay requires a SYNC operation to take effect. If
NO_SYNC_CLKout12_13 is set before a SYNC event, the
digital delay value will be unused.
Setting the NO_SYNC_CLKoutX_Y bit has no effect on
clocks already synchronized together.
CLKout12_13_DDLY, 10 bits
R4[13:4]
Delay
(Divide >1)
0 (0x00)
5 clock cycles 6 clock cycles
1 (0x01)
5 clock cycles 6 clock cycles
2 (0x02)
5 clock cycles 6 clock cycles
3 (0x03)
5 clock cycles 6 clock cycles
4 (0x04)
5 clock cycles 6 clock cycles
5 (0x05)
5 clock cycles 6 clock cycles
6 (0x06)
6 clock cycles 7 clock cycles
7 (0x07)
7 clock cycles 8 clock cycles
...
12 (0x0C)
29
Delay
(Divide = 1)
...
Power
Mode
Normal
Mode
...
12 clock cycles 13 clock cycles
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LMK01801 Dual Clock Distribution
NO_SYNC_CLKoutX_Y Programming Addresses
CLKout12_13_HS
R3[10]
LMK01801 Dual Clock Distribution
R4[13:4]
Delay
(Divide = 1)
13 (0x0D)
Delay
(Divide >1)
Power
Mode
R5[12:10, 9:7, 6:4]
Divide Value
2 (0x02)
2
3 (0x03)
3
4 (0x04)
4
5 (0x05)
5
6 (0x06)
6
7 (0x07)
7
13 clock cycles 14 clock cycles
...
...
...
520 (0x208)
520 clock
cycles
521 clock
cycles
521 (0x209)
521 clock
cycles
522 clock
cycles
522 (0x20A)
522 clock
cycles
523 clock
cycles
Extended
Mode
CLKout12_13_DIV, 11 bits
16.8 REGISTER R5
Register 5 sets the clock output dividers and analog delay.
16.8.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL
[14], Select Analog Delay
These bits individually select the analog delay block for use
with CLKout12 or CLKout13. It is not required for both outputs
of a clock output group to use analog delay, but if both outputs
do select the analog delay block, then the analog delay will
be the same for each output. When neither clock output uses
analog delay, the analog delay block is powered down.
R5[14]
State
0
0
Analog delay powered down
0
1
Analog delay on CLKout13
1
0
Analog delay on CLKout12
1
1
Analog delay on both
CLKouts
CLKout0_3_DIV
R5[6:4]
CLKout4_7_DIV
R5[9:7]
CLKout8_11_DIV
R5[12:10]
CLKout12_13_DIV
R5[27:17]
Invalid
1 (0x01)
1
2 (0x02)
2(Note 20)
3 (0x03)
3
4 (0x04)
4 (Note 20)
5 (0x05)
5 (Note 20)
6
...
...
24 (0x18)
24
25 (0x19)
25
26 (0x1A)
26
27 (0x1B)
27
...
...
1044 (0x414)
1044
1045 (0x415)
1045
16.9.1 uWireLock
Setting uWireLock will prevent any changes to uWire registers R0 to R5. Only by clearing uWireLock bit in R15 can the
MICROWIRE registers be unlocked and written to once more.
uWireLock
CLKoutX_Y_Div, 2 bits
www.ti.com
Divide Value
0 (0x00)
8
1 (0x01)
1
Extended Mode
16.9 REGISTER 15
R15 [4]
R5[12:10, 9:7, 6:4]
Normal Mode
Note 20: After programming CLKout12_13_DIV a SYNC event must occur
on the channels using this divide value (CLKout 12 and CLKout13), A SYNC
event may be generated by changing the SYNC1_POL_INV bit or through
the SYNC1 pin. Ensure that CLKin1 is stable before this SYNC event occurs.
CLKoutX_Y_DIV Programming Addresses
Programming Address
0 (0x00)
Power Mode
Using a divide value of 26 or greater will cause the clock group
to operate in extended mode regardless of the clock group's
digital delay value.
16.8.2 CLKoutX_Y_DIV. Clock Output Divide
CLKoutX_Y_DIV sets the divide value for the clock outputs X
through Y. The divide may be even or odd. Both even and odd
divides output a 50% duty cycle clock.
Programming CLKoutX_Y_DIV is as follows:
CLKoutX_Y_DIV
Divide Value
6 (0x06)
CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14]
R5[13]
R5[27:17]
30
State
0
Registers Unlocked
1
Registers locked, Write-protected
17.1 POWER SUPPLY
17.1.1 Current Consumption
(Note 22), (Note 23)
From Table 10 the current consumption can be calculated for
any configuration.
For example, the current for the entire device with 1 LVDS
(CLKout0) and 1 LVPECL 1600 mVpp /w 240 Ω emitter resistors (CLKout1) output active with a clock output divide = 1,
and no other features enabled can be calculated by adding
the following blocks:
• Core Current
• Clock Buffer
• One LVDS Output Buffer Current
• Bank A
• Output Divider Buffer Current
• LVPECL 1600 mVpp buffer /w 240 Ω emitter resistors
Since there will be one LVPECL output drawing emitter current, this means some of the power from the current draw of
31
www.ti.com
LMK01801 Dual Clock Distribution
the device is dissipated in the external emitter resistors which
doesn't add to the power dissipation budget for the device but
is important for LDO ICC calculations.
For total current consumption of the device add up the significant functional blocks. In this example 92 mA =
• 1 mA (core current)
• 22 mA (Bank A current)
• 15 mA (Output Buffer current)
• 21 mA (Output Divider current)
• 9 mA (LVDS output current)
• 24 mA (LVPECL 1600 mVpp buffer /w 240 Ω emitter
resistors)
Once the total current consumption has been calculated,
power dissipated by the device can be calculated. The power
dissipation of the device is equel to the total current entering
the device multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected to
the LVPECL outputs, this power will be 0 watts. Continuing
the output with 240 Ω emitter resistors. Total IC power = 275.1
mW = 3.3 V * 95 mA -28.5 mW.
17.0 Application Information
Block
Typical
ICC (mA)
Condition
Power
Power
dissipated
dissipated
externally
in device
(mW)
(mW)
(Note 21)
Core
Core
Bank
Bank A
All outputs and dividers off
At least on output enabled
1
22
3.3
72.6
-
Bank B
At least on output enabled
25
82.5
-
CLKout0 to CLKout3
Buffers
CLKout4 to CLKout7
CLKout8 to CLKout11
-
Output
Divider
Input
Divider
Analog
Delay
CLKout0 to CLKout11
CLKout12 and CLKout13
15
49.5
Divide = 1
21
69.3
-
-
Divide = 2 to 8
24.2
79.8
-
Divide = 1 to 25 and DDLY = 1 to 12
15
49.5
-
Divide = 26 to 1045 or DDLY > 13
19.1
63.0
-
9
29.7
CLKout12_13_ADLY = 0 to 3
3.4
11.2
-
CLKout12_13_ADLY = 4 to 7
3.8
12.5
-
Bank A
Divide = 2 to 8
Bank B
Divide = 2 to 8
Analog Delay Value
-
On when any on output in the group is
enabled
CLKout12 to CLKout13
-
CLKout12_13_ADLY = 8 to 11
4.2
13.9
-
CLKout12_13_ADLY = 12 to 15
4.7
15.5
-
CLKout12_13_ADLY = 16 to 23
5.2
17.2
-
2.8
9.2
-
CLkout0 to CLKout11; 100 Ω differential termination
9
29.7
-
CLkout12 to CLKout13; 100 Ω differential termination
When only one, CLKout12 or CLKout13, have Analog Delay Selected.
Clock Output Buffers
LVPECL
LVDS
14
46.2
-
CLkout0 to CLKout11; LVPECL 1600
mVpp,
AC coupled using 240 Ω emitter resistors
24
79.2
28.5
CLkout12 to CLKout13; LVPECL 1600
mVpp,
AC coupled using 240 Ω emitter resistors
29.5
97.3
28.5
10 MHz
18.6
61.4
-
50 MHz
23.1
76.2
-
150 MHz
31.7
104.6
-
10 MHz
24.7
81.51
-
50 MHz
30.3
100
-
150 MHz
42.0
138.6
-
10 MHz
9.7
32
-
50 MHz
10.8
35.6
-
150 MHz
13.5
44.5
-
10 MHz
15
49.5
-
50 MHz
17.5
57.7
-
150 MHz
22.8
75.2
-
LVCMOS Pair, CLKout4 to CLKout11,
(CLKoutX_TYPE = 6 - 10), CL = 5 pF
LVCMOS
LMK01801 Dual Clock Distribution
TABLE 10. Typical Current Consumption for Selected Functional Blocks (TA = 25 °C, VCC = 3.3 V)
LVCMOS Pair, CLKout12 and
CLKout13,
(CLKoutX_TYPE = 6 - 10), CL = 5 pF
LVCMOS Single, CLKout4 to CLKout11,
(CLKoutX_TYPE=11 - 13), CL = 5 pF
LVCMOS Single, CLKout12 and
CLKout13,
(CLKoutX_TYPE= 11 - 13), CL = 5 pF
Note 21: Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level of one LVPECL
clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 * Vem2/Rem
Note 22: Assuming θJA = 25.8 °C/W, the total power dissipated on chip must be less than (125 °C - 85 °C) / 25.8 °C/W = 1.5 W to guarantee a junction temperature
less than 145 °C
Note 23: Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.20
www.ti.com
32
17.2.1 Vcc Pins and Decoupling
All Vcc pins must always be connected.
Integrated capacitance on the IC makes high frequency decoupling capacitors unnecessary. Ferrite beads should be
used on CLKout Vcc pins to minimize crosstalk through power
supply. When several clocks share the same frequency, a
single ferrite bead can be shared with the common frequency
CLKout Vcc's for power supply isolation.
17.2.2 Unused clock outputs
Leave unused clock outputs floating and powered down.
17.2.3 Unused clock inputs
Unused clock inputs can be left floating.
17.2.4 Bias
Proper bypassing of the Bias pin with a 1 µF capacitor connected to Vcc4_Bias (Pin 25) is important for low noise performance.
17.2.5 In MICROWIRE Mode
SYNC0 and SYNC1 have an internal pullup and may be left
as a no-connect if external SYNC is not required. MIRCROWIRE SYNC may still be used in this condition.
17.3 THERMAL MANAGEMENT
Power consumption of the LMK01801 can be high enough to
require attention to thermal management. For reliability and
performance reasons the die temperature should be limited
to a maximum of 125 °C. That is, as an estimate, TA (ambient
temperature) plus device power consumption times θJA
should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to a printed circuit board. To maximize the removal
of heat from the package a thermal land pattern including
multiple vias to a ground plane must be incorporated on the
PCB within the footprint of the package. The exposed pad
30148773
FIGURE 7. Recommended Land and Via Pattern
33
www.ti.com
LMK01801 Dual Clock Distribution
must be soldered down to ensure adequate heat conduction
out of the package.
A recommended land and via pattern is shown in Figure 7.
More information on soldering LLP packages and gerber footprints can be obtained: http://www.national.com/analog/packaging.
A recommended footprint including recommended solder
mask and solder paste layers can be found at: http://
www.national.com/analog/packaging/llp/gerber.html for the
SQA48A package.
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 7 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
17.2 PIN CONNECTION RECOMMENDATIONS
LMK01801 Dual Clock Distribution
17.4 DRIVING CLKin INPUTS
17.4.1 Driving CLKin Pins with a Differential Source
Both CLKin ports can be driven by differential signals. It is
recommended that the input mode be set to bipolar
(CLKinX_BUF_TYPE = 0) when using differential reference
clocks. The LMK01801 family internally biases the input pins
so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either
LVDS or LVPECL are shown in Figure 8 and Figure 9.
30148722
FIGURE 11. DC Coupled LVCMOS/LVTTL
Reference Clock
If the CLKin pins are being driven with a single-ended LVCMOS/ LVTTL source, either DC coupling or AC coupling may
be used. If DC coupling is used, see Figure 12, the
CLKinX_BUF_TYPE should be set to MOS buffer mode
(CLKinX_BUF_TYPE = 1) and the voltage swing of the source
must meet the specifications for DC coupled, MOS-mode
clock inputs given in the table of Electrical Characteristics. If
AC coupling is used, the CLKinX_BUF_TYPE should be set
to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The
voltage swing at the input pins must meet the specifications
for AC coupled, bipolar mode clock inputs given in the table
of Electrical Characteristics. In this case, some attenuation of
the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient.
30148788
FIGURE 8. CLKinX/X* Termination for an LVDS
Reference Clock Source
30148787
FIGURE 9. CLKinX/X* Termination for an LVPECL
Reference Clock Source
30148785
FIGURE 12. DC Coupled LVCMOS/LVTTL Reference
Clock
Finally, a reference clock source that produces a differential
sine wave output can drive the CLKin pins using the circuit
shown in Figure 10. Note: the signal level must conform to the
requirements for the CLKin pins listed in the Section 10.0
Electrical Characteristics.
17.5 TERMINATION AND USE OF CLOCK OUTPUT
(DRIVERS)
When terminating clock drivers keep in mind these guidelines
for optimum phase noise and jitter performance:
• Transmission line theory should be followed for good
impedance matching to prevent reflections.
• Clock drivers should be presented with the proper loads.
For example:
— LVDS drivers are current drivers and require a closed
current loop.
— LVPECL drivers are open emitters and require a DC
path to ground.
• Receivers should be presented with a signal biased to
their specified DC bias level (common mode voltage) for
proper operation. Some receivers have self-biasing inputs
that automatically bias to the proper voltage level. In this
case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver
with an LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or
input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its
optimum DC voltage (common mode voltage).
For example, when driving the OSCin/OSCin* input of the
LMK04800 family, OSCin/OSCin* should be AC coupled because OSCin/ OSCin* biases the signal to the proper DC
level. This is only slightly different from the AC coupled cases
described in Section 17.4.2 Driving CLKin Pins with a SingleEnded Source because the DC blocking capacitors are
30148724
FIGURE 10. CLKinX/X* Single-ended Termination
17.4.2 Driving CLKin Pins with a Single-Ended Source
The CLKin pins of the LMK01801 family can be driven using
a single-ended reference clock source, for example, either a
sine wave source or an LVCMOS/LVTTL source. Either AC
coupling or DC coupling may be used. In the case of the sine
wave source that is expecting a 50 Ω load, it is recommended
that AC coupling be used as shown in Figure 11 the circuit
below with a 50 Ω termination.
Note: The signal level must conform to the requirements for the CLKin pins
listed
in
the
Section
10.0
Electrical
Characteristics.
CLKinX_BUF_TYPE is recommended to be set to bipolar mode
(CLKinX_BUF_TYPE = 0).
www.ti.com
34
17.5.1 Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with
100 Ω as close as possible to the LVDS receiver as shown in
Figure 13.
30148719
FIGURE 16. Differential LVDS Operation, AC Coupling,
External Biasing at the Receiver
Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in is modified by replacing
the 50 Ω terminations to Vbias with a single 100 Ω resistor
across the input pins of the receiver, as shown in Figure 17.
When using AC coupling with LVDS outputs, there may be a
startup delay observed in the clock output due to capacitor
charging. The previous figures employ a 0.1 μF capacitor.
This value may need to be adjusted to meet the startup requirements for a particular application.
30148720
FIGURE 13. Differential LVDS Operation, DC Coupling,
No Biasing of the Receiver
For DC coupled operation of an LVPECL driver, terminate
with 50 Ω to VCC - 2 V as shown in Figure 14. Alternatively
terminate with a Thevenin equivalent circuit (120 Ω resistor
connected to VCC and an 82 Ω resistor connected to ground
with the driver connected to the junction of the 120 Ω and 82
Ω resistors) as shown in Figure 15 for VCC = 3.3 V.
30148782
FIGURE 17. LVDS Termination for a Self-Biased Receiver
LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω to 240 Ω emitter resistors
close to the LVPECL driver to provide a DC path to ground as
shown in Figure 18. For proper receiver operation, the signal
should be biased to the DC bias level (common mode voltage)
specified by the receiver. The typical DC bias voltage for
LVPECL receivers is 2 V.
A typical application is shown in Figure 18, where Rem=120
Ω to 240 Ω. Refer to the reciever input recommendations to
determine if the proper value of CA's, if needed.
30148718
FIGURE 14. Differential LVPECL Operation, DC Coupling
30148721
30148717
FIGURE 15. Differential LVPECL Operation, DC Coupling,
Thevenin Equivalent
FIGURE 18. Differential LVPECL Operation, AC Coupling,
External Biasing at the Receiver,
Rem=120 Ω to 240 Ω
17.5.2 Termination for AC Coupled Differential Operation
AC coupling allows for shifting the DC bias level (common
mode voltage) when driving different receiver standards.
Since AC coupling prevents the driver from providing a DC
bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level.
When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking
capacitors, however the proper DC bias point needs to be
established at the receiver. One way to do this is with the termination circuitry in Figure 16.
17.5.3 Termination for Single-Ended Operation
A balun can be used with either LVDS or LVPECL drivers to
convert the balanced, differential signal into an unbalanced,
single-ended signal.
It is possible to use an LVPECL driver as one or two separate
800 mVpp signals. When using only one LVPECL driver of a
CLKoutX/CLKoutX* pair, be sure to properly terminated the
unused driver. When DC coupling one of the LMK04800 family clock LVPECL drivers, the termination should be 50 Ω to
35
www.ti.com
LMK01801 Dual Clock Distribution
placed between the termination and the OSCin/OSCin* pins,
but the concept remains the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common
mode voltage), not the driver.
LMK01801 Dual Clock Distribution
50 Ω termination with the proper DC bias level for the receiver.
The typical DC bias voltage for LVPECL receivers is 2 V (See
Section 17.5.2 Termination for AC Coupled Differential Operation). If the companion driver is not used it should be
terminated with either a proper AC or DC termination. This
latter example of AC coupling a single-ended LVPECL signal
can be used to measure single-ended LVPECL performance
using a spectrum analyzer or phase noise analyzer. When
using most RF test equipment no DC bias point (0 VDC) is
required for safe and proper operation. The internal 50 Ω termination of the test equipment correctly terminates the
LVPECL driver being measured as shown in Figure 21.
VCC - 2 V as shown in Figure 19. The Thevenin equivalent
circuit is also a valid termination as shown in Figure 20 for Vcc
= 3.3 V.
30148715
FIGURE 19. Single-Ended LVPECL Operation,
DC Coupling
30148714
FIGURE 21. Single-Ended LVPECL Operation, AC
Coupling
Rem=120 Ω to 240 Ω
30148716
FIGURE 20. Single-Ended LVPECL Operation, DC
Coupling, Thevenin Equivalent
When AC coupling an LVPECL driver use a 120 Ω to 240 Ω
emitter resistor to provide a DC path to ground and ensure a
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36
LMK01801 Dual Clock Distribution
18.0 Physical Dimensions inches (millimeters) unless otherwise noted
19.0 Ordering Information
Order Number
Package Marking
LMK01801BISQ
LMK01801BISQE
Packaging
1000 units
K01801BI
LMK01801BISQX
250 units
2500 units
37
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LMK01801 Dual Clock Distribution
Notes
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