19-2970; Rev 3; 1/09 KIT ATION EVALU E L B AVAILA WCDMA Quasi-Direct Modulator with VGA and PA Driver The MAX2395 fully monolithic quasi-direct modulator IC is designed for use in WCDMA/UMTS transmitters. The quasi-direct modulation architecture reduces system cost, component count, and board space compared to transmitters using an IF SAW filter with IF VCO and IF synthesizer blocks. The MAX2395 includes I/Q baseband filters, an IF I/Q modulator with VGA, a fully monolithic VCO with PLL, an upconverter mixer, an RF VGA, and a power amplifier (PA) driver. The use of the quasi-direct modulator scheme ensures 5% (typ) EVM and a 30dB (min) carrier suppression. The RF VGA and IF VGA provide a nominal 90dB of output power control. No external local oscillators are required, enabling efficient implementation of variable duplex offset systems. Features o 5% EVM for POUT = +6dBm o 1920MHz to 1980MHz Operation o +2.7V to +3.3V Single-Supply Operation o +6dBm Output Power at 72mA o 81dB Minimum Automatic Gain-Control (AGC) Range o Automatic ICC Throttle Back for Optimal Power Consumption o No IF SAW Filter Necessary o On-Chip RF PLL, with Fully Monolithic VCO o Ultra-Low External Component Count The PLL is programmed by loading data on the SPI™/ MICROWIRE™-compatible 3-wire serial bus. The IC operates from a single +2.7V to +3.3V supply. The devices are available in space-saving 28-pin QFN and thin QFN exposed-pad packages (5mm x 5mm). Applications Ordering Information PART TEMP RANGE PIN-PACKAGE MAX2395EGI -40°C to +85°C 28 QFN-EP* WCDMA Phones MAX2395ETI -40°C to +85°C 28 TQFN-EP* UMTS/EDGE Phones MAX2395ETI+ -40°C to +85°C 28 TQFN-EP* W-TDD Phones *EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. N.C. 1 POUT 2 VCC_PA SDATA CS N.C. N.C. BVP VTUNE + SCLK Pin Configuration/ Functional Diagram 28 27 26 25 24 23 22 SERIAL BUS RF INTEGER-N PLL 3 BIAS_SET 4 VGC 5 LO GEN 21 GND_VCO 20 VCC_VCO 19 RFCP 18 VCC_CP 17 VCC_PLL SPI is a trademark of Motorola, Inc. 0° MAX2395 90° VCC_BB 7 15 LD 10 11 12 13 14 N.C. 9 Q- IDLE 8 Q+ REF I- 16 I+ 6 SHDN VCC_IF MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2395 General Description MAX2395 WCDMA Quasi-Direct Modulator with VGA and PA Driver ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +3.6V All Other Pins to GND..................................-0.3V to VCC_ + 0.3V I_, Q_, REF to GND..............................................................1VP-P Digital Input Current .........................................................±10mA Continuous Power Dissipation (TA = +70°C) 28-Pin QFN (derate 20.8mW/°C above +70°C) .........1667mW 28-Pin TQFN (derate 21.3mW/°C above +70°C) .......1702mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.3V, RBIAS = 12kΩ, TA = -40°C to +85°C. Typical values are at VCC = +2.85V and TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER CONDITIONS Supply Voltage Range Operating Supply Current MIN TYP MAX UNITS 2.7 V 2.85 3.3 VVGC = 0.35V 46 60 POUT = 0dBm 67 82 POUT = +6dBm Idle Current IDLE = VIL Shutdown Current SHDN = 0 72 90 IDLE_PRG = 0 16 21 IDLE_PRG = 1 19 27 VGC Input Current VGC Input Current During Shutdown 0.5 -10 SHDN = VIL Gain-Control Voltage Range 0.35 Lock Indicator High—Leakage Current PLL locked, VLD = VCC Lock Indicator Low—Sink Voltage PLL unlocked, sinking 100µA SHDN Input Logic-High, VDH SHDN Input Logic-Low 10 mA µA +10 µA 1 µA 2.20 V 4 µA 0.4 V 1.5 VCC V 0 0.5 V SHDN Input Resistance Resistance to ground Digital Input Logic-High, VIH All digital input pins including IDLE, SDATA, SCLK, and CS (Note 3) 0.7 x VDH VCC V Digital Input Logic-Low, VIL All digital input pins including IDLE, SDATA, SCLK, and CS (Note 3) 0 0.3 x VDH V Digital Control Pin Input Current IDLE, SDATA, SCLK, and CS 50 k -10 +10 µA I/Q Input Leakage Current -10 +10 µA I/Q DC Common-Mode Voltage 1.35 1.65 V 2 1.45 _______________________________________________________________________________________ WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395 EV kit, VCC = +2.7V to +3.3V, RBIAS = 12kΩ, VVGC adjusted to obtain maximum rated output power, and TA = -40°C to +85°C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel (12.2kbps), envelope level 1VP-P. Typical values are at VCC = +2.85V and TA = +25°C, unless otherwise noted. See Tables 1 and 3 for register settings.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 1920 1950 1980 MHz CASCADED RF SPECIFICATIONS RF Frequency Range (Notes 4, 6) Maximum Output Power (Note 6) VGC set for maximum output power while meeting ACPR1, ACPR2, out-of-band emissions, and output noise density specifications 6 dBm Out-of-Band Emissions (Note 6) At f = 1575MHz -31 -24 At RF + 2 x IF (image) -13 -8.5 Adjacent Channel Power Ratio, ACPR1 (Notes 5, 6) ∆∆f = ±5MHz/3.84MHz BW POUT > 0dBm and TA > 0°C -48 -45 POUT ≤ 0dBm and TA ≤ 0°C -45 -43 Alternate Channel Power Ratio, ACPR2 (Notes 5, 6) ∆∆f = ±10MHz/3.84MHz BW -60 -57 Output Noise Power Density (Note 6) POUT = +6dBm at 1920MHz, noise measured at 1880MHz -140 -137 POUT = +6dBm at 1980MHz, noise measured at 2110MHz -146 -143 Minimum Output Power VVGC = 0.35V -85 -78 Carrier Suppression EVM (Note 6) dBc dBc dBc/Hz 30 Sideband Suppression dBc dBm dB 32 dB Including BB filter, POUT = +6dBm 5 7.5 Including BB filter, POUT = -44dBm 8.6 14.6 %RMS I/Q MODULATION BASEBAND INPUTS Passband Amplitude Ripple Baseband Selectivity DC to 2MHz (Notes 6, 7) Relative to passband -0.3 +0.4 dB At 8.08MHz 8 35 At 13.44MHz 25 50 4032 9750 65,535 8 19.2 40 MHz 16 MHz dB INTEGER-N RF PLL Main PLL Integer Division Ratios 16-bit register (64/65 dual-modulus prescaler) Reference Frequency Range Input Frequency for Reference Frequency Doubler OPCTRL register bit 7 = 1 Reference-Divider Ratio 9-bit register Charge-Pump Nominal Currents (Sink or Source) Locked, RCP1/RCP0 = 0 1, VCC/2 Locked, RCP1/RCP0 = 1 1, VCC/2 Charge-Pump Leakage Current 13 80 511 1200 1500 1800 2000 2500 3000 20 µA nA _______________________________________________________________________________________ 3 MAX2395 AC ELECTRICAL CHARACTERISTICS MAX2395 WCDMA Quasi-Direct Modulator with VGA and PA Driver AC ELECTRICAL CHARACTERISTICS (continued) MAX2395 EV kit, VCC = +2.7V to +3.3V, RBIAS = 12kΩ, VVGC adjusted to obtain maximum rated output power, and TA = -40°C to +85°C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel (12.2kbps), envelope level 1VP-P. Typical values are at VCC = +2.85V and TA = +25°C, unless otherwise noted. See Tables 1 and 3 for register settings.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS -130 -128 dBc/Hz ON-CHIP VCO Phase Noise At 3MHz offset, measured at the center of the RF band (Note 6) Supply Pushing Supply stepped from +2.7V to +3.3V, with on-chip voltage regulator ±0.15 MHz/V RF VCO Pulling When switching from IDLE mode to active Tx mode ±0.1 MHzP-P 3-WIRE SERIAL BUS INTERFACE Data to Clock Setup, tCS Figure 1 (Note 6) 20 ns Data to Clock Hold Time, tCH Figure 1 (Note 6) 10 ns Clock Pulse-Width High, tCWH Figure 1 (Note 6) 20 ns Clock Pulse-Width Low, tCWL Figure 1 (Note 6) 20 ns Clock to Load Enable/Setup Time, tES Figure 1 (Note 6) 20 ns Clock Frequency (Note 6) 20 MHz Note 1: The following parameters are characterized using the register settings below. Table 1. Characterization Register Settings REGISTER RFR OPCTRL Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 4 SETTINGS ADDRESS FUNCTION 4050 hex (80 dec for ÷R) 0000b Reference-divider register 3B7D hex 0100b Operational control settings Guaranteed at TA = +25°C and TA = +85°C by production test, and guaranteed by design and characterization at TA = -40°C. VDH is the high voltage applied to the shutdown pin. Output power, linearity, noise power, and LO leakage specifications are met over this frequency range. Specifications valid for all output power levels, unless limited by thermal noise at lower output power levels. Guaranteed by design and characterization. Tested at 1MHz and 2MHz in the passband. _______________________________________________________________________________________ WCDMA Quasi-Direct Modulator with VGA and PA Driver POUT ACPR1 vs. VVGC TA = -40°C TA = +25°C 6 TA = +85°C TA = +25°C -20 TA = -40°C -30 -40 -6 -2 2 6 1.6 1.7 2.1 FREQUENCY (GHz) BASEBAND FILTER REPSONSE 90 ICC (mA) TA = -40°C f = 2112.4MHz TA = +85°C 70 60 50 40 TA = +85°C 0 1.6 1.8 2.0 2.2 CARRIER AND SIDEBAND SUPPRESSION vs. POUT 0 TA = +85°C 65 20 SIDEBAND 55 TA = +25°C 50 45 -64 -54 -44 -34 -24 POUT (dBm) -14 -4 6 FROM SHDN 0 -5 -10 FROM 1920MHz TO 1980MHz -20 -25 30 -74 FROM IDLE 5 TA = -40°C 35 0 6 8 10 12 14 16 18 20 FREQUENCY (MHz) -15 40 10 4 10 FREQUENCY (kHz) SLOPE (dB/V) 30 2 FREQUENCY SETTLING TIME VGC SLOPE LINEARITY vs. POUT 60 40 -40 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 VVGC (V) 70 MAX2395 toc07 CARRIER 50 -30 -60 0.4 0.6 VVGC (V) 60 -20 -50 20 1.4 -10 TA = -40°C MAX2395 toc08 1.2 10 TA = +25°C 30 f = 1880MHz 1.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2.2 80 0.8 CARRIER AND SIDEBAND SUPPRESSION (dBc) 2.0 MAX2395 toc06 MAX2395 toc04 OUTPUT POWER NOISE DENSITY (dBm/Hz) -154 1.9 VCC = 2.7V TO 3.3V, INPUT APPLIED 100 -138 -150 -152 1.8 110 TA = +25°C -146 -148 -60 ICC vs. VVGC fRF = 1922.4MHz -140 -142 -144 -50 VVGC (V) OUTPUT NOISE DENSITY vs. VVGC -134 -136 RF LO, -42dB -40 -90 1.5 POUT (dBm) -130 -132 -30 -80 -60 FILTER RESPONSE (dB) -30 -26 -22 -18 -14 -10 RF LO-3IF, RF LO-2IF, -32dB -35dB -20 -70 -50 4 RF IMAGE, 15dB -10 MAX2395 toc03 MAX2395 toc02 TA = +85°C -10 WANTED SIGNAL, 0dB 0 MAX2395 toc05 5 0 10 MAX2395 toc09 8 7 10 POUT (dBm), ACPR (dBc) EVM (%RMS) 9 OUTPUT SPECTRUM vs. FREQUENCY 20 MAX2395 toc01 10 OUTPUT SPECTRUM (dBm) EVM vs. POUT -74 -64 -54 -44 -34 -24 POUT (dBm) -14 -4 6 0 100 200 300 400 500 600 700 800 900 TIME (µs) _______________________________________________________________________________________ 5 MAX2395 Typical Operating Characteristics (VCC = +2.85V, fRF = 1950MHz, MPL = 1, and TA = +25°C, unless otherwise noted.) WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395 Pin Description PIN NAME 1 N.C. 2 POUT 3 VCC_PA 4 BIAS_SET Bias-Setting Pin. The DC voltage at this pin is a bandgap voltage. For nominal bias, connect a 12kΩ resistor to ground. The value of this resistor can be adjusted to alter current consumption, linearity, and noise performance of the RF output. 5 VGC Gain-Control Pin. Analog input pin controls both the IF VGA and RF VGA gain. When not driven, the voltage on this pin is typically +1.5V. An RC filter on this pin must be used to filter out DAC noise or the PDM clock. 6 VCC_IF Supply for IF Section. Bypass to system ground with a capacitor as close to the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). 7 VCC_BB Supply for Baseband Section. Bypass to system ground with a capacitor as close to the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). 8 IDLE 9 6 SHDN FUNCTION Connect to RF GND on PCB Transmitter Output. This is an open-collector output and requires a pullup inductor to the supply voltage. This pullup inductor can be part of the output matching network and can be connected directly to the battery. Supply for the PA Driver. This pin must be bypassed with a capacitor to system ground as close to the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). Idle CMOS Digital Input. Drive LOW to place the device in WCDMA compressed mode (VCO and PLL are ON; all others are OFF). A small RC lowpass filter can be used to minimize the effect of external digital noise. Shutdown CMOS Digital Input. Drive LOW to place the device in shutdown (everything OFF except serial interface and registers, which retain their values). A small RC lowpass filter can be used to minimize the effect of external digital noise. A logic-low on the SHDN pin overrides the serial bus SHDN bit status. 10, 11 I+, I- Differential I-Channel Baseband Inputs to the Baseband Filter 12, 13 Q+, Q- Differential Q-Channel Baseband Inputs to the Baseband Filter 14, 24, 25 N.C. 15 LD Lock CMOS Output. This pin is an open-drain output. Output HIGH indicates the RF PLL is locked. 16 REF Reference Frequency Input. This pin is internally biased to approximately +1.0V and must be ACcoupled to the reference source. This is a high-impedance port and can be externally terminated to the desired impedance. 17 VCC_PLL Supply for PLL. Bypass with a capacitor to GND (see the Typical Operating Circuit). 18 VCC_CP Supply for Synthesizer Charge Pump. Bypass with a capacitor to GND (see the Typical Operating Circuit). 19 RFCP Leave Open RF Charge-Pump Output. Connect the RF PLL’s loop filter between RFCP and system ground. Keep the line from this pin to the tank tune input as short as possible to prevent spurious pickup. Connect the loop filter as close to the tune input as possible. _______________________________________________________________________________________ WCDMA Quasi-Direct Modulator with VGA and PA Driver PIN NAME FUNCTION 20 VCC_VCO Supply for VCO. Bypass to system ground with a capacitor as close to the pin as possible. Do not share ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit). 21 GND_VCO RF VCO Varactor Ground. Connect to the ground at the PLL loop-filter capacitors. Do not connect to the exposed pad. 22 VTUNE 23 BYP Bypass with a Capacitor to GND. The capacitor is used by the on-chip VCO voltage regulator (see the Typical Operating Circuit). 26 CS 3-Wire Serial Bus Enable Input (Figure 1) 27 SDATA 28 SCLK — EP Oscillator-Frequency Tuning Voltage Input 3-Wire Serial Bus Data Input (Figure 1) 3-Wire Serial Bus Clock Input (Figure 1) Exposed Pad. Connect to the ground plane for proper heat dissipation. Detailed Description The MAX2395 quasi-direct modulator accepts differential I/Q baseband inputs with external common-mode bias. A gain-control voltage pin (VGC) controls the gain of the IF and RF VGAs simultaneously to achieve the best current consumption and linearity performance. GmC Filters The internal GmC filters are used to eliminate noise and baseband DAC aliasing signals above 8MHz. The GmC filter can be bypassed (GMC_EN bit, OPCTRL register bit 3), lowering the total current at the expense of no filtering. To speed up the settling time when transitioning from IDLE to transmit mode, the filter can be forced to stay active in IDLE mode using the IDLE_PRG bit (OPCTRL register bit 1). Contact factory if bypass mode is used. I/Q Modulator Differential in-phase (I) and quadrature-phase (Q) input pins are designed to be DC-coupled and biased with the baseband output from a digital-to-analog converter (DAC). The I_ and Q_ inputs need a DC bias, which can range from 1.35V to 1.65V. The current draw is negligible and the differential input capacitance is 4pF. The VCO frequency is divided by 6 to produce the RF I/Q LO signals. IF/RF VGA The part offers approximately 90dB of gain-control range. An external voltage must be applied using a DAC allowing for dynamic gain control. To minimize the noise contribution from the DAC to the RF signal, place an RC filter at this pin (refer to the MAX2395 Evaluation Kit data sheet). The PA driver is included in the RF VGA. Internal VCO and Tank The integrated monolithic VCO and tank is tuned through the VTUNE pin. The RF/IF LO signals are generated from this oscillator. PLL The internal PLL uses a charge-pump output to drive a loop filter. The loop filter is typically a passive 2ndorder lead lag filter with a bandwidth of 10kHz. The loop filter must be optimized for a selected chargepump current, where KVCO = 90MHz/V. The internal architecture requires the RF VCO to run at 1.2x the desired frequency, mandating a 240kHz comparison frequency for an output step size of 200kHz. The LD output indicates whether the PLL is locked. An output high indicates a lock condition. There is an optional frequency doubler at the input of the PLL reference divider. When using a 13MHz reference frequency, either a 40kHz comparison can be used or the internal frequency doubler is enabled to allow a comparison frequency of 80kHz. The optional frequency double can be activated by setting OPCTRL register bit 7 = 1. PA Driver/RF Upconverter The IF signal is upconverted with an image reject RF mixer, and differentially fed into the PA driver. The PA driver converts differential input signals to a singleended output. The driver requires a pullup inductor, which is part of the output matching network. _______________________________________________________________________________________ 7 MAX2395 Pin Description (continued) MAX2395 WCDMA Quasi-Direct Modulator with VGA and PA Driver Register Definition The MAX2395 includes three programmable, 20-bit registers consisting of two divide registers and an operational control register. These registers are programmed from the SPI/ MICROWIRE-compatible serial port. The 4 least significant bits (LSBs) are reserved for the register’s address. The register bits have been assigned to allow sharing of the 3-wire bus with the MAX2390/MAX2391/MAX2392/MAX2401 receiver ICs. The 16 most significant bits (MSBs) are used for register data. Data is shifted in MSB first, followed by the 4-bit address. When CS is low, the clock input is active and data is shifted with the rising edge of the clock. When CS transitions to high, the shift register is latched into the register selected by the contents of the address bits. Power-up defaults for the three registers are shown in Table 2. Initialize the registers according to the characterization table (Table 1). The RFM register sets the main frequency divide ratio for the RF PLL. The RFR register sets the reference frequency divide ratio. The RF VCO frequency is determined by the following: RF VCO frequency = fREFin (RFM/RFR) where fREFin is the external input reference frequency for the MAX2395. The operational control register (OPCTRL) controls the state of the IC. See Table 3 for the function of each bit. The RFR divide register includes test bits B9–B15. These bits are used to troubleshoot the VCO and synthesizer section (see Table 4). These bits are not needed for normal use and should be left as the values at power-up. The device offers several different operation modes for conserving power. Table 5 explains how to implement each mode. Shutdown and Idle Mode™ The part offers a shutdown mode and idle mode for optimal power management. In shutdown mode, all functions are turned off except the serial interface. When the part is shut down using the OPCTRL register, the IC draws a residual current of 60µA (typ). In idle mode, the VCO, PLL, and serial interface remain on to minimize startup time. The GmC filter can be software programmed to power on or off during idle mode (see Table 5). Applications Information External Matching to PA The Tx outputs are internally matched to 50Ω. The open-collector output requires a pullup inductor to VCC. The selection of matching in the MAX2395 Evaluation Kit allows optimization of ACPR. Electromagnetic Compliance Considerations Two major concepts should be employed to produce a low-spur and EMC-compliant transmitter: Minimize circular current-loop area to reduce H-field radiation, and minimize losses. To minimize circular current-loop area, bypass as close to the device as possible and use the distributed capacitance of a ground plane. To minimize losses, make RF traces short. Program only the necessary bits in any register to minimize clock cycles. RC filtering can also be used to slow the clock edges on the 3-wire interface, reducing highfrequency spectral content. RC filtering also provides for transient protection against IEC 802 testing by shunting high frequencies to ground, while the series resistance attenuates the transients for error-free operation. The same applies to the logic-input pins (SHDN, IDLE). High-frequency bypass capacitors are required close to the pins with a dedicated via to ground. The package provides minimal inductance ground by using an exposed pad under the part. Provide at least five lowinductance vias under the pad to ground to minimize ground inductance. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as a slot radiator and reduce its shield effectiveness. Layout Issues The MAX2395 Evaluation Kit can be used as a reference for board layout. Gerber files are available upon request at www.maxim-ic.com. To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC node in the circuit. At the end of each trace is a bypass capacitor with impedance to ground less than 1Ω at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor. Idle Mode is a trademark of Maxim Integrated Products, Inc. 8 _______________________________________________________________________________________ WCDMA Quasi-Direct Modulator with VGA and PA Driver MAX2395 Table 2. Register Power-Up Default States (fREF = 19.2MHz, fRF = 1950MHz) REGISTER DEFAULT ADDRESS RFM 9750 dec 0010b Main-divider ratio register RFR 4050 hex (80 dec for ÷R) 0000b Reference-divider register 197D hex 0100b Operational control settings OPCTRL FUNCTION Table 3. Operation Control Register (OPCTRL) Bit Assignments BIT NAME POWER-UP STATE BIT LOCATION (0 = LSB) FUNCTION SHDN 1 0 Setting this bit to zero shuts down everything except the serial interface and registers, which retain their values. It is overridden by a logic-low on the SHDN pin. IDLE_PRG 0 1 If bit is set to 1, this leaves the GmC filters and the servo loop ON when the IDLE pin goes LOW. If bit is set to zero, the GmC filters shut off when the IDLE pin goes LOW. — 1 2 Leave in power-up state. GmC_EN 1 3 Setting this bit to zero bypasses GmC filters. PLL_EN 1 4 Setting this bit to zero shuts off the RF PLL. VCO_EN 1 5 Setting this bit to zero shuts off the RF VCO. PA_RF_IF_EN 1 6 Setting this bit to zero shuts off the PA driver, RF upconverter, and IF modulator sections. X2_EN 0 7 Setting this bit to 1 enables the X2 multiplier for use in the REF divider section when TCXO frequency is 13MHz. MPL 1 8 Maximum power level setting: 1 = +6dBm; 0 = +3dBm PRD_Bias 0 9 Predriver bias: 0 = -25%; 1 = nominal OUT_Bias 0 10 RCP1, RCP0 11 Output bias: 0 = nominal; 1 = +30% 12, 11 A 2-bit word sets the RF charge-pump current as follows: 0 0 = 1000µA 0 1 = 1500µA 1 0 = 2000µA 1 1 = 2500µA A 2-bit word sets the Ameliorator current as follows: 0 0 = Off 0 1 = Low (nominal) 1 0 = Mid 1 1 = High These bits are used in DC offset trimming mode, where DC_TRM = 1. AML1, AML0 00 14, 13 DC_TRM 0 15 Setting this bit to 1 enables the DC offset trimming mode. _______________________________________________________________________________________ 9 Table 4. Reference-Divider (RFR) Register BIT NAME POWER-UP STATE BIT LOCATION (0 = LSB) RFR8 to RFR0 001010000 8 to 0 Reference-divider register bits 10, 9 0 0 = Normal operation (lock-detect output at LD pin) 0 1 = RFM-DIV output 1 0 = RFR-DIV output 1 1 = Low logic output LD1, LD0 00 FUNCTION RF CP test bits: 0 0 0 = Normal mode 0 0 1 = Source sink ON 0 1 1 = Sink ON 1 0 1 = Source ON 1 1 0 = Source, sink OFF RCPT2, RCPT1, RCPT0 000 13, 12, 11 RESERVED 1 14 Program to 1 for normal operation RESERVED 0 15 Program to 0 for normal operation 1 0 X X 1 1 0 0 SHDN mode All OFF except serial bus and registers (which retain values). A zero on the SHDN pin overrides the SHDN bit. IDLE mode 1 1 0 1 1 1 1 X 10 Power-up mode All OFF except RF PLL, RF VCO, serial bus, and registers (which retain values). RF PLL and RF VCO are on or off depending on the control-bit values before toggling the IDLE pin to zero. The 5 different TX blocks can be toggled ON/OFF using the serial bus. GmC X RF PLL X RF VCO IDLE_PRG BIT (1) X COMMENTS I/Q MOD, RF UC, PA DRIVER IDLE PIN (8) 0 POWER-DOWN MODES OFF OFF OFF OFF ON OFF X X OFF ON OFF X X X ON X X X X SERIAL BUS SHDN BIT (0) Table 5. Power-Down Modes SHDN PIN (9) MAX2395 WCDMA Quasi-Direct Modulator with VGA and PA Driver OFF ON ______________________________________________________________________________________ WCDMA Quasi-Direct Modulator with VGA and PA Driver BIT 14 BIT 5 BIT 4 A1 MAX2395 BIT 15 SDATA A0 SCLK tCWH tCWL CS tCS tCH tES Figure 1. 3-Wire SPI/MICROWIRE Serial-Interface Timing Diagram MSB LSB 20-BIT REGISTER B5 B4 B3 B2 B1 B0 A3 ADDRESS 4 BITS A2 A1 RFM DIVIDE RATIO REGISTER (16 BITS) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 ADDRESS 0 1 0 RFR DIVIDE RATIO REGISTER (9 BITS) B6 B5 B4 B3 B2 B1 B0 0 ADDRESS 0 0 0 B1 B0 0 ADDRESS 1 0 0 B9 DATA 16 BITS B8 B7 B15 B14 B13 B12 B11 B10 B15 B14 B13 B12 B11 B10 B15 B14 B13 B12 B11 B10 B15 B14 B13 B12 B11 OPERATION CONTROL REGISTER (16 BITS) B10 B9 B8 B7 B6 B5 B9 B8 B7 B6 B4 B3 B2 A0 Figure 2. Register Assignments It is recommended that the exposed pad be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. Soldering the pad to ground is critical for proper heat dissipation. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as a slot radiator and reduce its shield effectiveness. ______________________________________________________________________________________ 11 MAX2395 WCDMA Quasi-Direct Modulator with VGA and PA Driver Typical Operating Circuit POUT VCC _PA BIAS_SET VGC VCC _IF VCC _BB N.C. 26 25 24 VTUNE BVP 23 SERIAL BUS 1 VCC 22 21 GND_VCO 100pF VCC _VCO 20 2 RF INTEGER-N PLL 3 LO GEN 4 5 0° 19 18 17 RFCP WCDMA MODEM N.C. POWER AMPLIFIER 27 N.C. 28 CS SCLK VCC SDATA TCXO 19.2MHz VCC _CP VCC _PLL MAX2395 90° 6 16 7 15 REF LD 100pF 14 N.C. 13 Q- 12 Q+ 11 I- 10 I+ 9 SHDN IDLE 8 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 12 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 QFN-EP G2855-2 21-0091 28 TQFN-EP T2855-3 21-0140 ______________________________________________________________________________________ WCDMA Quasi-Direct Modulator with VGA and PA Driver REVISION NUMBER REVISION DATE 2 5/05 — 3 1/09 Removed obsolete parts MAX2394/MAX2403/MAX2407 from data sheet DESCRIPTION PAGES CHANGED — 1–13 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX2395 Revision History