SEMICONDUCTOR TECHNICAL DATA # $! !#" L SUFFIX CERAMIC CASE 620 " The MC14506UB is an expandable AND–OR–INVERT gate with inhibit and 3–state output. The expand option allows cascading with any other gate, which may be carried as far as desired as long as the propagation delay added with each gate is considered. For example, the second AOI gate in this device may be used to expand the first gate, giving an expanded 4–wide, 2–input AOI gate. This device is useful in data control and digital multiplexing applications. • • • • • P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B 3–State Output Separate Inhibit Line Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–Power TTL Loads or One Low–Power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ORDERING INFORMATION MC14XXXUBCP MC14XXXUBCL MC14XXXUBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL Lead Temperature (8–Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v TRUTH TABLE A B C D E LOGIC DIAGRAM AA BA CA DA EA 1 2 3 4 5 15 ZA VDD = PIN 16 VSS = PIN 8 INH 6 DIS 14 3–STATE OUTPUT DISABLE v Inhibit Disable Z 0 0 0 X 0 X X 0 0 0 X 0 0 X 0 X 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 X 1 X X 0 1 X X X X 1 X 0 X 1 X 1 X X 0 0 X X X 0 0 0 0 1 0 0 0 X X X X X X X X X X 1 X 0 1 0 High Impedance X = Don’t Care EB 13 DB 12 CB 11 BB 10 AB 9 7 ZB Z = (AB + CD + E + I) REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14506UB 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.0 2.0 2.5 — — — 2.25 4.50 6.75 1.0 2.0 2.5 — — — 1.0 2.0 2.5 5.0 10 15 4.0 8.0 12.5 — — — 4.0 8.0 12.5 2.75 5.50 8.25 — — — 4.0 8.0 12.5 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 1.0 2.0 4.0 — — — 0.002 0.004 0.006 1.0 2.0 4.0 — — — 30 60 120 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Three–State Leakage Current ITL 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (0.6 µA/kHz) f + IDD IT = (1.1 µA/kHz) f + IDD IT = (1.7 µA/kHz) f + IDD — ± 0.1 — ± 0.0001 ± 0.1 µAdc — ± 3.0 µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. PIN ASSIGNMENT MC14506UB 2 AA 1 16 VDD BA 2 15 ZA CA 3 14 DISABLE DA 4 13 EB EA 5 12 DB INH 6 11 CB ZB 7 10 BB VSS 8 9 AB MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 295 110 75 580 225 180 5.0 10 15 — — — 270 95 65 480 175 140 5.0 10 15 — — — 180 75 50 430 160 125 5.0 10 15 — — — 200 80 55 330 110 90 5.0 10 15 — — — 220 100 65 500 225 160 5.0 10 15 — — — 230 95 60 400 175 150 5.0 10 15 — — — 60 45 35 150 110 90 Unit tTLH, tTHL Data Propagation Delay Time tPLH = (1.7 ns/pF) CL + 210 ns tPLH = (0.66 ns/pF) CL + 77 ns tPLH = (0.5 ns/pF) CL + 50 ns tPLH tPHL = (1.7 ns/pF) CL + 185 ns tPHL = (0.66 ns/pF) CL + 62 ns tPHL = (0.5 ns/pF) CL + 40 ns tPHL Expand Propagation Delay Time tPLH = (1.7 ns/pF) CL + 95 ns tPLH = (0.66 ns/pF) CL + 42 ns tPLH = (0.5 ns/pF) CL + 25 ns tPLH tPHL = (1.7 ns/pF) CL + 115 ns tPHL = (0.66 ns/pF) CL + 47 ns tPHL = (0.5 ns/pF) CL + 30 ns tPHL Inhibit Propagation Delay Time tPLH = (1.7 ns/pF) CL + 135 ns tPLH = (0.66 ns/pF) CL + 67 ns tPLH = (0.5 ns/pF) CL + 40 ns tPLH tPHL = (1.7 ns/pF) CL + 145 ns tPHL = (0.66 ns/pF) CL + 62 ns tPHL = (0.5 ns/pF) CL + 35 ns tPHL 3–State Propagation Delay Time “1” to High Impedance ns ns ns ns ns ns ns tPHZ ns “0” to High Impedance tPLZ 5.0 10 15 — — — 90 55 40 225 140 100 ns High Impedance to “1” tPZH 5.0 10 15 — — — 110 50 40 300 125 100 ns High Impedance to “0” tPZL 5.0 10 15 — — — 170 70 50 425 175 125 ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” Is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 16 16 VDD = 15 Vdc a b c 12 10 10 Vdc a b c 8.0 6.0 UNUSED INPUTS CONNECTED TO VSS 5.0 Vdc a 4.0 b a b c c 2.0 0 0 2.0 14 Vout , OUTPUT VOLTAGE (Vdc) Vout , OUTPUT VOLTAGE (Vdc) 14 4.0 6.0 8.0 10 TA = + 125°C TA = + 25°C TA = – 55°C 12 14 VDD = 15 Vdc a 12 a TA = + 125°C b TA = + 25°C c TA = – 55°C b c 10 Vdc a b 10 8.0 c A AND B CONNECTED TO Vin ENABLE INPUT CONNECTED TO VDD. OTHER INPUTS CONNECTED TO VSS. 6.0 5.0 Vdc 4.0 a b c 2.0 0 16 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc) (a) Expand Inputs (b) Data Inputs 12 14 16 Figure 1. Typical Voltage Transfer Characteristics MOTOROLA CMOS LOGIC DATA MC14506UB 3 VDD 16 VDD 16 INH AA BA CA DA EA AB BB CB DB EB DIS ZA VOH INH AA BA CA DA EA AB BB CB DB EB DIS IOH EXTERNAL POWER SUPPLY ZB 8 8 VSS Figure 2. Typical Output Source Characteristics Test Circuit ZA VOL IOL EXTERNAL POWER SUPPLY ZB VSS Figure 3. Typical Output Sink Characteristics Test Circuit VDD 16 VDD 16 INH AA BA CA DA EA AB BB CB DB EB DIS 8 VDD ZA ITL PULSE GENERATOR B 50% DUTY CYCLE A VSS INH AA BA CA DA EA AB BB CB DB EB DIS 8 ZB Figure 4. 3–State Leakage Current Test Circuit MC14506UB 4 0.01 µF CERAMIC ZA ZB VSS CL 500 µF CL IDD Figure 5. Typical Power Dissipation Test Circuit MOTOROLA CMOS LOGIC DATA VDD 16 PULSE GENERATOR INH AA BA CA DA EA AB BB CB DB EB DIS ZA ZB 8 VSS 20 ns 20 ns VSS tPLH VOH tPHL 90% 50% 10% OUTPUT CL VDD 90% 50% 10% INPUT VOL tTHL CL tTLH Figure 6. Switching Time Test Circuit and Waveforms (Data Inputs) VDD Vout VDD 16 B A PULSE GENERATOR S1 INH AA BA CA DA EA AB BB CB DB EB DIS ZA 8 VSS 20 ns CL S2 20 ns 90% 50% 10% DISABLE INPUT 1k A tPZL 90% tPLZ B 10% tPHZ OUTPUT ZB 90% tPZH 10% VOH ≈ 2.5 V @ VDD = 5 V, 10 V AND 15 V ≈ 2 V @ VDD = 5 V ≈ 6 V @ VDD = 10 V ≈ 10 V @ VDD = 15 V VOL * To test other side of circuit connect to this output and change switch (S1) to other expand input (E). SWITCH POSITIONS TEST S1 S2 tPLZ A A tPHZ B B tPZL A A tPZH B B Figure 7. Switching Time Test Circuit and Waveforms (For 3–State Output) MOTOROLA CMOS LOGIC DATA MC14506UB 5 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– K H G D J 16 PL 0.25 (0.010) MC14506UB 6 SEATING PLANE M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14506UB/D* MC14506UB MC14506UB/D 7