Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER GENERAL DESCRIPTION ICS HiPerClockS™ FEATURES • Fully integrated PLL The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. • 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL The ICS87973I-147 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 10MHz to 150MHz • VCO range: 240MHz to 500MHz The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. The input frequency range is 6MHz to 120MHz. • Output skew: 200ps (maximum) • Cycle-to-cycle jitter, (all banks ÷ 4): 55ps (maximum) • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Pin compatible with MPC973 The ICS87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. • Compatible with PowerPC™ and Pentium™ Microprocessors VDD QFB GNDO EXT_FB QB3 VDDO QB2 GNDO 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. QB1 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. VDDO 1. System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. QB0 GNDO Example Applications: FSEL_FB0 PIN ASSIGNMENT FSEL_B1 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 FSEL_FB1 FSEL_B0 41 25 QSYNC FSEL_A1 42 24 GNDO FSEL_A0 43 23 QC0 QA3 44 22 VDDO VDDO 45 21 QC1 ICS87973I-147 FSEL_C0 19 FSEL_C1 QA1 48 18 QC2 VDDO 49 17 VDDO QA0 50 16 QC3 GNDO 51 15 GNDO VCO_SEL 52 1 14 INV_CLK 5 6 7 8 9 10 11 12 13 VDDA nCLK CLK CLK1 CLK0 CLK_SEL REF_SEL 4 PLL_SEL 3 FSEL_FB2 GNDI 2 FRZ_DATA 20 47 FRZ_CLK 46 nMR/OE QA2 GNDO 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View 87973DYI-147 www.icst.com/products/hiperclocks.html 1 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER BLOCK DIAGRAM VCO_SEL PLL_SEL REF_SEL CLK 1 nCLK D 0 CLK0 0 CLK1 1 Q 0 PHASE DETECTOR 1 VCO LPF CLK_SEL EXT_FB D Q SYNC FRZ QA0 SYNC FRZ QA1 SYNC FRZ QA2 SYNC FRZ QA3 SYNC FRZ QB0 SYNC FRZ QB1 SYNC FRZ QB2 SYNC FRZ QB3 FSEL_FB2 nMR/OE D POWER-ON RESET Q ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 D Q ÷2, ÷4, ÷6, ÷8 FSEL_A0:1 2 0 ÷4, ÷6, ÷8, ÷10 ÷2 2 D Q D Q QC0 SYNC FRZ QC1 SYNC FRZ QC2 SYNC FRZ QC3 QFB 1 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2 2 SYNC PULSE 3 SYNC FRZ QSYNC DATA GENERATOR FRZ_CLK FRZ_DATA OUTPUT DISABLE CIRCUITRY 12 INV_CLK 87973DYI-147 www.icst.com/products/hiperclocks.html 2 REV. A AUGUST 26, 2003 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER SIMPLIFIED BLOCK DIAGRAM nMR/OE FSEL_A[0:1] 2 CLK 1 nCLK CLK0 0 CLK1 1 CLK_SEL 0 PLL VCO RANGE 240MHz - 500MHz 0 REF_SEL EXT_FB ÷2 0 ÷1 1 1 FSEL_ A1 A0 0 0 0 1 1 0 1 1 PLL_SEL SYNC FRZ QA0 SYNC FRZ QA1 SYNC FRZ QA2 SYNC FRZ QA3 SYNC FRZ QB0 SYNC FRZ QB1 SYNC FRZ QB2 SYNC FRZ QB3 FSEL_B[0:1] 2 FSEL_ B1 B0 0 0 0 1 1 0 1 1 VCO_SEL QAx ÷4 ÷6 ÷8 ÷12 QBx ÷4 ÷6 ÷8 ÷10 FSEL_C[0:1] 2 FSEL_ C1 C0 0 0 0 1 1 0 1 1 QCx ÷2 ÷4 ÷6 ÷8 QC0 0 1 SYNC FRZ QC1 SYNC FRZ QC2 SYNC FRZ QC3 INV_CLK FSEL_FB[0:2] 3 FSEL_ FB2 FB1 FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FRZ_CLK FRZ_DATA 87973DYI-147 OUTPUT DISABLE CIRCUITRY www.icst.com/products/hiperclocks.html 3 QFB SYNC FRZ QSYNC REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 GNDI Power Type Description 2 nMR/OE Input Pullup 3 FRZ_CLK Input Pullup 4 FRZ_DATA Input Pullup 5, 26, 27 FSEL_FB2, FSEL_FB1, FSEL_FB0 Input Pullup 6 PLL_SEL Input Pullup 7 REF_SEL Input Pullup 8 CLK_SEL Input Pullup 9, 10 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 11 CLK Input Pullup Non-inver ting differential clock input. 12 nCLK Input Inver ting differential clock input. VDD/2 default when left floating. 13 VDDA Power Analog supply pin. 14 INV_CLK Input Pullup Power supply ground. Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs to tristate and resets output divide circuitr y. Enables and disables all outputs. LVCMOS / LVTTL interface levels. Clock input for freeze circuitr y. LVCMOS / LVTTL interface levels. Configuration data input for freeze circuitr y. LVCMOS / LVTTL interface levels. Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels. Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVCMOS / LVTTL interface levels. Selects between CLK0 or CLK1 and CLK, nCLK inputs. When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1. LVCMOS / LVTTL interface levels. Clock select input. Selects between CLK0 and CLK1 as phase detector reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Inver ted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. 15, 24, 30, 35, 39, 47, 51 16, 18, 21, 23 17, 22, 33, 37, 45, 49 GNDO Power Power supply ground. QC3, QC2, QC1, QC0 Output Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. VDDO Power Output supply pins. 19, 20 FSEL_C1, FSEL_C0 Input 25 QSYNC Output Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. 28 VDD Power Core supply pins. 29 QFB Output Feedback clock output. LVCMOS / LVTTL interface levels. 31 EXT_FB Input 32, 34, 36, 38 44, 46, 48, 50 QB3, QB2, QB1, QB0 FSEL_B1, FSEL_B0 FSEL_A1, FSEL_A0 QA3, QA2, QA1, QA0 52 VCO_SEL 40, 41 42, 43 Pullup Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. Extended feedback. LVCMOS / LVTTL interface levels. Bank B clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. Output Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. Output Input Pullup Bank A clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels. NOTE: Pullup refer to internal input resistors. See table 2, Pin Characteristics, for typical values. 87973DYI-147 www.icst.com/products/hiperclocks.html 4 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP, RPULLDOWN Input Pullup/Pulldown Resistor 51 KΩ Power Dissipation Capacitance (per output) Output Impedance CPD ROUT Minimum Typical Maximum VDD, VDDA, VDDO = 3.465V 5 7 Units 18 pF 12 Ω TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs Inputs Outputs Inputs Outputs FSEL_A1 FSEL_A0 QA FSEL_B1 FSEL_B0 QB FSEL_C1 FSEL_C0 QC 0 0 ÷4 0 0 ÷4 0 0 ÷2 0 1 ÷6 0 1 ÷6 0 1 ÷4 1 0 ÷8 1 0 ÷8 1 0 ÷6 1 1 ÷12 1 1 ÷10 1 1 ÷8 TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE Control Pin Logic 0 Logic 1 VCO_SEL VCO/2 VCO REF_SEL CLK0 or CLK1 CLK, nCLK CLK_SEL CLK0 CLK1 PLL_SEL BYPASS PLL Enable PLL nMR/OE Master Reset/Output Hi Z Enable Outputs INV_CLK Non-Inver ted QC2, QC3 Inver ted QC2, QC3 87973DYI-147 www.icst.com/products/hiperclocks.html 5 REV. A AUGUST 26, 2003 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER fVCO 1:1 MODE QA QC QSYNC 2:1 MODE QA QC QSYNC 3:1 MODE QC(÷2) QA(÷4) QSYNC 3:2 MODE QC(÷2) QA(÷8) QSYNC 4:1 MODE QC(÷2) QA(÷8) QSYNC 4:3 MODE QA(÷6) QC(÷8) QSYNC 6:1 MODE QA(÷12) QC(÷2) QSYNC FIGURE 1. TIMING DIAGRAMS 87973DYI-147 www.icst.com/products/hiperclocks.html 6 REV. A AUGUST 26, 2003 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 42.3°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 2.935 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 225 mA IDDA Analog Supply Current 20 mA Maximum Units VDD + 0.3 V NOTE: Special thermal handling may be required in some configurations. TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Test Conditions Minimum Input High Voltage LVCMOS Inputs 2 LVCMOS Inputs -0.3 VIL Input Low Voltage IIN Input Current VOH Output High Voltage IOH = -20mA VOL Output Low Voltage IOL = 20mA VPP Peak-to-Peak Input Voltage; NOTE 1, 2 CLK, nCLK VCMR Common Mode Input Voltage; NOTE 1, 2 CLK, nCLK Typical 0.8 V ±120 µA 2.4 V 0.5 V 0.3 1 V VDD - 2V VDD - 0.6V V Maximum Units NOTE 1: Common mode voltage is defined as VIH of the differential signal. NOTE 2. For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical CLK0, CLK1, 120 MHz CLK, nCLK; NOTE 1 FRZ_CLK 20 MHz NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * Feedback Divide" is in the VCO range of 240MHz to 500MHz. fIN 87973DYI-147 Input Frequency www.icst.com/products/hiperclocks.html 7 REV. A AUGUST 26, 2003 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX t(Ø) Test Conditions Output Frequency CLK0 Static Phase Offset; CLK1 NOTE 1 CLK, nCLK Maximum Units ÷2 150 MHz ÷4 125 MHz ÷6 83.33 MHz ÷8 62.5 MHz QFB ÷8 In Frequency = 50MHz Minimum Typical -10 145 300 ps -65 90 245 ps -130 18 165 ps 200 ps 55 ps 500 MHz 10 mS 150 700 ps tsk(o) Output Skew; NOTE 2 tjit(cc) Cycle-to-Cycle Jitter; NOTE 3, 4 fVCO PLL VCO Lock Range tLOCK PLL Lock Time; NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle 45 55 % tPZL, tPZH Output Enable Time; NOTE 3 2 10 ns tPLZ, tPHZ Output Disable TIme; NOTE 3 2 8 ns All Banks ÷ 4 240 0.8V to 2V NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 87973DYI-147 www.icst.com/products/hiperclocks.html 8 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% VDD SCOPE VDD, VDDA, VDDO nCLK Qx LVCMOS V V Cross Points PP CMR CLK GND GND -1.65V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT V V DDO n ➤ DDO DDO 2 ➤ tcycle V V DDO 2 ➤ QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB DIFFERENTIAL INPUT LEVEL Qx 2 tcycle n+1 2 ➤ V DDO t jit(cc) = tcycle n –tcycle n+1 Qy 2 t sk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER nCLK VDD 2 CLK0, CLK1 CLK VDD VDD 2 ➤ ➤ t (Ø) 2 EXT_FB ➤ t (Ø) ➤ EXT_FB t (Ø) mean = Static Phase Offset t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) STATIC PHASE OFFSET (LVCMOS) STATIC PHASE OFFSET (DIFFERENTIAL) V DDO 2V Clock Outputs QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB 2V 0.8V 0.8V tR 2 Pulse Width t tF odc = PERIOD t PW t PERIOD OUTPUT RISE/FALL TIME 87973DYI-147 OUTPUT DUTY CYCLE/ PULSE WIDTH PERIOD www.icst.com/products/hiperclocks.html 9 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION USING THE OUTPUT FREEZE CIRCUITRY OVERVIEW To enable low power states within a system, each output of ICS87973I-147 (Except QC0 and QFB) can be individually frozen (stopped in the logic “0” state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the ICS87973I-147 serial interface are FPGA’s and ASICs. edge of the FRZ_CLK signal. To place an output in the freeze state, a logic “0” must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic “1” must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic “0”, it is used for the start bit of the next cycle; otherwise, the device will wait and won’t start the next cycle until it sees a logic “0” bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state. PROTOCOL The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic “0” start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the ICS87973I-147 can sample each FRZ_DATA bit with the rising FRZ_DATA rt Sta it B QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC FRZ_CLK FRZ Clocked FRZ Latched FIGURE 2A. FREEZE DATA INPUT PROTOCOL Qx FREEZE Internal Qx Internal Qx Out FIGURE 2B. OUTPUT DISABLE TIMING 87973DYI-147 www.icst.com/products/hiperclocks.html 10 REV. A AUGUST 26, 2003 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87973I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01µF 10Ω V DDA .01µF 10 µF FIGURE 3. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 4 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87973DYI-147 www.icst.com/products/hiperclocks.html 11 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 87973DYI-147 nCLK Zo = 50 Ohm FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY www.icst.com/products/hiperclocks.html 12 BY REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER SCHEMATIC EXAMPLE Figure 6 shows a schematic example of using ICS87973I-147. This example shows general design of input, output termination, logic control input pull up/down and power supply filtering. In this example, the clock input is driven by an LVCMOS driver. R1 43 Zo = 50 52 51 50 49 48 47 46 45 44 43 42 41 40 VDD U1 1K Serial Clcok R8 1K R10 1 2 3 4 5 6 7 8 9 10 11 12 13 1K Serial Data VDD RS Zo = 50 LVCMOS CLOCK GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK VDDA R7 VDD C16 10u C11 0.01u R5 1K R6 1K ICS87973I-147 14 15 16 17 18 19 20 21 22 23 24 25 26 10 - 15 39 38 37 36 35 34 33 32 31 30 29 28 27 GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD FSEL_FB0 INV_CLK GNDO QC3 VDDO QC2 FSEL_C1 FSEL_C0 QC1 VDDO QC0 GNDO QSYNC FSEL_FB1 R9 VCO_SEL GNDO QA0 VDDO QA1 GNDO QA2 VDDO QA3 FSEL_A0 FSEL_A1 FSEL_B0 FSEL_B1 VDD R2 Logic Input Pin Examples Set Logic Input to '1' VDD RU1 1K Zo = 50 R4 1K Set Logic Input to '0' VDD RU2 Not Install To Logic Input pins RD1 Not Install 43 To Logic Input pins RD2 1K R3 (U1-17) C3 0.1uF VDD (U1-22) C4 0.1uF (U1-28) C5 0.1uF (U1-33) C6 0.1uF (U1-37) C7 0.1uF 43 (U1-45) C8 0.1uF Zo = 50 (U1-49) C9 0.1uF VDD=3.3V FIGURE 6. ICS87973I-147 SCHEMATIC EXAMPLE 87973DYI-147 www.icst.com/products/hiperclocks.html 13 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 58.0°C/W 42.3°C/W 47.1°C/W 36.4°C/W 42.0°C/W 34.0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87973I-147 is: 8364 87973DYI-147 www.icst.com/products/hiperclocks.html 14 REV. A AUGUST 26, 2003 ICS87973I-147 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER FOR 52 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BCC MINIMUM NOMINAL MAXIMUM 52 N A -- -- 1.60 A1 A2 0.05 -- 0.15 1.35 1.40 1.45 b 0.22 0.32 0.38 c 0.09 -- 0.20 12.00 BASIC D D1 10.00 BASIC E 12.00 BASIC E1 10.00 BASIC e 0.65 BASIC L 0.45 -- 0.75 θ 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 87973DYI-147 www.icst.com/products/hiperclocks.html 15 REV. A AUGUST 26, 2003 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87973DYI-147 ICS7973DI147 52 Lead LQFP 160 per tray -40°C to 85°C ICS87973DYI-147T ICS7973DI147 52 Lead LQFP on Tape and Reel 500 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87973DYI-147 www.icst.com/products/hiperclocks.html 16 REV. A AUGUST 26, 2003