HUF76107D3, HUF76107D3S
Data Sheet
20A, 30V, 0.052 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power
MOSFETs are manufactured using
the innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is
capable of withstanding high energy in the avalanche mode
and the diode exhibits very low reverse recovery time and
stored charge. It was designed for use in applications
where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay
drivers, low voltage bus switches, and power management
in portable and battery operated products.
January 2003
Features
• Logic Level Gate Drive
• 20A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.052Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76107.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
HUF76107D3
TO-251AA
76107D
HUF76107D3S
TO-252AA
76107D
D
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76107D3ST.
S
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
JEDEC TO-252AA
SOURCE
DRAIN
GATE
GATE
DRAIN
(FLANGE)
SOURCE
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
30
V
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
20
10.5
10
Figure 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
0.30
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figure 9, 10)
-
0.042
0.052
Ω
ID = 10.5A, V GS = 5V (Figure 9)
-
0.058
0.080
Ω
ID = 10A, VGS = 4.5V (Figure 9)
-
0.065
0.085
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R θJC
(Figure 3)
-
-
3.3
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-251, TO-252
-
-
100
oC/W
VDD = 15V, ID ≅ 10A, RL = 1.50Ω,
VGS = 4.5V, RGS = 33Ω
(Figure 15)
-
-
120
ns
-
14
-
ns
tr
-
66
-
ns
td(OFF)
-
16
-
ns
tf
-
22
-
ns
tOFF
-
-
57
ns
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
©2003 Fairchild Semiconductor Corporation
tON
td(ON)
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Electrical Specifications
TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
75
ns
-
18
-
ns
tr
-
30
-
ns
td(OFF)
-
62
-
ns
tf
-
20
-
ns
tOFF
-
-
125
ns
-
8.6
10.3
nC
-
4.7
5.7
nC
-
0.35
0.42
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 20A, RL =0.75Ω,
VGS = 10V, RGS = 33Ω
(Figures 16)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V,ID ≅ 10.5A,
RL = 1.43Ω
Ig(REF) = 1.0mA
(Figure 14)
Gate to Source Gate Charge
Qgs
-
1.00
-
nC
Gate to Drain “Miller” Charge
Qgd
-
2.40
-
nC
-
315
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
-
170
-
pF
Reverse Transfer Capacitance
CRSS
-
30
-
pF
MIN
TYP
MAX
UNITS
ISD = 10.5A
-
-
1.25
V
trr
ISD = 10.5A, dISD/dt = 100A/µs
-
-
39
ns
QRR
ISD = 10.5A, dISD/dt = 100A/µs
-
-
49
nC
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
Typical Performance Curves Unless otherwise specified
25
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
©2003 Fairchild Semiconductor Corporation
150
20
VGS = 10V
15
VGS = 4.5V
10
5
0
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x Zθ JC x RθJC + TC
SINGLE PULSE
0.01
10-5
10 -4
10-2
10-3
10-1
t, RECTANGULAR PULSE DURATION (s)
10 0
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
IDM, PEAK CURRENT (A)
TC = 25 oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
VGS = 10V
I
=
150 - TC
I25
125
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
10 0
101
FIGURE 4. PEAK CURRENT CAPABILITY
200
TJ = MAX RATED
TC = 25oC
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
VDSS(MAX) = 30V
100
IAS, AVALANCHE CURRENT (A)
200
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
10
STARTING T J = 150oC
10ms
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
1
0.001
0.01
1
0.1
tAV, TIME IN AVALANCHE (ms)
10
100
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
©2003 Fairchild Semiconductor Corporation
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
30
30
-55oC
VGS = 5V
25
25oC
20
15
10
VGS = 4.5V
20
15
VGS = 4V
10
VGS = 3.5V
5
5
0
0
0
1
3
5
2
4
VGS, GATE TO SOURCE VOLTAGE (V)
6
VGS = 3V
0
2
3
4
5
6
FIGURE 8. SATURATION CHARACTERISTICS
2.00
90
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ID = 20A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
80
ID = 12A
70
ID = 5A
60
50
40
30
2
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
4
1.75
1.50
1.25
1.00
0.75
0.50
-60
0
60
120
180
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.15
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS , ID = 250µA
1.1
1.0
0.9
0.8
0.7
0.6
-60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
NORMALIZED GATE
THRESHOLD VOLTAGE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 10V
150oC
I D, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25 VDD = 15V
0
60
120
TJ, JUNCTION TEMPERATURE (oC)
180
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
ID = 250µA
1.10
1.05
1.00
0.95
0.90
-60
0
60
120
TJ , JUNCTION TEMPERATURE (oC)
180
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
10
600
C, CAPACITANCE (pF)
500
VGS , GATE TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ C DS + CGD
400
C ISS
300
200
COSS
100
CRSS
0
0
5
15
10
25
20
VDD = 15V
8
6
4
2
0
30
WAVEFORMS IN
DESCENDING ORDER:
I D = 20A
I D = 12A
I D = 5A
0
4
2
6
8
10
Qg, GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
100
100
VGS = 4.5V, VDD = 15V, ID = 10A, RL= 1.50Ω
VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω
tr
60
td(OFF)
40
td(OFF)
80
SWITCHING TIME (ns)
SWITCHING TIME (ns)
80
tf
20
tr
60
tf
40
td(ON)
20
td(ON)
0
0
10
20
30
40
0
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10
VGS
Qg(5)
+
-
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
RGS
VGS
90%
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORMS
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
PSPICE Electrical Model
SUBCKT HUF76107 2 1 3 ;
REV June 1998
CA 12 8 4.2e-10
CB 15 14 4.9e-10
CIN 6 8 2.85e-10
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
ESLC
11
-
EBREAK 11 7 17 18 35.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
EVTEMP
RGATE + 18 22
9
20
GATE
1
+
50
-
LDRAIN 2 5 1e-9
LGATE 1 9 3.61e-9
LSOURCE 3 7 3.61e-9
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-3
RGATE 9 20 3.39
RLDRAIN 2 5 10
RLGATE 1 9 36.1
RLSOURCE 3 7 36.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 30e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
5
51
IT 8 17 1
RLDRAIN
RSLC1
51
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),7))}
.MODEL DBODYMOD D (IS = 2.8e-13 IKF = 5 RS = 1.37e-2 TRS1 = 2e-4 TRS2 = 2e-6 CJO = 4.9e-10 TT = 2.88e-8 M = 3.9e-1 XTI =4.75 )
.MODEL DBREAKMOD D (RS = 2.5e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7)
.MODEL DPLCAPMOD D (CJO = 3.2e-10 IS = 1e-30 N = 10 M = 7.4e-1)
.MODEL MMEDMOD NMOS (VTO = 2.07 KP = 1.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)
.MODEL MSTROMOD NMOS (VTO = 2.4 KP = 19.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.8 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS=.1)
.MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8)
.MODEL RDRAINMOD RES (TC1 = 3.9e-2 TC2 = 5.5e-5)
.MODEL RSLCMOD RES (TC1 = 1e-4 TC2 = 3.2e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-12 TC2 = 6e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -5.96e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.4e-3 TC2 = 1e-10)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.2 VOFF= -0.5)
VON = -0.5 VOFF= -4.2)
VON = -0.8 VOFF= 0.0)
VON = 0.0 VOFF= -0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
SABER Electrical Model
nom temp=25 deg c
30v LL Ultrafet
REV Junel 1998
template huf76107 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=2.8e-13, xti=4.75, cjo=4.9e-10,tt=2.88e-8, m=3.9e-1)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=3.2e-10,is=1e-30,n=10,m=7.4e-1)
m..model mmedmod = (type=_n,vto=2.07,kp=1.25,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=19.5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.8,kp=1e-1,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.2,voff=-0.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-4.2)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.0,voff=-0.8)
LDRAIN
DPLCAP
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
c.ca n12 n8 = 4.2e-10
c.cb n15 n14 = 4.9e-10
c.cin n6 n8 = 2.85e-10
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 3.61e-9
l.lsource n3 n7 = 3.61e-9
EVTEMP
RGATE + 18 22
9
20
21
71
11
16
MWEAK
DBODY
6
EBREAK
+
17
18
MMED
MSTRO
RLGATE
CIN
-
8
LSOURCE
7
SOURCE
3
RSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9.94e-4,tc2=-9.84e-8
res.rdbody n71 n5 =1.37e-2, tc1=2e-4, tc2=2e-6
res.rdbreak n72 n5 =2.5e-1, tc1=9.94e-4, tc2=9.12e-7
res.rdrain n50 n16 = 3.7e-3, tc1=3.9e-2,tc2=5.5e-5
res.rgate n9 n20 = 3.39
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 36.1
res.rlsource n3 n7 = 36.1
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=3.2e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 30e-3, tc1=1e-12,tc2=6e-6
res.rvtemp n18 n19 = 1, tc1=-1.4e-3,tc2=1e-10
res.rvthres n22 n8 = 1, tc1=-1.9e-3,tc2=-5.96e-6
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
DRAIN
2
5
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 35.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/50))**7 ))
}
}
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
SPICE Thermal Model
th
JUNCTION
REV June1998
HUF76107
CTHERM1 th 6 5.0e-5
CTHERM2 6 5 9.0e-4
CTHERM3 5 4 1.3e-3
CTHERM4 4 3 1.3e-3
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 7.9e-3
RTHERM1
RTHERM1 th 6 2.0e-4
RTHERM2 6 5 6.0e-3
RTHERM3 5 4 3.5e-2
RTHERM4 4 3 8.5e-1
RTHERM5 3 2 5.1e-1
RTHERM6 2 tl 1
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76107
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-5
ctherm.ctherm2 6 5 = 9.0e-4
ctherm.ctherm3 5 4 = 1.3e-3
ctherm.ctherm4 4 3 = 1.3e-3
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm6 2 tl = 7.9e-3
rtherm.rtherm1 th 6 = 2.0e-4
rtherm.rtherm2 6 5 = 6.0e-3
rtherm.rtherm3 5 4 = 3.5e-2
rtherm.rtherm4 4 3 = 8.5e-1
rtherm.rtherm5 3 2 = 5.1e-1
rtherm.rtherm6 2 tl = 1
}
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2003 Fairchild Semiconductor Corporation
CASE
HUF76107D3, HUF76107D3S Rev. B1
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Advance Information
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Rev. I2