Hynix HY5V66GF-P 4 banks x 1m x 16bit synchronous dram Datasheet

HY5V66GF
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hyundai HY5V66GF is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V66GF is organized as 4banks of 1,048,576x16.
HY5V66GF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply Note)
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 60Ball FD-BGA with 0.65mm of
pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
•
Data mask function by UDQM or LDQM
•
Internal four banks operation
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
HY5V66GF-H
133MHz
HY5V66GF-P
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 1Mbits
x16
LVTTL
10.1x 6.4 60Ball 0.65
Pin -pitch FD-BGA
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.4/Nov. 01
1
HY5V66GF
PIN CONFIGURATION
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 0.4/Nov. 01
2
HY5V66GF
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
1Mx16 Bank 3
CLK
Row active
Row
Pre
Decoders
1Mx16 Bank 2
CS
Column
Pre
Decoders
UDQM
Y decoders
LDQM
Bank Select
A0
A1
Rev. 0.4/Nov. 01
DQ1
DQ14
DQ15
Column Add
Counter
Address
Registers
Address buffers
A11
BA0
BA1
DQ0
I/O Buffer & Logic
Column
Active
Memory
Cell
Array
Sense AMP & I/O Gate
WE
X decoders
refresh
1Mx16 Bank 0
X decoders
CAS
State Machine
RAS
1Mx16 Bank 1
X decoders
X decoders
CKE
Burst
Counter
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
3
HY5V66GF
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
3.0
VDDQ + 2.0
V
1,2
Input Low Voltage
VIL
VSSQ - 2.0
0
0.8
V
1,3
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3VNote2, VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level
Voutref
1.4
V
CL
50
pF
Input Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Note
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Rev. 0.4/Nov. 01
4
HY5V66GF
CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Pin
Input capacitance
Data input / output capacitance
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS,
CAS, WE, UDQM, LDQM
CI2
2.5
5
pF
DQ0 ~ DQ15
CI/O
2
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3VNote3)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
Rev. 0.4/Nov. 01
5
HY5V66GF
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3VNote5, VSS=0V)
Speed
Parameter
Operating Current
Precharge Standby Current
in Power Down Mode
Symbol
-P
85
80
Unit
Note
mA
1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
IDD2P
CKE ≤ VIL(max), tCK = min
2
mA
IDD2PS
CKE ≤ VIL(max), tCK = ∞
2
mA
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
15
mA
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
12
mA
IDD3P
CKE ≤ VIL(max), tCK = min
6
mA
IDD3PS
CKE ≤ VIL(max), tCK = ∞
5
mA
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
30
mA
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
20
mA
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Active Standby Current
in Non Power Down Mode
Burst Mode Operating Current
-H
IDD1
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Test Condition
CL=3
CL=2
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
150
120
mA
120
mA
160
mA
1
mA
1
2
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
Rev. 0.4/Nov. 01
6
HY5V66GF
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-H
Parameter
Unit
Min
System clock
cycle time
CAS Latency = 3
-P
Symbol
tCK3
Max
7.5
Min
10
1000
CAS Latency = 2
Note
Max
ns
1000
tCK2
10
Clock high pulse width
tCHW
2.5
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
-
3
-
ns
1
6
ns
Access time from
clock
10
ns
CAS Latency = 3
tAC3
5.4
CAS Latency = 2
tAC2
6
-
6
ns
2
Data-out hold time
tOH
2.7
-
3
-
ns
Data-Input setup time
tDS
1.5
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
1
-
ns
1
Address setup time
tAS
1.5
-
2
-
ns
1
Address hold time
tAH
0.8
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
1
-
ns
1
Command setup time
tCS
1.5
-
2
-
ns
1
Command hold time
tCH
0.8
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1.5
-
1
-
ns
CLK to data output
in high Z-time
CAS Latency = 3
tOHZ3
ns
5.4
CAS Latency = 2
tOHZ2
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.4/Nov. 01
7
HY5V66GF
AC CHARACTERISTICS I
-H
Parameter
-P
Symbol
Unit
Min
Max
Min
Max
Operation
tRC
65
-
70
-
ns
Auto Refresh
tRRC
65
-
70
-
ns
RAS to CAS Delay
tRCD
20
-
20
-
ns
RAS Active Time
tRAS
45
120K
50
120K
ns
RAS Precharge Time
tRP
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
15
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
1
-
1
-
CLK
Data-In to Active Command
tDAL
4
-
3
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
CLK
MRS to New Command
tMRD
1
-
1
-
CLK
CAS Latency = 3
tPROZ3
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
ms
Note
RAS Cycle Time
Precharge to Data
Output Hi-Z
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.4/Nov. 01
8
HY5V66GF
DEVICE OPERATING OPTION TABLE
HY5V66GF-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
HY5V66GF-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
Rev. 0.4/Nov. 01
9
HY5V66GF
COMMAND TRUTH TABLE
Command
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
L
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Burst-READ-SingleWRITE
H
X
L
L
Entry
H
L
L
H
Exit
L
H
H
X
L
H
H
L
X
L
V
X
X
V
X
H
X
X
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
H
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
power down
H
X
Precharge selected Bank
Entry
V
H
Precharge All Banks
X
X
Exit
Clock
Suspend
Note
V
CA
Read with Autoprecharge
Self Refresh1
BA
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.4/Nov. 01
10
HY5V66GF
PACKAGE INFORMATION
60 Ball FD-BGA Package
0.90±0.10
(PKG Hight)
9.10 REF
0.17±0.10
STAND OFF
0.15±0.05
1.
80
±
0.
10
0.15±0.05
Rev. 0.4/Nov. 01
@ 0.10 ⒨
0.
6
5
T
Y
P
3.
90
R
E
F
7
6
5
4
3
2
1
0.65TYP
1.
30
T
Y
P
2.
60
T
Y
P
11
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