Cypress BCM43143KMLGT Single-chip ieee 802.11b/g/n mac/phy/radio with usb/sdio host interface Datasheet

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Document Number: 002-15045 Rev. *D
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Revised July 1, 2016
Advance Data Sheet
BCM43143
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with
USB/SDIO Host Interface
GE NE R AL DE S C RI PT ION
F E A T U RE S
The BCM43143 is a single-band, single-stream, IEEE
802.11n compliant, MAC/PHY/Radio system-on-achip with internal 2.4 GHz Power Amplifier (PA) and
integrated T/R switch. The BCM43143 supports
internal RX diversity by providing two antenna ports.
The device enables development of USB or SDIO
802.11n WLAN clients that can take advantage of the
high throughput and extended range of Broadcom’s
second-generation solution. The BCM43143
maintains compatibility with legacy IEEE 802.11b/g
devices.
•
State-of-the-art security is provided by industry
standard support for WPA, WPA2 (802.11i), and
hardware-accelerated AES encryption/decryption,
coupled with TKIP, IEEE 802.1X support, and a
WLAN Authentication and Privacy Infrastructure
(WAPI) hardware engine.
Embedded hardware acceleration enables increased
system performance and reduced host-CPU
utilization in both client and access point
configurations. The BCM43143 also supports
Broadcom’s widely accepted and deployed WPS to
easily secure WLAN networks.
• SDIO and USB wireless client modules for digital
TVs, Blu-ray Disc® players, set-top boxes, game
consoles, and printers.
• Supports the I2S digital audio interface.
• Stand-alone wireless USB dongles and
multimedia streaming boxes.
F E A T U RE S
•
•
•
•
•
•
Supports 3.3V ±10% power supply input with high
efficiency Power Management Unit (PMU).
Programmable dynamic power management.
Eight GPIOs with multiplexed JTAG interface.
Complies with USB 2.0 specification and link
power management.
Supports standard SDIO v2.0 (50 MHz, 4-bit and
1-bit) and USB host interfaces.
20 MHz reference clock.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports USB 2.0, standard SDIO v2.0 (50 MHz,
4-bit and 1-bit) host interfaces.
Supports the I2S audio interface.
Greenfield, mixed mode, and legacy mode
support.
802.11n MPDU/MSDU aggregation support for
high throughput.
Full IEEE 802.11b/g legacy compatibility with
enhanced performance.
Supports Broadcom’s OneDriver™ software.
Supports drivers for Windows®, Linux®, and
Android™ operating systems.
Comprehensive wireless network security
support that includes WPA, WPA2, and AES
encryption/decryption, coupled with TKIP, IEEE
802.1X support, and a WAPI encryption/
decryption engine.
Single stream IEEE 802.11n support for 20 MHz
and 40 MHz channels provides PHY layer rates
up to 150 Mbps for typical upper-layer throughput
in excess of 90 Mbps.
Supports the IEEE 802.11n RX space-time block
coding (STBC) and low-density parity check
(LDPC) options for improved range and power
efficiency.
Supports an IEEE 802.15.2 external coexistence
interface to optimize bandwidth utilization with
other colocated wireless technologies such as
GPS, WiMAX, LTE, Bluetooth, and UWB.
Integrated ARM Cortex-M3 processor and onchip memory for complete WLAN subsystem
functionality, minimizing the need to wake up the
applications processor for standard WLAN
functions. This allows for further minimization of
power consumption while maintaining the ability
to field upgrade with future features. On-chip
memory includes 448 KB SRAM and 256 KB
ROM.
USB 2.0 with Link Power Management (LPM) for
low power standby application.
SDIO out of band low power application.
Integrated One Time Programmable (OTP)
memory to save configuration settings.
43143-DS104-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203
November 14, 2014
BCM43143 Advance Data Sheet
Revision History
F E A T U RE S
•
IEEE 802.11x Key Features:
• IEEE 802.11n compliant.
• 2.4 GHz internal PA.
• Internal T/R and RX diversity switches.
• Supports MCS 0–7 coding rates.
• Support for Short Guard Interval (SGI).
•
Single stream IEEE 802.11n support for 20 MHz
and 40 MHz channels provides PHY layer rates
up to 150 Mbps for typical upper-layer throughput
in excess of 90 Mbps.
Supports the IEEE 802.11n RX space-time block
coding (STBC) and low-density parity check
(LDPC) options for improved range and power
efficiency.
Package options:
• 7 mm × 7 mm, 56-pin QFN package.
Figure 1: BCM43143 High-Level Block Diagram
JTAG
JTAG
USB
USB 2.0
Device
SDIO or I2S
Interface
SDIO or
I2S
Interface
Internal Bus
BCM43143
IEEE
802.11n
MAC
GPIO
IEEE
802.11n
2.4 GHz
Radio
PA
2.4 GHz
RF Front
End
(switches)
Security
OTP
GPIO
IEEE
802.11n
PHY
(2 Kbits)
Serial
Flash
Interface
FLASH
Memory
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 2
BCM43143 Advance Data Sheet
Revision History
Revision History
Revision
Date
Change Description
43143-DS104-R
11/14/14
43143-DS103-R
02/24/14
43143-DS102-R
06/25/13
43143-DS101-R
06/03/13
Updated:
• Table 7: “Guaranteed Operating Conditions and DC Characteristics,” on
page 32.
• Table 8: “WLAN Current Consumption in SDIO Mode using
SR_VDDBAT5V,” on page 33.
• Table 9: “WLAN Current Consumption in USB mode using VDD33,” on
page 34.
Updated:
• “Reset and Low-Power Off Mode” on page 12
• Table 6: “Absolute Maximum Ratings,” on page 30
• Table 8: “WLAN Current Consumption in SDIO Mode using
SR_VDDBAT5V,” on page 32
• Table 9: “WLAN Current Consumption in USB mode using VDD33,” on page
33
• Table 16: “2.4 GHz Band Transmitter RF Specifications,” on page 40
• Section 14: “Thermal Information,” on page 53
Updated:
• Table 7 on page 34.
Added:
• Various features on cover, reorganized feature lists.
• “Link Power Management (LPM) Support” on page 16.
• “I2S Interface” on page 17.
• “Serial Flash Timing” on page 47.
• “I2S Slave Mode Tx Timing” on page 48.
43143-DS100-R
04/26/12
Updated:
• Figure 1 on page 2.
• Figure 3 on page 11.
• Figure 4 on page 13.
• Note in “Crystal Oscillator” on page 15.
• Figure 9 on page 24.
• Table 2 on page 25.
• Table 3 on page 26.
• Table 4 on page 28.
• Table 5 on page 32.
• Table 6 on page 33.
• Table 7 on page 34.
• Table 9 on page 36.
• Table 10 on page 37.
• Table 11 on page 39.
• Note in Section 14: “Thermal Information,” on page 56.
• Table 24 on page 56
Initial release.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 3
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2014 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the
EU. Any other trademarks or trade names mentioned are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,
intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,
pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES
THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL
WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT.
BCM43143 Advance Data Sheet
Table of Contents
Table of Contents
About This Document .................................................................................................................................. 9
Purpose and Audience ............................................................................................................................ 9
Acronyms and Abbreviations................................................................................................................... 9
Document Conventions ........................................................................................................................... 9
Technical Support ........................................................................................................................................ 9
Section 1: Introduction ..................................................................................................... 10
Section 2: Power Management and Resets .................................................................... 12
Power Management.................................................................................................................................... 12
Power Topology.......................................................................................................................................... 12
Reset and Low-Power Off Mode................................................................................................................ 13
Section 3: WLAN Global Functions ................................................................................. 14
GPIO Interface............................................................................................................................................. 14
OTP .............................................................................................................................................................. 14
JTAG Interface ............................................................................................................................................ 14
Crystal Oscillator........................................................................................................................................ 15
Section 4: WLAN USB 2.0 Host Interface ........................................................................ 16
Link Power Management (LPM) Support.................................................................................................. 17
I2S Interface................................................................................................................................................. 17
Section 5: SDIO Interface.................................................................................................. 18
Section 6: Wireless LAN MAC and PHY .......................................................................... 19
IEEE 802.11n MAC Description ................................................................................................................. 19
IEEE 802.11n PHY Description .................................................................................................................. 21
Single-Band Radio Transceiver ................................................................................................................ 22
Receiver Path........................................................................................................................................ 22
Transmitter Path.................................................................................................................................... 22
Calibration ............................................................................................................................................. 22
Section 7: Pin Assignments ............................................................................................. 23
56-Pin QFN Assignments........................................................................................................................... 23
56-Pin QFN Signals............................................................................................................................... 24
Pin Assignments by Pin Number.................................................................................................... 24
Pin Assignments by Pin Name....................................................................................................... 25
Section 8: Signal and Pin Descriptions........................................................................... 26
Package Signal Descriptions .................................................................................................................... 26
Strapping Options ...................................................................................................................................... 30
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 5
BCM43143 Advance Data Sheet
Table of Contents
Section 9: Electrical Characteristics ............................................................................... 31
Absolute Maximum Ratings ...................................................................................................................... 31
Recommended Operating Conditions and DC Characteristics ............................................................. 32
WLAN Current Consumption..................................................................................................................... 33
Section 10: Regulator Electrical Specifications ............................................................. 35
Core Buck Switching Regulator................................................................................................................ 35
CLDO ........................................................................................................................................................... 37
LNLDO ......................................................................................................................................................... 38
Section 11: WLAN Specifications .................................................................................... 39
2.4 GHz Band General RF Specifications................................................................................................. 39
2.4 GHz Band Receiver RF Specifications ............................................................................................... 39
2.4 GHz Band Transmitter RF Specifications .......................................................................................... 41
2.4 GHz Band Local Oscillator Specifications ......................................................................................... 42
Section 12: Antenna Specifications................................................................................. 43
Voltage Standing Wave Ratio.................................................................................................................... 43
Section 13: Timing Characteristics.................................................................................. 44
Power Sequence Timing ............................................................................................................................ 44
Serial Flash Timing..................................................................................................................................... 46
I2S Slave Mode Tx Timing.......................................................................................................................... 47
SDIO Default Mode Timing ........................................................................................................................ 49
SDIO High Speed Mode Timing................................................................................................................. 50
USB Parameters ......................................................................................................................................... 52
Section 14: Thermal Information...................................................................................... 54
Junction Temperature Estimation and PSIJT Versus ThetaJC................................................................ 54
Section 15: Package Information ..................................................................................... 55
Section 16: Ordering Information .................................................................................... 56
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 6
BCM43143 Advance Data Sheet
List of Figures
List of Figures
Figure 1: BCM43143 High-Level Block Diagram ............................................................................................... 2
Figure 2: BCM43143 System Diagram Showing Two Antennas and a Single Stream .................................... 10
Figure 3: BCM43143 Functional Block Diagram .............................................................................................. 11
Figure 4: Power Topology with the VDD33 (3.3V) Main Supply ...................................................................... 13
Figure 5: Recommended Oscillator Configuration ........................................................................................... 15
Figure 6: WLAN USB 2.0 Host Interface Block Diagram ................................................................................. 16
Figure 7: Enhanced MAC Block Diagram ........................................................................................................ 20
Figure 8: PHY Block Diagram .......................................................................................................................... 21
Figure 9: BCM43143 56-Pin QFN Package ..................................................................................................... 23
Figure 10: Power-Up Sequence Timing—3V Supply ...................................................................................... 44
Figure 11: Power-Up Sequence Timing—5V Supply with External DC-DC Conversion ................................. 45
Figure 12: Serial Flash Timing Diagram (STMicroelectronics-Compatible) ..................................................... 46
Figure 13: I2S Slave Mode Timing ................................................................................................................... 47
Figure 14: SDIO Bus Timing (Default Mode) ................................................................................................... 49
Figure 15: SDIO Bus Timing (High-Speed Mode)............................................................................................ 50
Figure 16: 7 mm × 7 mm, 56-pin QFN package............................................................................................... 55
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 7
BCM43143 Advance Data Sheet
List of Tables
List of Tables
Table 1: Crystal Oscillator Requirements ........................................................................................................ 15
Table 2: Pin Assignments by Pin Number ....................................................................................................... 24
Table 3: Pin Assignments by Signal Name ...................................................................................................... 25
Table 4: BCM43143 Signal Descriptions ......................................................................................................... 26
Table 5: Strapping Options .............................................................................................................................. 30
Table 6: Absolute Maximum Ratings ............................................................................................................... 31
Table 7: Guaranteed Operating Conditions and DC Characteristics ............................................................... 32
Table 8: WLAN Current Consumption in SDIO Mode using SR_VDDBAT5V ................................................. 33
Table 9: WLAN Current Consumption in USB mode using VDD33 ................................................................. 34
Table 10: Core Buck Switching Regulator (CBUCK) Specifications ................................................................ 35
Table 11: CLDO Specifications ........................................................................................................................ 37
Table 12: LNLDO Specifications ...................................................................................................................... 38
Table 13: 2.4 GHz Band General RF Specifications........................................................................................ 39
Table 14: 2.4 GHz Band Receiver RF Specifications ...................................................................................... 39
Table 15: 2.4 GHz Receiver Sensitivity ........................................................................................................... 40
Table 16: 2.4 GHz Band Transmitter RF Specifications .................................................................................. 41
Table 17: 2.4 GHz Band Local Oscillator Specifications.................................................................................. 42
Table 18: Power-Up Timing Parameters.......................................................................................................... 45
Table 19: Serial Flash Timing .......................................................................................................................... 46
Table 20: Timing for I2S Transmitters and Receivers...................................................................................... 47
Table 21: SDIO Bus Timing Parameters (Default Mode) ................................................................................. 49
Table 22: SDIO Bus Timing Parameters (High-Speed Mode) ......................................................................... 51
Table 23: USB Parameters .............................................................................................................................. 52
Table 24: 56-pin QFN Thermal Characteristics ............................................................................................... 54
Table 25: Ordering Information ........................................................................................................................ 56
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 8
About This Document
BCM43143 Advance Data Sheet
About This Document
Purpose and Audience
This document provides details of the functional, operational, and electrical characteristics of the Broadcom®
BCM43143. It is intended for hardware design, application, and OEM engineers.
Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and
other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php.
Document Conventions
The following conventions may be used in this document:
Convention
Description
Bold
User input and actions: for example, type exit, click OK, press Alt+C
Monospace
Code: #include <iostream>
HTML: <td rowspan = 3>
Command line commands and parameters: wl [-l] <command>
<>
Placeholders for required elements: enter your <username> or wl <command>
[]
Indicates optional command-line parameters: wl [-l]
Indicates bit and byte ranges (inclusive): [0:3] or [7:0]
Technical Support
Broadcom provides customer access to a wide range of information, including technical documentation,
schematic diagrams, product bill of materials, PCB layout information, and software updates through its
customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering
support representative.
In addition, Broadcom provides other product support through its Downloads & Support site
(http://www.broadcom.com/support/).
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 9
BCM43143 Advance Data Sheet
Introduction
Se c t i o n 1 : I n t ro d u c t i o n
The Broadcom® BCM43143 single-chip device provides the highest level of integration for wireless systems
with integrated IEEE 802.11b/g/n (MAC/PHY/radio). It provides a small form-factor solution with minimal
external components to drive down the cost for mass volumes and allows for wireless media client flexibility in
size, form, and function.
Figure 2: BCM43143 System Diagram Showing Two Antennas and a Single Stream
BCM43143
Host
I/F
IEEE
802.11n
MAC/PHY
IEEE 802.11n
2.4 GHz Radio
Transceiver
with integrated
PA
BCM43143
RF
TR and Rx
Diversity
Switches
RF
TR and Rx
Diversity
Switches
IEEE 802.11n
2.4 GHz Radio
Transceiver
with integrated
PA
IEEE
802.11n
MAC/PHY
Host
I/F
Employing a native 32-bit bus with a Direct Memory Access (DMA) architecture, the BCM43143 offers significant
performance improvements in both transfer rates and CPU utilization. Flexible support for a variety of system
bus interfaces is provided, including USB and SDIO devices.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 10
BCM43143 Advance Data Sheet
Introduction
Figure 3 shows a block diagram of the device.
Figure 3: BCM43143 Functional Block Diagram
BCM43143
USB20d
USB
Clock and Reset
MAXI
Host Interface
DFLL
(PL368/9 regs. ifc)
Xtal
SAXI
MAXI
PLL
SDIOd
XTAL
POR
EXTPOR_L
(inside USB)
AXI2APB 1
PLL
MAXI
(inside WL radio)
ClkRst
ChipCommon
OTP
(2 Kbits) DevID
BUCK
(inside PMU)
SAXI
pinmux
Power Topology
AXI
backplane
PL301
WDog timer
Digital
I/Os
ARM
CORTEX-M3
JTAG
MAXI
I2S
GPIO
SECI
RAM
ROM
(448 KB)
(256 KB)
CLDO
(inside PMU)
CLDO
SOCSRAM
SFLASH
(inside USB)
SAXI
(BT Coex)
mini PMU
(inside WL radio)
GSIO
(SPI2C)
UART
UART
WLAN 802.11bgn (1 × 1)
MAXI
JTAG
MAXI
JTAG_SEL
PMU Ctrl
SAXI
PMU
Broadcom®
November 14, 2014 • 43143-DS104-R
AXI2APB 0
(Core register ifc)
IEEE
802.11n
MAC
IEEE
802.11n
PHY
IEEE
802.11n
2.4 GHz
Radio
iTR
iPA
RF Ifc
iRD
RF_SWCTRL
pinmux
Digital
I/Os
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 11
BCM43143 Advance Data Sheet
Power Management and Resets
S e c t i o n 2 : P o w e r M a n a g e m e n t a n d R e s e ts
Power Management
The BCM43143 includes an internal Power Management Unit (PMU). The PMU takes care of powering up the
chip, and also enables and disables clocks based on clock requests sent from BCM43143 internal blocks.
Power Topology
The BCM43143 contains a high-efficiency power topology to convert input supply voltages to the supply
voltages required by the device’s internal blocks. A CBUCK switching regulator is used to convert the input
supply to 1.35V. Internal LDOs perform a low-noise conversion from 1.35V to 1.2V. As shown in Figure 4 on
page 13, the BCM43143 supports two power supply configurations:
•
A 3.3V power supply, connected to SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3.
•
A 5V power supply connected to SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3
connected to 3.3V. The latter can be obtained through a DC-DC conversion as shown in Figure 4 on page
13.
The default VDDIO supply of the BCM43143 is 3.3V. In SDIO mode, the BCM43143 supports an SDIO interface
specific voltage range of 1.8V to 3.3V. Refer to pin 46 description in Table 4 on page 26. All VDDIO pins other
than pin 46 remain at 3.3V as described in Table 4 on page 26.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 12
BCM43143 Advance Data Sheet
Reset and Low-Power Off Mode
Figure 4: Power Topology with the VDD33 (3.3V) Main Supply
GPIO
VDDIO
BCM43143
USB2.0
3.3V
LDO
USB_AVDD3P3
50 mA
2.5V
For 5 volts power
supplies only
WRF_PAD_VDD3P3
5V
VBUS
PA
WRF_PA_VDD3P3
D+
3.3V
BG
DGND
3.3V
5V
SR_VDDVBAT5V
mini
PMU
3.3V - 5V
Buck
1.2V
500mA
2.2 µH
Radio
1.35V
XTAL_VDD1P2
WRF_SYN_VDD1P2
LNLDO_VOUT1P2
1.35V
1 µF
SR_VLX
4.7 µF
PMU
LNDO_VDD1P5
1 µF
1 µF
1.35V
LDO_VDD1P5
Digital
Core
CLDO
150 mA
1.2V
VDDC
VOUT_CLDO
2.2 µF
Reset and Low-Power Off Mode
Full-chip reset is achieved by switching off the 3.3V VDDIO voltage to pins 1, 25, 37, and 53. This puts the chip
in reset and low-power off mode; in this mode the internal CBUCK switcher is shut down, bringing the total
typical current consumption down to less than 100 µA. The device must be kept in reset/low-power off mode for
at least 25 ms.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 13
BCM43143 Advance Data Sheet
WLAN Global Functions
Section 3: WLAN Global Functions
GPIO Interface
There are 19 General-Purpose I/O (GPIO) pins provided on the BCM43143. GPIOs 0–18 are multiplexed with
the JTAG, SDIO, I2S, SFlash, and Serial Enhanced Coexistence Interface (SECI) functions. These pins can be
used to interface to various external devices. Upon power-up and reset, these pins become tristated.
Subsequently, they can be programmed to be either input or output pins via the GPIO control register. A
programmable internal pull-up/pull-down resistor is included on each GPIO. If a GPIO output enable is not
asserted, and the corresponding GPIO signal is not being driven externally, the GPIO state is determined by its
programmable resistor.
OTP
The BCM43143 has 2 Kbits of on-chip One-Time Programmable (OTP) memory that can be used for nonvolatile storage of WLAN information such as a MAC address and other hardware-specific board and interface
configuration parameters.
JTAG Interface
The BCM43143 supports the IEEE 1149.1 JTAG boundary-scan standard for testing a packaged device on a
manufactured board. The JTAG interface is enabled by driving the JTAG_SEL pin high.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 14
BCM43143 Advance Data Sheet
Crystal Oscillator
Crystal Oscillator
Table 1 lists the requirements for the crystal oscillator.
Table 1: Crystal Oscillator Requirements
Parameter
Value
Frequency
20 MHz
Mode
AT cut, fundamental
Load capacitance
16 pF
ESR
50Ω maximum
Frequency stability
±10 ppm at 25°C
±10 ppm at 0°C to +85°C
Aging
±3 ppm/year maximum the first year, ±1 ppm thereafter
Drive level
300 µW maximum
Q-factor
40,000 minimum
Shunt capacitance
< 5 pF
Figure 5 shows the recommended oscillator configuration.
Figure 5: Recommended Oscillator Configuration
XTAL_OP_IN
27 pF
Crystal
20 MHz 10 ppm
XTAL_ON_OUT
Note: Refer to reference
schematics for designspecific details.
27 pF
220
Note: The component values referenced in Figure 5 are only recommended values and the correct
values will have to be characterized on a per board basis. Please see the reference board schematic
for the correct characterized values.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 15
BCM43143 Advance Data Sheet
WLAN USB 2.0 Host Interface
Section 4: WLAN USB 2.0 Host Interface
The BCM43143 USB interface can be set to operate as a USB 2.0 port. Features include the following:
•
A USB 2.0 protocol engine that supports the following:
– A Parallel Interface Engine (PIE) between packet buffers and USB transceiver
– Up to nine endpoints, including Configurable Control Endpoint 0
•
Separate endpoint packet buffers with a 512-byte FIFO buffer each
•
Host-to-device communication for bulk, control, and interrupt transfers
•
Configuration and status registers
Figure 6 shows the blocks in the device core.
Figure 6: WLAN USB 2.0 Host Interface Block Diagram
32-Bit On-Chip Communication System
DMA Engines
RX FIFO
TX FIFOs
Endpoint Management Unit
USB 2.0 Protocol Engine
USB 2.0 PHY
D+
D-
The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It
is primarily responsible for data transmission and recovery. On the transmit side, data is encoded, along with a
clock, using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data stream.
A SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery
circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered
data and clock are then shifted to the clock domain that is compatible with the internal bus logic.
The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces
between the packet buffers and the USB transceiver. It handles packet identification (PID), USB packets, and
transactions.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 16
BCM43143 Advance Data Sheet
Link Power Management (LPM) Support
The endpoint logic contains nine uniquely addressable endpoints. These endpoints are the source or sink of
communication flow between the host and the device. Endpoint zero is used as a default control port for both
the input and output directions. The USB system software uses this default control method to initialize and
configure the device information and allows USB status and control access. Endpoint zero is always accessible
after a device is attached, powered, and reset.
Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT
endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and
maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size
cannot be more than 512 bytes.
Link Power Management (LPM) Support
The USB 2.0 host interface supports a power management feature called Link Power Management (LPM) which
is similar to the existing suspend/resume, but has transitional latencies of tens of microseconds between power
states (instead of three to greater than 20 millisecond latencies of the USB 2.0 suspend/resume). LPM simply
adds a new feature and bus state that co-exists with the USB 2.0 defined suspend/resume.
I2S Interface
The I2S interface for audio supports slave mode transmit 2.1 or 5.1 channel operation. The I2S signals are:
•
I2S bit clock: I2S_BITCLK
•
I2S Word Select: I2S_WS
•
I2S Data Out: I2S_SDOUT
I2S_BITCLK and I2S_WS are inputs, while I2S_SDOUT is an output. Channel word lengths of 16 bits, 20 bits,
24 bits, and 32 bits are supported, and the data is justified so that the MSB of the left-channel data is aligned
with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit clock
cycle after the I2S_WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted
when I2S_WS is low, and right-channel data is transmitted when I2S_WS is high. An embedded 128 x 32 bits
single port SRAM for data processing enhances the performance of the interface.
The bit depth of I2S is 16, 20, 24, and 32.
Variable sampling rates are also supported:
•
8k, 12k, 16k, 24k, 32k, 48k, 96k with a 12.288 MHz master clock used by the external master receiver and/
or controller
•
22.05k, 44.1k, 88.2k with a 11.2896 MHz master clock used by the external master receiver and/or
controller
•
96k with a 24.567 MHz master clock used by the external master receiver and/or controller
The BCM43143 needs an external clock source input on the slave clock pin for the I2S interface. The slave clock
frequency is dependent upon the audio sample rate and the external I2S codec.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 17
BCM43143 Advance Data Sheet
SDIO Interface
Section 5: SDIO Interface
The SDIO interface is enabled by a strapping option (see Table 5 on page 30 for details). The BCM43143
supports all of the SDIO version 2.0 modes:
•
1-bit SDIO-SPI mode (25 Mbps)
•
1-bit SDIO-SD mode (25 Mbps)
•
4-bit SDIO-SD default speed mode (100 Mbps)
•
4-bit SDIO-SD high speed mode (200 Mbps).
The SDIO interface supports the full clock range from 0 to 50 MHz. The chip has the ability to stop the SDIO
clock between transactions to reduce power consumption. As an option, the GPIO_4 or the GPIO_16 pin can
be mapped to provide an SDIO Interrupt signal. This out-of-band interrupt is hardware generated and is always
valid (unlike the SDIO in-band interrupt, which is signalled only when data is not driven on SDIO lines). The
ability to force control of the gated clocks from within the WLAN chip is also provided. Three functions are
supported:
•
Function 0 standard SDIO function. Maximum BlockSize/ByteCount = 32 bytes.
•
Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. Maximum
BlockSize/ ByteCount = 64 bytes.
•
Function 2 WLAN function for efficient WLAN packet transfer through DMA. Maximum BlockSize/
ByteCount = 512 bytes.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 18
BCM43143 Advance Data Sheet
Wireless LAN MAC and PHY
S e c t i o n 6 : Wi r e l e s s L A N M A C a n d P H Y
IEEE 802.11n MAC Description
The IEEE 802.11n MAC features include:
•
Enhanced MAC for supporting 802.11n features
•
Programmable Access Point (AP) or Station (STA) functionality
•
Programmable mode selection as Independent Basic Service Set (IBSS) or infrastructure
•
Aggregated MAC Protocol Data Unit (MPDU) support for High Throughput (HT)
•
Passive scanning
•
Network Allocation Vector (NAV), Interframe Space (IFS), and Timing Synchronization Function (TSF)
functionality
•
RTS/CTS procedure support
•
Transmission of response frames (ACK/CTS)
•
Address filtering of receive frames as specified by IBSS rules
•
Multirate support
•
Programmable Target Beacon Transmission Time (TBTT), beacon transmission/cancellation, and
Announcement Traffic Indication Message (ATIM) window
•
Coordination Function (CF) conformance: Setting a NAV for neighborhood Point Coordination Function
(PCF) operation
•
Security through a variety of encryption schemes including WEP, TKIP, AES, WPA, WAP2, and
IEEE 802.1X
•
Power management
•
Statistics counters for MIB support
The MAC core supports the transmission and reception of packet sequences, together with related timing,
without any packet-by-packet driver interaction. Time-critical tasks requiring response times of only a few
milliseconds are handled in the MAC core. This achieves the required medium timing while minimizing driver
complexity. Also, the MAC driver processes incoming packets that have been buffered in the MAC core in bursts,
enabling high bandwidth performance.
The MAC driver interacts with the MAC core to prepare transmit packet queues and to analyze and forward
received packets to upper software layers. The internal blocks of the MAC core are connected to a
Programmable State Machine (PSM) through the host interface that connects to the internal bus (see Figure 7
on page 20).
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 19
BCM43143 Advance Data Sheet
IEEE 802.11n MAC Description
Figure 7: Enhanced MAC Block Diagram
Host Interface (Host Registers)
TX Status FIFO
Six TX FIFOs
Templates
Power
Management
Timing and
Control
RX FIFO
Wireless Security Engine
TX Engine
Code Memory
Programmable
State Machine
(PSM)
RX Engine
Data Memory
PHY Interface
The host interface consists of registers for controlling and monitoring the status of the MAC core and interfacing
with the TX/RX FIFOs. For transmission, 32 KB of FIFO buffering is available that can be dynamically allocated
to six transmit queues plus template space for beacons, ACKs, and probe responses. Whenever the host has
a frame to transmit, the host queues the frame into one of the transmit FIFOs with a TX descriptor containing
TX control information. The PSM schedules the transmission on the medium depending on the frame type,
transmission rules in the IEEE 802.11™ protocol, and the current medium occupancy scenario. After the
transmission completes, a TX status is returned to the host, informing the host of the transmission.
The MAC contains a 10 KB RX FIFO. Received frames are sent to the host along with RX descriptors that
contain additional frame reception information.
The power management block maintains power management state information of the core (and of the
associated STAs in the case of an AP) to help with dynamic frame transmission decisions by the core.
The wireless security engine performs the required encryption/decryption on the TX/RX frames. This block
supports separate transmit and receive keys with four shared keys and 50 link-specific keys. The link-specific
keys are used to establish a secure link between any two network nodes. The wireless security engine supports
the following encryption schemes that can be selected on a per-destination basis:
•
None: The wireless security engine acts as a pass-through
•
WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std. 802.11-2007
•
WEP128: 104-bit secure key and 24-bit IV
•
TKIP: IEEE Std. 802.11-2007
•
AES: IEEE Std. 802.11-2007
The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the
encryption engine and the addition of a CRC-32 Frame Check Sequence (FCS) as required by IEEE 802.112007. Similarly, the receive engine is responsible for byte flow from the PHY interface to the RX FIFO through
the decryption engine and for detection of errors in the RX frame.
The timing block performs the TSF, NAV, and IFS functionality as described in IEEE Std. 802.11-2007.
The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for
both transmission and reception. The PSM also maintains the statistics counters required for MIB support.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 20
BCM43143 Advance Data Sheet
IEEE 802.11n PHY Description
IEEE 802.11n PHY Description
The PHY supports:
•
Programmable data rates from MCS 0–7 in 20 MHz and 40 MHz channels, as specified in 802.11n.
•
Short Guard Interval (SGI) and optional reception of two space-time block encoded streams.
•
All scrambling, encoding, forward error correction, and modulation in the transmit direction, and inverse
operations in the receive direction.
•
Advanced digital signal processing technology for best-in-class receive sensitivity.
•
Both mixed-mode and optional greenfield preamble of 802.11n.
•
Both long and optional short IEEE 802.11b preambles.
•
Closed-Loop transmit power control.
•
Per-packet receive antenna diversity.
•
Automatic Gain Control (AGC).
•
Available per-packet channel quality and signal strength measurements.
The BCM43143 PHY provides baseband processing at all mandatory 802.11n data rates up to 150 Mbps, and
the legacy rates specified in IEEE 802.11b/g, including 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbps. This
core acts as an intermediary between the MAC and the 2.4 GHz radio, converting back and forth between
packets and baseband waveforms.
Figure 8: PHY Block Diagram
CCK/DSSS
Demodulate
Filters and
Radio Comp
AFE
and
Radio
Radio
Control
Block
Common Logic
Block
Frequency and
Timing Synch
Carrier Sense,
AGC, and Rx
FSM
Tx FSM
OFDM
Demodulate
Viterbi
Decoder
Descramble
and Deframe
Buffers
MAC
Interface
FFT/IFFT
Modulation
and Coding
Frame and
Scramble
Filters and
Radio Comp
PA Comp
Modulate and
Spread
COEX
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 21
BCM43143 Advance Data Sheet
Single-Band Radio Transceiver
Single-Band Radio Transceiver
The BCM43143 has a 2.4 GHz radio transceiver that ensures low power consumption and robust
communication in 20 MHz and 40 MHz channel bandwidths as specified in IEEE 802.11n.
Receiver Path
The BCM43143 has a wide dynamic range, direct conversion receiver. It employs high-order, on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The excellent noise figure of the receiver
makes an external LNA unnecessary.
Transmitter Path
Baseband data is modulated and upconverted to the 2.4 GHz ISM band. Linear on-chip power amplifiers are
included, which are capable of delivering a nominal output power exceeding +15 dBm while meeting the IEEE
802.11n specification. The TX gain has 128 steps of 0.25 dB per step.
Calibration
The BCM43143 features dynamic on-chip calibration, eliminating process variation across components. This
enables the device to be used in high-volume applications because calibration routines are not required during
manufacturing. These calibration routines are performed periodically in the course of normal radio operation.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 22
BCM43143 Advance Data Sheet
Pin Assignments
S e c t i o n 7 : P i n A s s i g n m e n ts
56-Pin QFN Assignments
The 56-pin QFN package pin assignments are shown in Figure 9.
VD
DC
GP
IO
GP 18
IO
VD 17
DI
GS O
IO
SF _CS
LA N
SD SH_
IO CS
S D _ DA N
IO TA
S D _ DA 0
IO T A
SD _CL 1
IO K
VD _CM
DI D
SD O
IO
S D _ DA
IO T A
VD _DA 2
DC T A
3
Figure 9: BCM43143 56-Pin QFN Package
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VDDIO
1
42 USB_RREF
UART_RX
2
41 USB_MONPLL
UART_TX
3
40 USB_AVDD3P3
WRF_PAD_VDD3P3
4
39 USB_DM
NC
5
38 USB_DP
WRF_PA_VDD3P3
6
37 VDDIO
WRF_OUT_IN1
7
NC
8
WRF_RFIN2
9
36 SFLASH_SO|GSIO_SDO
BCM43143
7 X 7 QFN
35 SFLASH_CLK|GSIO_SCLK
34 SFLASH_SI|GSIO_SDI
WRF_GPIOOUT 10
33 VDDC
LNLDO_VDD1P5 11
32 LDO_VDD1P5
LNLDO_VDD1P5 12
31 VOUT_CLDO
LNLDO_VDD1P5 13
30 SR_VDDBAT5V
LNLDO_VDD1P5 14
29 SR_VLX
15 16 17 18 19 20 21 22 23 24 25 26 27 28
5
IO
GP 4
IO
GP 3
IO
GP O
DI
VD 2
IO
GP 1
IO
GP 0
IO
GP
DC L
VD _SE UT
O
AG _
JT ON
_ N
AL _I
XT _OP P2 2
1
AL D 1P
XT _VD DD
AL _V P2
XT SYN UT1
_
R F VO
W O_
LD
LN
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 23
BCM43143 Advance Data Sheet
56-Pin QFN Assignments
56-Pin QFN Signals
Pin Assignments by Pin Number
Table 2: Pin Assignments by Pin Number
Pin
Signal Name
Pin
Signal Name
1
VDDIO
29
SR_VLX
2
UART_RX
30
SR_VDDBAT5V
3
UART_TX
31
VOUT_CLDO
4
WRF_PAD_VDD3P3
32
LDO_VDD1P5
5
GND
33
VDDC
6
WRF_PA_VDD3P3
34
SFLASH_SI|GSIO_SDI
7
WRF_OUT_IN1
35
SFLASH_CLK|GSIO_SCLK
8
GND
36
SFLASH_SO|GSIO_SDO
9
WRF_RFIN2
37
VDDIO
10
WRF_GPIOOUT
38
USB_DP
11
LNLDO_VDD1P5
39
USB_DM
12
LNLDO_VDD1P5
40
USB_AVDD3P3
13
LNLDO_VDD1P5
41
USB_MONPLL
14
LNLDO_VDD1P5
42
USB_RREF
15
LNLDO_VOUT1P2
43
VDDC
16
WRF_SYN_VDD1P2
44
SDIO_DATA3
17
XTAL_VDD1P2
45
SDIO_DATA2
18
XTAL_OP_IN
46
VDDIO
19
XTAL_ON_OUT
47
SDIO_CMD
20
JTAG_SEL
48
SDIO_CLK
21
VDDC
49
SDIO_DATA1
22
GPIO0
50
SDIO_DATA0
23
GPIO1
51
SFLASH_CSN
24
GPIO2
52
GSIO_CSN
25
VDDIO
53
VDDIO
26
GPIO3
54
GPIO17
27
GPIO4
55
GPIO18
28
GPIO5
56
VDDC
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 24
BCM43143 Advance Data Sheet
56-Pin QFN Assignments
Pin Assignments by Pin Name
Table 3: Pin Assignments by Signal Name
Signal Name
Pin
Signal Name
Pin
GPIO0
22
SR_VLX
29
GPIO1
23
UART_RX
2
GPIO2
24
UART_TX
3
GPIO3
26
USB_AVDD3P3
40
GPIO4
27
USB_DM
39
GPIO5
28
USB_DP
38
GPIO17
54
USB_MONPLL
41
GPIO18
55
USB_RREF
42
GSIO_CSN
52
VDDC
21
JTAG_SEL
20
VDDC
33
LDO_VDD1P5
32
VDDC
43
LNLDO_VDD1P5
11
VDDC
56
LNLDO_VDD1P5
12
VDDIO
1
LNLDO_VDD1P5
13
VDDIO
25
LNLDO_VDD1P5
14
VDDIO
37
LNLDO_VOUT1P2
15
VDDIO
46
GND
5
VDDIO
53
GND
8
VOUT_CLDO
31
SDIO_CLK
48
WRF_GPIOOUT
10
SDIO_CMD
47
WRF_OUT_IN1
7
SDIO_DATA0
50
WRF_PA_VDD3P3
6
SDIO_DATA1
49
WRF_PAD_VDD3P3
4
SDIO_DATA2
45
WRF_RFIN2
9
SDIO_DATA3
44
WRF_SYN_VDD1P2
16
SFLASH_CLK|GSIO_SCLK
35
XTAL_ON_OUT
19
SFLASH_CSN
51
XTAL_OP_IN
18
SFLASH_SI|GSIO_SDI
34
XTAL_VDD1P2
17
SFLASH_SO|GSIO_SDO
36
SR_VDDBAT5V
30
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 25
BCM43143 Advance Data Sheet
Signal and Pin Descriptions
S e c t i o n 8 : Si g n a l a n d Pi n D e s c ri p t i o n s
Package Signal Descriptions
The signal name, type, and description of each pin in the BCM43143 56-pin QFN package is listed in Table 4.
The symbols shown in the Type column indicate pin directions (I/O = bidirectional, I = input, O = output, and OD
= open drain output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and
PD = weak internal pull-down resistor), if any. Resistor strapping options are defined in Table 5 on page 30.
Table 4: BCM43143 Signal Descriptions
Pin
Signal
Type
Description
SDIO Bus Interface
48
SDIO_CLK
I/O
SDIO clock
When not used as SDIO this is a general purpose GPIO pin
(GPIO12) or an I2S Audio Interface signal (I2S_WS)
47
SDIO_CMD
I/O
SDIO bus command line
When not used as SDIO this is a general purpose GPIO pin
(GPIO11) or an I2S Audio Interface signal (I2S_BITCLK)
50
SDIO_DATA0
I/O
SDIO data line 0
When not used as SDIO this is a general purpose GPIO pin
(GPIO14)
49
SDIO_DATA1
I/O
SDIO data line 1
When not used as SDIO this is a general purpose GPIO pin
(GPIO13) or an I2S Audio Interface signal (I2S_SDOUT)
45
SDIO_DATA2
I/O
SDIO data line 2
When not used as SDIO this is a general purpose GPIO pin
(GPIO10)
44
SDIO_DATA3
I/O
SDIO data line 3
When not used as SDIO this is a general purpose GPIO pin
(GPIO9)
USB Interface
39
USB_DM
I/O
USB data negative
38
USB_DP
I/O
USB data positive
41
USB_MONPLL
–
USB reserved pin for Diagnostic purposes only
42
USB_RREF
–
USB bandgap reference resistor/capacitor, tie this pin in parallel
through a 100 pF capacitor and a 4 kΩ resistor to ground
WLAN RF Signal Interface
7
WRF_OUT_IN1
I/O
2.4 GHz RF output, 2.4 GHz RF input 1
9
WRF_RFIN2
I
2.4 GHz RF input 2
10
WRF_GPIOOUT
O
WLAN reference output.
Connect to ground through a 15 kΩ, 1% resistor.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 26
BCM43143 Advance Data Sheet
Package Signal Descriptions
Table 4: BCM43143 Signal Descriptions (Cont.)
Pin
Signal
Type
Description
I2S Audio Interface
47
I2S_BITCLK
I/O
I2S serial bit clock, only available when no SDIO I/F
48
I2S_WS
I/O
I2S word select, only available when no SDIO I/F
49
I2S_SDOUT
I/O
I2S serial data out, only available when no SDIO I/F
Serial Flash Interface and SPI/BSC Interface
51
SFLASH_CSN
34
SFLASH_SI GSIO_SDI I/O
This pin is muxed with:
• Serial flash data in
• SPI/BSC data in
When not used as SFLASH or GSIO this is a general purpose
GPIO pin (GPIO6)
36
SFLASH_SO
GSIO_SDO
I/O
This pin is muxed with:
• Serial flash data out
• SPI/BSC data out
When not used as SFLASH or GSIO this is a general purpose
GPIO pin (GPIO8)
35
SFLASH_CLK
GSIO_SCLK
I/O
This pin is muxed with:
• Serial flash clock
• SPI/BSC clock
When not used as SFLASH or GSIO this is a general purpose
GPIO pin (GPIO7)
52
GSIO_CSN
I/O
SPI/BSC chip select.
When not used as GSIO this is a general purpose GPIO pin
(GPIO16).
Broadcom®
November 14, 2014 • 43143-DS104-R
I/O
Serial flash chip select.
When not used as SFLASH, this is a general purpose GPIO pin
(GPIO15)
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 27
BCM43143 Advance Data Sheet
Package Signal Descriptions
Table 4: BCM43143 Signal Descriptions (Cont.)
Pin
Signal
Type
Description
GPIO Pins
22
GPIO0
TDI
BTCX_RF_ACTIVE
SECI_IN0
I/O
This pin is muxed with:
• GPIO0, a general purpose I/O pin
• JTAG test data in
• Legacy BT coexistence RF Active
• SECI in0
23
GPIO1
TDO
BTCX_TX_CONF
SECI_OUT
I/O
This pin is muxed with:
• GPIO1, a general purpose I/O pin
• JTAG test data out
• Legacy BT coexistence TX Conf
• SECI out
24
GPIO2
TCK
BTCX_STATUS
SECI_AUX0
I/O
This pin is muxed with:
• GPIO2, a general purpose I/O pin
• JTAG test clock
• Legacy BT coexistence Status
• SECI aux0
26
GPIO3
TRST-L
BTCX_PRISEL
SECI_IN1
I/O
This pin is muxed with:
• GPIO3, a general purpose I/O pin
• JTAG test reset low
• Legacy BT coexistence Priority Select
• SECI in1
27
GPIO4
TMS
BTCX_FREQ
I/O
This pin is muxed with:
• GPIO4, a general purpose I/O pin
• JTAG test mode select
• Legacy BT coexistence FREQ
28
GPIO5
EXTPOR_L
I/O (PU) This pin is muxed with:
• GPIO5, a general purpose I/O pin
• External power-on reset low, when JTAG_SEL high
54
GPIO17
I/O (PD) General purpose I/O pin
55
GPIO18
I/O (PD) General purpose I/O pin
UART Interface
2
UART_RX
I/O (PD) UART receive data (SW debug)
3
UART_TX
I/O (PU) UART transmit data (SW debug)
Crystal Oscillator
19
XTAL_ON_OUT
O
XTAL oscillator output.
Connect a 20 MHz, 10 ppm crystal between the XTAL_ON_OUT
and XTAL_OP_IN pins
18
XTAL_OP_IN
I
XTAL oscillator input
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 28
BCM43143 Advance Data Sheet
Package Signal Descriptions
Table 4: BCM43143 Signal Descriptions (Cont.)
Pin
Signal
Type
Description
I (PD)
JTAG select
Test Pins
20
JTAG_SEL
Strap Pins
2
UART_RX
I/O (PD) Strap RemapToROM[1]
3
UART_TX
I/O (PU) Strap RemapToROM[0]
34
SFLASH_SI
I/O (PD) Strap SDIOHighDrive
54
GPIO17
I/O (PD) Strap SDIOEnabled
55
GPIO18
I/O (PD) Strap SDIOIso
Integrated Voltage Regulators
11, 12,
13, 14
LNLDO_VDD1P5
PWR
LNLDO 1.5V input
15
LNLDO_VOUT1P2
PWR
LNLDO 1.2V output
30
SR_VDDBAT5V
PWR
VBAT power input
29
SR_VLX
PWR
CBUCK switching regulator output
31
VOUT_CLDO
PWR
Output of core LDO
32
LDO_VDD1P5
PWR
Input of core LDO
WLAN Power Supplies
40
USB_AVDD3P3
PWR
USB 3.3V input
16
WRF_SYN_VDD1P2
PWR
RF synthesizer VDD 1.2V input
6
WRF_PA_VDD3P3
PWR
WLAN PA 3.3V supply
4
WRF_PAD_VDD3P3
PWR
WLAN PA driver 3.3V supply
17
XTAL_VDD1P2
PWR
XTAL oscillator 1.2V supply
Miscellaneous Power Supplies and Ground
21, 33,
43, 56
VDDC
PWR
Core supply for WLAN
1, 25, 37, VDDIO
53
PWR
I/O supply for pads (3.3V)
46
VDDIO
PWR
I/O supply for SDIO pads (1.8V to 3.3V). Can only be 3.3V when
USB is used.
H
GND_SLUG
GND
Ground
5, 8
GND
GND
Ground
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 29
BCM43143 Advance Data Sheet
Strapping Options
Strapping Options
The pins listed in Table 5 are sampled at Power-On Reset (POR) to determine the various operating modes.
Sampling occurs within a few milliseconds following internal POR or deassertion of external POR. After POR,
each pin assumes the function specified in the signal descriptions table. Each pin has an internal pull-up (PU)
or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU
resistor to VDDIO or a PD resistor to GND (use 10 kΩ or less)1.
Table 5: Strapping Options
Signal Name Mode
Default
Description
[UART_RX,
UART_TX]
RemapToROM[1:0] [PD,PU] 00 = Boot from SRAM, ARMCM3 in reset, no SFLASH
connected
01 = Boot from ROM, no SFLASH connected (default)
10 = Boot from SFLASH
11 = Invalid
GPIO17
SDIOEnabled
PD
0 = USB Enabled, SDIO pins can be GPIO or I2S (default)
1 = SDIO Enabled
GPIO18
SDIOIso
PD
0 = SDIO pads are not in Isolation mode (default)
1 = Keep SDIO pads in Isolation mode
SFLASH_SI
SDIOHighDrive
PD
0 = SDIO pins drive strength set by SDIOd core or PMU Chip
Control (= default)
1 = SDIO pins drive strength set by SDIOd core to either 12 mA
or 16 mA
1. BCM43143 reference board schematics can be obtained through your Broadcom representative.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 30
BCM43143 Advance Data Sheet
Electrical Characteristics
S e c t i o n 9 : E l e c t r i c a l C h a ra c t e r i s t i c s
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
Absolute Maximum Ratings
Caution! These specifications indicate levels where permanent damage to the device can occur.
Functional operation is not guaranteed under these conditions. Operation at absolute maximum
conditions for extended periods can adversely affect the long-term reliability of the device.
Table 6: Absolute Maximum Ratings
Rating
Symbol
Minimum
Maximum
Unit
DC supply for CBUCK switching regulator
SR_VDDBAT5V
–0.5
5.5
V
DC supply voltage for the WL PA/PA driver
WRF_PA_VDD3P3,
WRF_PAD_VDD3P3
–0.5
3.8
V
DC supply voltage for I/O
VDDIO
–0.5
3.8
V
DC supply voltage for the BCM43143 core
VDDC
–0.5
1.32
V
DC supply voltage for BCM43143 RF blocks
WRF_SYN_VDD1P2,
XTAL_VDD1P2
–0.5
1.32
V
DC input supply voltage for CLDO and LNLDO
LDO_VDD1P5,
LNLDO_VDD1P5
–0.5
2.1
V
Maximum junction temperature
TJ_MAX
–
125
°C
Operating humidity
–
–
85
%
Ambient operating temperature
–
Storage temperature
–
65
a
°C
TSTG
–40
125
°C
Storage humidity
–
–
60
%
ESD protection (HBM)
VESD
–
2000
V
a. On a 1s1P JEDEC board, not exceeding TJ_MAX, see Section 14: “Thermal Information,” on page 54.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 31
BCM43143 Advance Data Sheet
Recommended Operating Conditions and DC Characteristics
Recommended Operating Conditions and DC Characteristics
Table 7: Guaranteed Operating Conditions and DC Characteristics
Value
Element
Parameter
Minimum
Typical
Maximum
Unit
DC supply for CBUCK switching
regulator
SR_VDDBAT5V
2.3
3.6
5.25
V
DC supply voltage for WL PA/PA driver WRF_PA_VDD3P3,
WRF_PAD_VDD3P3
2.97
3.3
3.63
V
DC supply voltage for core
VDDC
1.14
1.2
1.26
V
DC supply voltage for RF blocks in
chip
VDDRF
1.14
1.2
1.26
V
VIH
0.625 × VDDIO –
–
V
0.25 × VDDIO V
SDIO Interface I/O Pinsa
Input high voltage
Input low voltage
VIL
–
Output high voltage @ 2 mA
VOH
0.75 × VDDIO –
–
V
Output low voltage @ 2 mA
VOL
–
–
0.125 ×
VDDIO
V
Input low voltage
VIL
–
–
0.8
V
Input high voltage
VIH
2.0
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.4
V
Output high voltage @ 2 mA
VOH
VDDIO – 0.4V –
–
V
Input low voltage
VIL
–
–
0.8
V
Input high voltage
VIH
2.0
–
–
V
–
–
Other Digital I/O Pins
RF Switch Control I/O Pins
Output low voltage @ 2 mA
VOL
–
0.4
V
Output high voltage @ 2 mA
VOH
VDDIO – 0.4V –
–
V
Input capacitance
Cin
–
5
pf
–
a. VDDIO voltage tolerance is ±10%; for SDIO 1.8V levels (VDDIO at pin 46 = 1.8V ±10%), the maximum SDIO
clock frequency should be limited to 25 MHz in high-speed mode only.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 32
BCM43143 Advance Data Sheet
WLAN Current Consumption
WLAN Current Consumption
The WLAN current consumption measurements are shown in Table 8 through Table 9 on page 34.
Table 8: WLAN Current Consumption in SDIO Mode using SR_VDDBAT5Va
VDDIO SR_VDDBAT5V
Host Interface SDIO
WRF_PA_VDD3P3 WRF_PAD_VDD3P3 USB_AVDD3P3
I_Total P_Total
mA
mW
OFF (Low power off
mode: VDDIO
switched off)
0
0.07
0
0
0
0.07
0.2
Sleepb
1
2
0
1
1
<5
< 17
Power savec
1
3
0
1
1
<6
< 20
RX (Listen), 2.4 GHz
HT 20d
1
40
0
1
0
42
139
RX (Active), 2.4 GHz
HT 20e,f
2
65
0
1
0
68
224
TX CCK (20 dBm @
Chip port, 2.4 GHz HT
20)g
1
56
329
30
0
416
1373
TX OFDM, 54 Mbps (–
20 dBm @ Chip port,
2.4 GHz HT 20)g
2
58
295
30
0
385
1265
TX MCS7 (18 dBm @
Chip port, 2.4 GHz
HT20)g
2
72
249
24
0
347
1145
TX MCS7 (18 dBm @
Chip port, 2.4 GHz
HT40)g
2
78
272
25
0
377
1244
a. Typical numbers, measured at 3.3V, 25°C.
b. Inter-beacon sleep.
c. Beacon interval = 102.4 ms, DTIM = 3, Beacon duration = 1 ms @ 1 Mbps.
Integrated sleep + wake up + Beacon RX current over 3 DTIM intervals.
d. Carrier sense (CCA) when no carrier present.
e. Carrier sense (CS) detect/packet RX.
f. Applicable to all supported rates.
g. Duty cycle is 100%.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 33
BCM43143 Advance Data Sheet
WLAN Current Consumption
Table 9: WLAN Current Consumption in USB mode using VDD33a
VDDIO SR_VDDBAT5V
Host Interface USB
WRF_PA_VDD3P3 WRF_PAD_VDD3P3 USB_AVDD3P3
I_Total
mA
P_Total
mW
0
0.07
0
0
0
0.07
0.2
Sleepb
0.4
2
0
1
5.6
<9
< 30
Power savec
0.4
3
0
1
5.6
< 10
< 33
RX (Listen), 2.4 GHz
HT 20d
0.4
45
0
1
22
68
226
RX (Active), 2.4 GHz
HT 20e,f
0.4
70
0
1
23
94
312
TX CCK (20 dBm @
Chip port, 2.4 GHz HT
20)g
0.5
55
320
30
21
427
1407
TX OFDM, 54 Mbps
(–20 dBm @ Chip
port,
2.4 GHz HT 20)g
0.4
59
265
30
21
376
1239
TX MCS7 (18 dBm @
Chip port, 2.4 GHz
HT20)g
0.6
74
248
24
21
368
1213
TX MCS7 (18 dBm @
Chip port, 2.4 GHz
HT40)g
1.6
80
272
25
21
400
1319
OFF (Low power off
mode: VDDIO
switched off)
a. Typical numbers, measured at 3.3V, 25°C.
b. Inter-beacon sleep.
c. Beacon interval = 102.4 ms, DTIM = 3, Beacon duration = 1 ms @ 1 Mbps.
Integrated sleep + wake up + Beacon RX current over 3 DTIM intervals.
d. Carrier sense (CCA) when no carrier present.
e. Carrier sense (CS) detect/packet RX.
f. Applicable to all supported rates.
g. Duty cycle is 100%.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 34
BCM43143 Advance Data Sheet
Regulator Electrical Specifications
Section 10: Regulator Electrical
Sp e c i f ic a t i o n s
Note: Values in this data sheet are design goals and are subject to change based on the results of
device characterization.
Functional operation is not guaranteed outside of the specification limits provided in this section.
Core Buck Switching Regulator
Table 10: Core Buck Switching Regulator (CBUCK) Specifications
Specification
Notes
Min
Typ
Max
Units
Input supply voltage (DC)
DC voltage range inclusive of
disturbances.
2.3
3.6
5.25
V
Input supply voltage (spikes)
Up to 10 seconds cumulative duration
over 7 years lifetime.
10 ms maximum pulse width.
–
–
5.5
V
PWM mode switching frequency CCM:
Load > 100 mA
SR_VDDBAT5V = 3.6V
2
4
6
MHz
PWM output current
–
–
500a
mA
–
Output current limit
–
–
1390
–
mA
Output voltage range
Programmable, 30 mV steps
Default = 1.35V
1.2
1.35
1.5
V
PWM output voltage
DC accuracy
Includes load and line regulation.
Forced PWM mode
–4
–
4
%
PWM ripple voltage, static
Measure with 20 MHz bandwidth limit.
–
7
20
mVpp
PWM mode peak efficiency
Peak Efficiency at 200 mA load
78
84
–
%
PFM mode efficiency
5 mA load current
–
65
–
%
Low Power Operating mode
(LPOM) efficiency
5 mA load current
–
80
–
%
Start-up time from power down
VDDIO already ON and steady.
Time from REG_ON rising edge to
CLDO reaching 1.2V
–
–
850
µs
External inductor
0603 size, ±30%, 0.26 ±25% ohms
1.2
2.2
3.3
µH
External output capacitor
Ceramic, X5R, 0402,
ESR <30mΩ at 4 MHz, ±20%,
6.3V
4.7
10
µF
Broadcom®
November 14, 2014 • 43143-DS104-R
b
2.53
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 35
BCM43143 Advance Data Sheet
Core Buck Switching Regulator
Table 10: Core Buck Switching Regulator (CBUCK) Specifications (Cont.)
Specification
Notes
Min
Typ
Max
Units
External input capacitor
For SR_VDDBATP5V pin,
Ceramic, X5R, 0603,
ESR < 30 mΩ at 4 MHz, ± 20%,
6.3V,
4.7 μF
0.76b
4.7
–
µF
Operating junction temperature –
–40
50
125
°C
Input supply voltage ramp-up
time
40
–
–
µs
0 to 4.3V
a. 500 mA TT junction temp 110°C. Derate to 372 mA for Tj > 125°C.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part
tolerance, DC-bias, temperature, and aging.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 36
BCM43143 Advance Data Sheet
CLDO
CLDO
Table 11: CLDO Specifications
Specification
Notes
Min
Typ
Max
Units
Input supply voltage (Vin)
Min = 1.2 + 0.1V = 1.3V
Dropout voltage requirement must be met
under maximum load.
1.2
1.35
1.5
V
Output currenta
–
–
–
150
mA
Output voltage (Vo)
Programmable in 25 mV steps.
Default = 1.2V
1.1
1.2
1.275 V
Dropout voltage
At max load
–
–
100
mV
Output voltage DC accuracy
Includes line/load regulation
–4
–
+4
%
Quiescent current
No load
–
10
–
µA
Line regulation
Vin from (Vo + 0.1V) to 1.5V, maximum load –
–
+1.1
%Vo/V
Load regulation
Load from 1 mA to 150 mA
–
–
0.02
%Vo/mA
currentb
Power-down
–
–
10
µA
Power supply rejection ratio
(PSRR)
@1 kHz
Vin ≥ 1.35V
Co = 2.2 µF
20
–
–
dB
PMU start-up time
SR_VDDBAT5V up and stable. Time from the –
VDDIO rising edge to the CLDO reaching
1.2V.
–
850
µs
LDO turn-on time
LDO turn-on time when rest of the chip is up –
–
180
µs
In-rush current during turn-on
Measured when the output capacitor is fully –
discharged.
–
150
mA
External output capacitor, Co
Total ESR: 30–200 mΩ
–
µF
External input capacitor
Only use an external input capacitor at the –
VDD_LDO pin if it is not supplied from
CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ
1
2.2
µF
Operating temperature
Junction temperature
50
125
°C
Leakage
1.67c 1
–40
a. Output current is measured at 125°C junction temperature.
b. Leakage current is measured by 85°C junction temperature.
c. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part
tolerance, DC-bias, temperature, and aging.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 37
BCM43143 Advance Data Sheet
LNLDO
LNLDO
Table 12: LNLDO Specifications
Specification
Notes
Min
Typ
Max
Units
Input supply voltage (Vin)
Min = 1.2Vo + 0.1V = 1.3V
1.3
1.35
1.5
V
Dropout voltage requirement must be met
under maximum load.
Output Current
–
–
–
100
mA
Output voltage (Vo)
Programmable in 25 mV steps.
Default = 1.2V
1.1
1.2
1.275
V
Dropout Voltage
At maximum load
–
–
100
mV
Output voltage DC accuracy includes line/load regulation
–4
–
+4
%
Quiescent current
No load
–
44
–
µA
Line regulation
Vin from (Vo + 0.1V) to 1.5V,
maximum load
–0.3
–
+0.3
%Vo/V
Load regulation
Load from 1 mA to 300 mA
–
0.02
0.05
%Vo/mA
Transient undershoot
–
–
–
TBD
mV
Transient overshoot
–
–
–
TBD
mV
Leakage current
Power-down
–
–
10
µA
Output noise
@30 kHz, 60 mA load Co = 1 µF
–
–
60
30
nV/rt Hz
nV/rt Hz
@100 kHz, 60 mA load Co = 1 µF
PSRR
@ 1kHz, Input > 1.3V, Co= 1 µF, Vo = 1.2V 20
–
–
dB
PMU start-up time
From power-down
–
–
850
µs
LDO Turn-on Time
LDO turn-on time when rest of chip is up
–
–
180
µs
In-rush current during turnon
Measured when the output capacitor is fully –
discharged.
–
150
mA
External output capacitor
(Co)
Total ESR (trace/capacitor): 30 mΩ–200
mΩ
1
2.2
µF
External input capacitor
Only use an external input capacitor at the –
VDD_LDO pin if it is not supplied from
CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–
200 mΩ
1
2.2
µF
Operating temperature
Junction temperature
50
125
°C
0.74a
–40
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part
tolerance, DC-bias, temperature, and aging.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 38
BCM43143 Advance Data Sheet
WLAN Specifications
S e c t i o n 11 : W L A N Sp e c i f i c a t i o n s
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
2.4 GHz Band General RF Specifications
Table 13: 2.4 GHz Band General RF Specifications
Item
Condition
Minimum Typical
Maximum
Unit
TX/RX switch time
Including TX ramp down –
5
10
μs
RX/TX switch time
Including TX ramp up
5
5
μs
–
2.4 GHz Band Receiver RF Specifications
The receiver specifications including sensitivity are shown in Table 14 and Table 15 on page 40.
Table 14: 2.4 GHz Band Receiver RF Specifications
Characteristic
Condition
Minimum Typical
Maximum
Unit
Cascaded noise figure
–
–
4
–
dB
Maximum receive levela
@ 1, 2 Mbps
–4
–
–
dBm
@ 5.5, 11 Mbps
–10
–
–
dBm
@ 54 Mbps
–10
–
–
dBm
Adjacent channel power rejection
• DSSS at 11 Mbpsb
RX = –70 dBm
35
–
–
dB
Return loss
Zo = 50Ω, across
dynamic range
TBD
TBD
TBD
dB
Maximum receiver gain
–
–
>90
–
dB
a. When using a suitable external RF switch.
b. Difference between interfering and desired signal (>25 MHz apart) at 8% PER for 1024-octet Physical-Layer
Service Data Units (PSDUs) with desired signal level as specified.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 39
BCM43143 Advance Data Sheet
2.4 GHz Band Receiver RF Specifications
Table 15: 2.4 GHz Receiver Sensitivity
Rate/Modulation
Typical Receive Sensitivitya b(dBm)
1 Mbps DSSS
–97
2 Mbps DSSS
–95
5.5 Mbps CCK
–91
11 Mbps CCK
–89
6 Mbps OFDM
–91
9 Mbps OFDM
–90
12 Mbps OFDM
–88
18 Mbps OFDM
–86
24 Mbps OFDM
–84
36 Mbps OFDM
–81
48 Mbps OFDM
–78
54 Mbps OFDM
–76
MCS0 (20 MHz channel)
–91
MCS1 (20 MHz channel)
–88
MCS2 (20 MHz channel)
–86
MCS3 (20 MHz channel)
–83
MCS4 (20 MHz channel)
–81
MCS5 (20 MHz channel)
–77
MCS6 (20 MHz channel)
–75
MCS7 (20 MHz channel)
–73
MCS0 (40 MHz channel)
–90
MCS1 (40 MHz channel)
–86
MCS2 (40 MHz channel)
–84
MCS3 (40 MHz channel)
–82
MCS4 (40 MHz channel)
–78
MCS5 (40 MHz channel)
–74
MCS6 (40 MHz channel)
–72
MCS7 (40 MHz channel)
–70
a. Values are measured at the input of the BCM43143. Thus, they include insertion losses from the integrated
baluns and integrated T/R switches, but exclude losses from the external circuits. For the 1, 2, 5.5, and 11 Mbps
rates, sensitivity is defined as an 8% packet error rate (PER) for 1000-octet PSDUs. For 11g rates (6 Mbps
OFDM up to 54 MBps OFDM), sensitivity is defined as a 10% packet error rate (PER) for 1000-octet PSDUs.
For 11n rates (MCS0 to MCS7), sensitivity numbers are provide for 10% PER and 4000byte packets.
b. Sensitivity levels at Vcc=3.3V±6%; at Vcc=3.3 ±10%, sensitivity levels may be degraded.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 40
BCM43143 Advance Data Sheet
2.4 GHz Band Transmitter RF Specifications
2.4 GHz Band Transmitter RF Specifications
Table 16: 2.4 GHz Band Transmitter RF Specifications
Characteristic
Condition
RF output frequency range
–
Chip output powera
(EVM and ACPR compliant,
Vcc=3.3V ±6%b)
20 MHz
channel
40 MHz
channel
Min.
Typ.
Max.
Unit
2400
–
2500
MHz
DSSS/CCK rates
1, 2, 5.5, and 11 Mbit/s
–
–
21.0
dBm
802.11g rates
6, 9, 12, 18, 24, and 36 Mpps
–
–
20.0
802.11g rate 48 Mbps
–
–
19.0
802.11g rate 56 Mbps
–
–
18.0
OFDM rates MCS0-MCS5
–
–
20.0
OFDM rate MCS6
–
–
19.0
OFDM rate MCS7
–
–
18.0
OFDM rates MCS0- MCS4
–
–
19.5
OFDM rate MCS5
–
–
19.0
OFDM rate MCS6
–
–
18.0
OFDM rate MCS7
–
–
17.0
Gain flatness
Maximum gain
–
–
2
dB
Output IP3
Maximum gain
–
37
–
dBm
Output P1dB
–
–
27
–
dBm
Carrier suppression
–
15
–
–
dBr
CCK TX spectrum mask @
maximum gain
fc –22 MHz < f < fc –11 MHz
–
–
–30
dBr
fc +11 MHz < f< fc +22 MHz
–
–
–30
dBr
f < fc –22 MHz; and f > fc +22 MHz
–
–
–50
dBr
f < fc –11 MHz and f > fc +11 MHz
–
–
–26
dBc
f < fc –20 MHz and f > fc +20 MHz
–
–
–35
dBr
f < fc –30 MHz and f > fc +30 MHz
–
–
–40
dBr
TX modulation accuracy (i.e.
EVM) at maximum gain
IEEE 802.11b mode
–
–
35%
–
IEEE 802.11g mode QAM64 54 Mbps
–
–
5%
–
Gain control step size
–
–
0.25
–
dB/
step
Amplitude balancec
DC input
–1
–
1
dB
Phase balance
DC input
–1.5
–
1.5
°
Baseband differential input
voltage
Shaped pulse
–
0.6
–
Vpp
OFDM TX spectrum mask
(chip output power = 16 dBm)
TX power ramp up
90% of final power
–
–
2
sec
TX power ramp down
10% of final power
–
–
2
sec
a. Power control will back off output power by 1.5 dB ensuring EVM and ACPR limits are always met.
b. Linear output power at 3.3V ±10% supply voltage may be degraded and EVM/ACPR compliant output power
may be lower than listed.
c. At a 3 MHz offset from the carrier frequency.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 41
BCM43143 Advance Data Sheet
2.4 GHz Band Local Oscillator Specifications
2.4 GHz Band Local Oscillator Specifications
Table 17: 2.4 GHz Band Local Oscillator Specifications
Characteristic
Condition
Minimum
Typical
Maximum
Unit
VCO frequency range
–
2412
–
2484
MHz
Reference input frequency range
–
–
Variousa
–
MHz
Reference spurs
–
–
–
–34
dBc
Local oscillator phase noise, single-sided
from 1–300 kHz offset
–
–
–
–86.5
dBc/Hz
Clock frequency tolerance
–
–
–
±20
ppm
a. Reference supported frequencies range from 12 MHz to 52 MHz.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 42
BCM43143 Advance Data Sheet
Antenna Specifications
S e c t i o n 1 2 : A n t e n n a Sp e c i f i c a t i o n s
Voltage Standing Wave Ratio
The Voltage Standing Wave Ratio (VSWR) into the antenna should be less than 2.5:1.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 43
BCM43143 Advance Data Sheet
Timing Characteristics
S e c t i o n 1 3 : Ti m i n g C h a r a c t e r i s t i c s
Power Sequence Timing
The recommended power-up sequence is to bring up the power supplies in the order of the rated voltage. This
power-up sequence minimizes the possibility of a latchup condition.
In the case of a 3.3V supply (see Figure 10), the 3.3V supplied to SR_VDDBAT5V, WRF_PA_VDD3P3,
WRF_PAD_VDD3P3, USB_AVDD3P3, and VDDIO can ramp at the same time.
In the case of a 5V supply (see Figure 11 on page 45), the 5V first ramps on SR_VDDBAT5V, followed by bringup of the 3.3V supply to WRF_PA_VDD3P3, WRF_PAD_VDD3P3, USB_AVDD3P3, and VDDIO. The powerup timing parameters for both configurations are shown in Table 18 on page 45.
Figure 10: Power-Up Sequence Timing—3V Supply
t2
t3
SR_VDDBAT5V
WRF_PA(D)_VDD3P3
USB_AVDD3P3
VDDIO
SR_VLX
VDDC
Internal Reset
Interface
BCM43143 TRI-STATE
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 44
BCM43143 Advance Data Sheet
Power Sequence Timing
Figure 11: Power-Up Sequence Timing—5V Supply with External DC-DC Conversion
t1
t2
t3
SR_VDDBAT5V
WRF_PA(D)_VDD3P3
USB_AVDD3P3
VDDIO
SR_VLX
VDDC
internal reset
interface
43143 TRI-STATE
Table 18: Power-Up Timing Parameters
Symbol
Description
Minimum
Typical
Maximum Unit
t1
SR_VDDBAT5V to 3P3 active
0a
50b
–
µs
t2
Time from VDDIO rising edge to VDDC reaching
1.2V
–
–
850
µs
t3
Time from VDDC reaching 1.2V to internal reset
deactivation
30
35
50
ms
a. In the case of the 3.3V power supply, t1 = 0 for SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3.
b. In the case of the 5V power supply, SR_VDD_BAT5V is directly connected to 5V, but the connection to
WRF_PA_VDD3P3, WRF_PAD_VDD3P3, and VDDIO must be made through a DC-DC converter chip to
convert 5V to 3V3. Since the converter chip introduces a delay in the ramp-up time, t1 = 50 µs (nominal). The
actual value of t1 will vary slightly based on the particular DC-DC converter chip used in the design.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 45
BCM43143 Advance Data Sheet
Serial Flash Timing
Serial Flash Timing
Figure 12: Serial Flash Timing Diagram (STMicroelectronics-Compatible)
tCS
SFLASH_CSN
tCSS
tCSH
tR
tWL
tWH
tF
SFLASH_CLK
tSU
SFLASH_SI
tH
VALID IN
tV
SFLASH_SO
High Impedance
tHO
High Impedance
VALID ON
Table 19: Serial Flash Timing
Parameter
Descriptions
Minimum
Typical
Maximum
Units
fSCK
Serial flash clock frequency
–
12.5
49.2
MHz
tWH
Serial flash clock high time
9
–
–
ns
tWL
Serial flash clock low time
9
–
–
ns
tR, tFa
Clock rise and fall timesb
TBD
–
–
V/ns
tCSS
Chip select active setup time
5
–
–
ns
tCS
Chip select deselect time
100
–
–
ns
tCSH
Chip select hold time
5
–
–
ns
tSU
Data input setup time
2
–
–
ns
tH
Data input hold time
5
–
–
ns
tHO
Data output hold time
0
–
–
ns
tV
Clock low to output valid
–
–
8
ns
a. tR and tF are expressed as a slew-rate.
b. Peak-to-peak
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 46
I2S Slave Mode Tx Timing
BCM43143 Advance Data Sheet
I2S Slave Mode Tx Timing
In I2S slave mode, the serial clock (I2S_BITCLK) input speed can vary up to a maximum of 12.288 MHz.
I2S Slave mode timing is illustrated in Figure 13.
Figure 13: I2S Slave Mode Timing
BITCLK
WS
SD
MSB
LSB
WORD n – 1
Right Channel
t HC = 0.35T
t RC
BITCLK
WORD n + 1
Right Channel
WORD n
Left Channel
T
MSB
V
t LC = 0.35T
t htr = 0
V
H = 2.0V
L = 0.8V
t dtr = 0.8T
SD/WS
T = clock period
Ttr = minimum allowed clock period for transmitter
T > Ttr
Table 20: Timing for I2S Transmitters and Receivers
Transmitter
Lower Limit
Parameter
Clock period T
Min
Max
Receiver
Upper Limit
Min
LOW tLC
rise time tRC
Broadcom®
November 14, 2014 • 43143-DS104-R
Max
Min
Max
Ttr
Ttr
Slave Mode:
Clock accepted by
transmitter or receiver:
HIGH tHC
Lower Limit
0.35 Tr
0.35 Tr
0.35 Tr
0.15 Ttr
0.35 Tr
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 47
I2S Slave Mode Tx Timing
BCM43143 Advance Data Sheet
Table 20: Timing for I2S Transmitters and Receivers
Transmitter
Lower Limit
Parameter
Min
Transmitter:
delay tdtr
hold time thtr
Max
Receiver
Upper Limit
Min
Max
Lower Limit
Min
Max
0.8 T
0
Receiver:
setup time tsr
0.2 Tr
hold time thr
0
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 48
BCM43143 Advance Data Sheet
SDIO Default Mode Timing
SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 14 and Table 21.
Figure 14: SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tISU
tIH
Input
Output
tODLY
tODLY
(max)
(min)
Table 21: SDIO Bus Timinga Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency – data transfer mode
fPP
0
–
25
MHz
Frequency – identification mode
fOD
0
–
400
kHz
Clock low time
tWL
10
–
–
ns
Clock high time
tWH
10
–
–
ns
Clock rise time
tTLH
–
–
10
ns
Clock low time
tTHL
–
–
10
ns
Input setup time
tISU
5
–
–
ns
Input hold time
tIH
5
–
–
ns
Output delay time – data transfer mode
tODLY
0
–
14
ns
Output delay time – identification mode
tODLY
0
–
50
ns
Inputs: CMD, DAT (referenced to CLK)
Outputs: CMD, DAT (referenced to CLK)
a. Timing is based on CL ≤40 pF load on CMD and data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 49
BCM43143 Advance Data Sheet
SDIO High Speed Mode Timing
SDIO High Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 15 and Table 22 on page 51.
Figure 15: SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tISU
tTLH
tIH
Input
Output
tODLY
Broadcom®
November 14, 2014 • 43143-DS104-R
tOH
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 50
BCM43143 Advance Data Sheet
SDIO High Speed Mode Timing
Table 22: SDIO Bus Timinga Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum Unit
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Frequency – data transfer mode
fPP
0
–
50c
MHz
Frequency – identification mode
fOD
0
–
400
kHz
Clock low time
tWL
7
–
–
ns
Clock high time
tWH
7
–
–
ns
Clock rise time
tTLH
–
–
3
ns
Clock low time
tTHL
–
–
3
ns
Input setup time
tISU
6
–
–
ns
Input hold time
tIH
2
–
–
ns
Output delay time – data transfer mode
tODLY
–
–
14
ns
Output hold time
tOH
2.5
–
–
ns
Total system capacitance (each line)
CL
–
–
40
pF
Inputs: CMD, DAT (referenced to CLK)
Outputs: CMD, DAT (referenced to CLK)
a. Timing is based on CL ≤40 pF load on CMD and data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
c. 0 - 46 MHz when running at 1.8V.
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 51
BCM43143 Advance Data Sheet
USB Parameters
USB Parameters
Table 23: USB Parameters
Parameter
Symbol
Comments
Minimum Typical
Maximum Unit
BPS
–
–
2.5
–
Gbaud
Reference frequency Fref
From crystal oscillator
–
100
–
MHz
Reference clock
amplitude
LVPECL, AC coupled
1
–
–
V
General
Baud rate
Vref
Receiver
Differential termination ZRX-DIFF-DC
Differential termination 80
100
120
Ω
DC impedance
ZRX-DC
DC common-mode
impedance
40
50
60
Ω
Powered down
termination
ZRX-HIGH-IMPDC
Power-down high
impedance
(singled ended to
ground)
200k
–
–
Ω
Input voltage
VRX-DIFFp-p
AC coupled, differential 175
p-p
–
1200
mV
Jitter tolerance
TRX-EYE
Minimum receiver eye
width
0.4
–
–
UI
Differential return loss RLRX-DIFF
Differential return loss
12
–
–
dB
Common-mode return RLRX-CM
loss
Common-mode return
loss
11
–
–
dB
Unexpected electrical TRX-IDEL-DETDIFF-ENTERTIME
idle enter detect
threshold integration
time
–
An unexpected
electrical idle must be
recognized no longer
than this time to signal
an unexpected idle
condition.
–
10
ms
Signal detect
threshold
VRX-IDLE-DETDIFFp-p
Electrical idle detect
threshold
65
–
175
mV
Output voltage
VTX-DIFFp-p
Differential p-p,
programmable in 16
steps
0
–
1200
mV
Output voltage rise
time
VTX-RISE
20% to 80%
0.125
–
–
UI
Output voltage fall
time
VTX-FALL
80% to 20%
0.125
–
–
UI
De-emphasis (a1)
VTX-DE-RATIO
Programmable in 16
steps
0
–
40
%
RX detection voltage
swing
VTX-RCVDETECT
The amount of voltage –
change allowed during
receiver detection.
–
600
mV
Transmitter
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 52
BCM43143 Advance Data Sheet
USB Parameters
Table 23: USB Parameters (Cont.)
Parameter
Symbol
Comments
Minimum Typical
Maximum Unit
AC peak commonmode voltage
VTX-CM-Acp
AC peak commonmode ripple
–
–
20
mV
0
Absolute delta of DC
common-mode voltage
during L0 and electrical
idle.
–
100
mV
0
–
25
mV
Absolute delta of DC VTX-CM-DCACTIVE-IDLEcommon-mode
voltage during L0 and DELTA
electrical idle
Absolute delta of DC
common-model
voltage between D+
and D-
VTX-CM-DC-LINE- DC offset between
DELTA
D+ and D–
VTX-IDLE-DIFFp
Electrical idle
differential peak output
voltage
Peak-to-peak voltage
0
–
20
mV
TX short circuit current ITX-SHORT
Current limit when TX
output is shorted to
ground.
–
–
90
mA
Differential termination ZTX-DIFF-DC
Differential termination 80
100
120
Ω
Differential return loss RLTX-DIFF
Differential return loss
8
–
–
dB
Common-mode return RLTX-CM
loss
Common-mode
return loss
8
–
–
dB
TX eye width
Minimum TX eye width 0.7
–
–
UI
TTX-EYE
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 53
BCM43143 Advance Data Sheet
Thermal Information
Section 14: Thermal Information
Table 24: 56-pin QFN Thermal Characteristicsa
Air Velocity m/s
Power W
TJ_MAX °C
Tt °C
JA, °C/W
JT °C/W
0
1.166
110.3
105.2
37.95
4.37
a. 1s1P JEDEC board, package only, no heat sink, TA = 65°C. P = 1.061W (PA on).
Note:
•
Ambient air temperature is 1 mm above the heat shield on top of the chip.
•
Ambient air temperature: TA = 65°C, subject to absolute junction maximum temperature at
125°C.
•
The BCM43143 is designed and rated for operation at a maximum junction temperature not to
exceed 125°C.
Junction Temperature Estimation and PSIJT Versus ThetaJC
Package thermal characterization parameter Psi-JT (JT) yields a better estimation of actual junction
temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta-JC (JC). The reason for
this is JC assumes that all the power is dissipated through the top surface of the package case. In actual
applications, some of the power is dissipated through the bottom and sides of the package. JT takes into
account power dissipated through the top, bottom, and sides of the package. The equation for calculating the
device junction temperature is as follows:
TJ = TT + P JT
Where:
•
TJ = junction temperature at steady-state condition, °C
•
TT = package case top center temperature at steady-state condition, °C
•
P = device power dissipation, Watts
•
JT = package thermal characteristics (no airflow), °C/W
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 54
BCM43143 Advance Data Sheet
Package Information
Section 15: Package Information
Figure 16: 7 mm × 7 mm, 56-pin QFN package
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 55
BCM43143 Advance Data Sheet
Ordering Information
S e c t i o n 1 6 : O rd e r i n g I n f o r m a t i o n
Table 25: Ordering Information
Part Number
Package
Ambient Temperature
BCM43143KMLG
7 mm × 7 mm, 56-pin QFN (RoHs compliant)
0 to 65°C (32 to 149°F)
Broadcom®
November 14, 2014 • 43143-DS104-R
Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio
Page 56
BCM43143 Advance Data Sheet
Broadcom® Corporation reserves the right to make changes without further notice to any products or
data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,
Broadcom Corporation does not assume any liability arising out of the application or use of this
information, nor the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
®
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2014 by BROADCOM CORPORATION. All rights reserved.
43143-DS104-R
November 14, 2014
Phone: 949-926-5000
Fax: 949-926-5203
E-mail: [email protected]
Web: www.broadcom.com