IDT IDT74FCT16952ATPV Fast cmos 16-bit registered transceiver Datasheet

IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16952AT/CT/ET
FAST CMOS
16-BIT REGISTERED
TRANSCEIVER
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤1µA (max.)
High drive outputs (-32mA IOH, 64mA IOL)
Power off disable outputs permit “live insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
• Available in SSOP and TSSOP packages
The FCT16952T 16-bit registered transceiver is built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type registered transceivers with
separate input and output control for independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be low to enter
data from the A port. xCLKAB controls the clocking function. When xCLKAB
toggles from low-to-high, the data present on the A port will be clocked into
the register. xOEAB performs the output enable function on the B port. Data
flow from the B port to A port is similar but requires using xCEBA, xCLKBA,
and xOEBA inputs. Full 16-bit operation is achieved by tying the control pins
of the independent transceivers together.
The FCT16952T is ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability allowing "live insertion" of boards when used as backplane
drivers.
FUNCTIONAL BLOCK DIAGRAM
54
31
2 CEBA
1 CEBA
30
55
2 CLKBA
1 CLKBA
28
1
2 OEAB
1 OEAB
26
3
2 CEAB
1 CEAB
2
27
2 CLKAB
1 CLKAB
29
56
2 OEBA
1 OEBA
C
CE
5
1A1
D
15
2A1
52
1B1
C
CE
D
42
2B 1
C
CE
D
C
CE
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2002
1
2002 Integrated Device Technology, Inc.
DSC-5442/2
IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
1 OEAB
1
56
1 OEBA
Symbol
Description
VTERM(2)
Terminal Voltage with Respect to GND
VTERM(3) Terminal Voltage with Respect to GND
Max
Unit
–0.5 to +7
V
–0.5 to VCC+0.5
V
1 CLKAB
2
55
1 CEAB
3
54
GND
4
53
GND
1A 1
5
52
1B 1
1A 2
6
51
1B 2
VCC
7
50
V CC
1A 3
8
49
1B 3
1A 4
9
48
1B 4
1A 5
10
47
1B 5
GND
11
46
GND
1A 6
12
45
1B 6
1A 7
13
44
1B 7
1A 8
14
43
1B 8
2A 1
15
42
2B 1
2A 2
16
41
2B 2
2A 3
17
40
2B 3
GND
18
39
GND
2A 4
19
38
2B 4
2A 5
20
37
2B 5
2A 6
21
36
2B 6
VCC
22
35
V CC
xCEAB
xCLKAB
xOEAB
xAx
xBx
2A 7
23
34
2B 7
H
X
L
X
B(2)
2A 8
24
33
2B 8
X
L
L
X
B(2)
GND
25
32
GND
L
↑
L
L
L
2 CEAB
26
31
2 CEBA
L
↑
L
H
H
2 CLKAB
27
30
2 CLKBA
X
X
H
X
Z
2 OEAB
28
29
1 CLKBA
1 CEBA
B-to-A Output Enable Input (Active LOW)
xCEAB
A-to-B Clock Enable Input (Active LOW)
xCEBA
B-to-A Clock Enable Input (Active LOW)
xCLKAB
A-to-B Clock Input
xCLKBA
B-to-A Clock Input
xAx
A-to-B Data Inputs or B-to-A 3-State Outputs
xBx
B-to-A Data Inputs or A-to-B 3-State Outputs
mA
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1,3)
Inputs
Outputs
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA, and
xOEBA.
2. Level of B before the indicated steady-state input conditions were established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
Description
A-to-B Output Enable Input (Active LOW)
°C
–60 to +120
Symbol
PIN DESCRIPTION
xOEBA
–65 to +150
DC Output Current
CAPACITANCE (TA = +25°C, F = 1.0MHz)
2 OEBA
xOEAB
Storage Temperature
IOUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
SSOP/ TSSOP
TOP VIEW
Pin Names
TSTG
2
IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current (Input pins)(5)
VCC = Max.
—
—
±1
µA
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
IIL
Input LOW Current (Input pins)(5)
VI = GND
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
Input LOW Current (I/O pins)(5)
IOZH
High Impedance Output Current
IOZL
(3-State Output pins)(5)
VCC = Max.
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
IOS
Short Circuit Current
VCC = Max., VO = GND(3)
–80
–140
–250
mA
VH
Input Hysteresis
—
100
—
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
—
5
500
µA
—
VCC = Max.
VIN = GND or VCC
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
IO
VOH
Test Conditions(1)
Parameter
Output Drive Current
Output HIGH Voltage
VCC = Max., VO =
VCC = Min.
VIN = VIH or VIL
2.5V(3)
IOH = –3mA
IOH = –15mA
IOH = –32mA(4)
IOL = 64mA
VOH
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = -55°C.
3
Min.
Typ.(2)
Max.
Unit
–50
2.5
2.4
2
—
—
3.5
3.5
3
0.2
–180
—
—
—
0.55
mA
—
—
±1
µA
V
V
IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
ICCD
IC
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.,
Outputs Open
xOEAB = xOEBA = GND
One Input Toggling
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
fi = 5MHz
50% Duty Cycle
One Bit Toggling
VCC = Max., Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
fi = 2.5MHz
50% Duty Cycle
Sixteen Bits Toggling
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
VIN = VCC
VIN = GND
—
0.8
1.7
mA
VIN = 3.4V
VIN = GND
—
1.3
3.2
VIN = VCC
VIN = GND
—
3.8
6.5(5)
VIN = 3.4V
VIN = GND
—
8.3
20(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (f CPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
FCT16952AT FCT16952CT
Symbol
Parameter
FCT16952ET
Condition(1)
Min.(2)
Max.
Min.(2)
Max. Min.(2)
Max.
Unit
CL = 50pF
RL = 500Ω
2
10
2
6.3
1.5
3.7
ns
tPLH
tPHL
Propagation Delay
xCLKAB, xCLKBA to xBx, xAx
tPZH
tPZL
Output EnableTime
xOEBA, xOEAB to xAx, xBx
1.5
10.5
1.5
7
1.5
4.4
ns
tPHZ
tPLZ
Output Disable Time
xOEBA, xOEAB to xAx, xBx
1.5
10
1.5
6.5
1.5
3.6
ns
tSU
Set-up Time, HIGH or LOW
2.5
—
2.5
—
1.5
—
ns
2
—
1.5
—
0
—
ns
3
—
3
—
2
—
ns
2
—
2
—
0
—
ns
Pulse Width HIGH or LOW, xCLKAB or xCLKBA (3)
3
—
3
—
3
—
ns
Output Skew(4)
—
0.5
—
0.5
—
0.5
ns
xAx, xBx to xCLKAB, xCLKBA
tH
Hold Time, HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
tSU
Set-up Time, HIGH or LOW
xCEBA, xCEAB, to xCLKAB, xCLKBA
tH
Hold Time, HIGH or LOW
xCEBA, xCEAB, to xCLKAB, xCLKBA
tW
tSK(o)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
500 Ω
V OUT
V IN
Pulse
Generator
D.U.T.
50pF
RT
500 Ω
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
CL
Test Circuits for All Outputs
DATA
INPUT
tH
t SU
TIM ING
INPUT
ASYNCHRONOUS CONTROL
PRES ET
CLEA R
ETC.
SYNCHRONOUS CONTROL
PRES ET
CLEA R
CLOCK ENABLE
ETC.
tR EM
t SU
3V
1.5V
0V
3V
1.5V
0V
LOW -HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW -HIGH
PULSE
1.5V
3V
1.5V
0V
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE
SAM E PHASE
INPUT TRANSITION
tPLH
t PH L
OUTPUT
t PLH
OPPOSITE P HASE
INPUT TRANSITION
t PH L
3V
1.5V
0V
DISABLE
3V
CONTROL
INPUT
1.5V
tPZL
VOH
1.5V
VOL
OUTPUT
NORM ALLY
LOW
3V
1.5V
0V
SW ITCH
CLOSED
Propagation Delay
SW ITCH
OPEN
3.5V
3.5V
1.5V
0.3V
t PZH
OUTPUT
NORM ALLY
HIGH
0V
t PLZ
V OL
tPHZ
0.3V
V OH
1.5V
0V
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16925AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
FCT
Temp. Range
XXX
Family
XXXX
Device Type
XX
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
952AT 16-Bit Registered Transceiver
952CT
952ET
16
Double-Density, 5 Volt, High Drive
74
– 40°C to +85°C
DATA SHEET DOCUMENT HISTORY
6/24/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
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7
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