ON MC100LVELT22DTG 3.3v dual lvttl/lvcmos to differential lvpecl translator Datasheet

MC100LVELT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Due to LVPECL (Low Voltage Positive ECL)
levels, only +3.3V and ground is required. The small 8−lead package
outline with low skew dual gate design makes the MC100LVELT22
ideal for applications which require translation of a clock and/or data
signal.
Features
•
•
•
•
•
•
•
350 ps Typical Propagation Delay
<100 ps Output−to−Output Skew
Flow Through Pinouts
The 100 Series Contains Temperature Compensation
LVPECL Operating Range: VCC = 3.15 V to 3.45 V
with GND = 0 V
When Unused TTL Input is left Open, Q Output will Default High
These are Pb−Free Devices
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MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
8
KVT22
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
A
L
Y
W
M
G
KR22
ALYWG
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 12
1
Publication Order Number:
MC100LVELT22/D
MC100LVELT22
Table 1. PIN DESCRIPTION
Q0
Q0
1
8
2
LVPECL
VCC
7
D0
PIN
Qn, Qn
D0, D1
VCC
GND
LVTTL/
LVCMOS
Q1
3
6
D1
Q1
4
5
GND
FUNCTION
LVPECL Differential Outputs
LVTTL/LVCMOS Inputs
Positive Supply
Ground
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
Level 1
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
7
V
7
V
50
100
mA
mA
VCC
Positive Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SO−8
SO−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
std bd
SO−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
std bd
TSSOP−8
41 to 44 ± 5%
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 260°C
265
°C
Pb−Free
VI VCC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
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2
MC100LVELT22
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
85°C
Typ
Max
28
Min
Typ
Max
Unit
29
mA
ICC
Power Supply Current
28
VOH
Output HIGH Voltage (Note 4)
2275
2420
2275
2420
2275
2420
mV
VOL
Output LOW Voltage (Note 4)
1490
1680
1490
1680
1490
1680
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Output parameters vary 1:1 with VCC. VCC can vary ±0.15 V.
4. Outputs are terminated through a 50 ohm resistor to VCC−2 V.
Table 5. LVTTL/LVCMOS INPUT DC CHARACTERISTICS VCC = 3.3 V; TA = −40°C to 85°C (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
IIH
Input HIGH Current
20
mA
VIN = 2.7 V
IIHH
Input HIGH Current
100
mA
VIN = VCC
IIL
Input LOW Current
−0.2
mA
VIN = 0.5 V
VIK
Input Clamp Diode Voltage
−1.2
V
VIH
Input HIGH Voltage
2.0
3.3
V
VIL
Input LOW Voltage
0
0.8
V
IIN = −18 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. VCC can vary ±0.15 V.
Table 6. AC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 6)
−40°C
Symbol
Characteristic
fmax
Maximum Toggle Frequency
t
PLH
Propagation Delay (Note 7)
skew
Skew
JITTER
Random Clock Jitter (RMS)
tjit(f)
Additive RMS Phase Jitter
fc = 50 MHz, Integration Range: 12 kHz
to 20 MHz (See Figure 2)
t /t
r f
Output Rise/Fall Time (20−80%)
t
t
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
350
200
Output−to−Output
Part−to−Part
350
600
30
200
MHz
350
600
100
400
30
100
400
2.1
1.1
1.9
200
350
600
ps
30
100
400
ps
1.6
ps
219
200
550
200
Unit
fs
500
200
500
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. VCC can vary ±0.15 V. Outputs are terminated through a 50 W resistor to VCC − 2 V.
7. Specifications for standard TTL input signal.
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MC100LVELT22
Figure 2. Typical MC100LVELT22 Phase Noise Plot at fCarrier = 50 MHz, VCC = 3.3 V, 255C
notably lower than that of the DUT. If the phase noise of the
source is greater than the noise floor of the device under test,
the source noise will dominate the additive phase jitter
calculation and lead to an incorrect negative result for the
additive phase noise within the integration range. The
Figure above is a good example of the MC100LVELT22
source generator phase noise having a significantly lower
floor than the DUT and results in an additive phase jitter of
219 fs.
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 219 fs. The additive RMS phase jitter
performance of the translator is highly dependent on the
phase noise of the input source.
To obtain the most precise additive phase noise
measurement, it is vital that the source phase noise be
Additive RMS phase jitter = √RMS phase jitter of output2 − RMS phase jitter of input2
219 fs + Ǹ587.92 fs2 * 545.23 fs2
Figure 2 was created with measured data from
Agilent−E5052B Signal Source Analyzer using ON
Semiconductor Phase Noise Explorer web tool. This free
application enables an interactive environment for advanced
phase noise and jitter analysis of timing devices and clock
tree designs. To see the performance of MC100LVELT22
beyond conditions outlined in this datasheet, please visit the
ON Semiconductor Green Point Design Tools homepage.
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4
MC100LVELT22
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
MC100LVELT22DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100LVELT22DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100LVELT22DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100LVELT22DTRG
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVELT22
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100LVELT22
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
5
0.25 (0.010)
B
−U−
L
0.15 (0.006) T U
M
M
4
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
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