IDT ICS291 Triple pll field prog. spread spectrum clock synthesizer Datasheet

DATASHEET
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER ICS291
Description
Features
The ICS291 field programmable spread spectrum clock
synthesizer generates up to six high-quality, high-frequency
clock outputs including multiple reference clocks from a
low-frequency crystal input. It is designed to replace
crystals, crystal oscillators and stand alone spread
spectrum devices in most electronic systems.
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Using IDT’s VersaClockTM software to configure PLLs and
outputs, the ICS291 contains a One-Time Programmable
(OTP) ROM for field programmability. Programming
features include input/output frequencies, spread spectrum
amount, eight selectable configuration registers and up to
two sets of three low-skew outputs.
Each of the two output groups are powered by a separate
VDDO voltage. VDDO may vary from 1.8 V to VDD.
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
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Packaged as 20-pin TSSOP – Pb-free, RoHS compliant
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Configurable Spread Spectrum Modulation
Input crystal frequency of 5 to 27 MHz
Clock input frequency of 3 to 166 MHz
Up to six reference outputs
Separate 1.8 to 3.3 V VDDO output level controls for
each bank of 3 outputs
Up to two sets of three low-skew outputs
Operating voltages of 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
The ICS291 is also available in factory programmed custom
versions for high-volume applications.
Block Diagram
VDD
S2:S0
3
OTP
ROM
with PLL
Values
VDDO1
3
PLL1 with
Spread
Spectrum
CLK1
CLK2
Divide
Logic
and
Output
Enable
Control
PLL2
PLL3
CLK3
CLK4
CLK5
X1/ICLK
Crystal or
Clock Input
Crystal
Oscillator
CLK6
X2
External capacitors
are required with a crystal input.
GND
3
PDTS
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Pin Assignment
20
S2
2
19
VDD
S1
VDD
3
18
PDTS
4
17
GND
VDDO1
5
16
CLK6
CLK1
6
15
CLK5
CLK2
7
14
CLK4
CLK3
GND
8
13
9
12
VDDO2
VDD
10
11
X2
GND
1
S0
X1/ICLK
20 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
GND
Power
Connect to ground.
2
S0
Input
Select pin 0. Internal pull-up resistor.
Pin Description
3
S1
Input
4
VDD
Power
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
5
VDDO1
Power
Power supply for outputs CLK1-CLK3.
6
CLK1
Output
Output clock 1. Weak internal pull-down when tri-state.
7
CLK2
Output
Output clock 2. Weak internal pull-down when tri-state.
8
CLK3
Output
Output clock 3. Weak internal pull-down when tri-state.
9
GND
Power
Connect to ground.
10
X1/ICLK
XI
Crystal input. Connect this pin to a crystal or external input clock.
11
X2
XO
12
VDD
Power
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect to +3.3 V.
13
VDDO2
Power
Power supply for outputs CLK4-CLK6.
14
CLK4
Output
Output clock 4. Weak internal pull-down when tri-state.
15
CLK5
Output
Output clock 5. Weak internal pull-down when tri-state.
16
CLK6
Output
Output clock 6. Weak internal pull-down when tri-state.
17
GND
Power
Connect to ground.
18
PDTS
Input
19
VDD
Power
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
Connect to +3.3 V.
20
S2
Input
Select pin 2. Internal pull-up resistor.
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External Components
EPROM CLOCK SYNTHESIZER
The ICS291 requires a minimum number of external
components for proper operation.
The ICS291 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Series Termination Resistor
Each output frequency can be represented as:
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS291
must be isolated from system power supply noise to perform
optimally.
OutputFreq
=
REFFreq
⋅
M
----N
Output Drive Control
The ICS291 has two output drive settings. For VDDO=VDD,
low drive should be selected when outputs are less than 100
MHz. High drive should be selected when outputs are
greater than 100 MHz.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
For VDDO<2.8 V, high drive should be selected for all output
frequencies.
Crystal Load Capacitors
IDT VersaClock Software
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
ICS291 Configuration Capabilities
The architecture of the ICS291 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS291 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electromagnetic interference (EMI). The
modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
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Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS291 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between ±0.125% to ±2.0%. For down spread,
the frequency can be modulated between -0.25% to -4.0%.
EPROM CLOCK SYNTHESIZER
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS291. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
Clock Outputs
Referenced to GND
Max.
Units
7
V
-0.5
VDD+0.5
V
-0.5
VDD+0.5
V
-65
150
°C
260
°C
125
°C
Storage Temperature
Soldering Temperature
Typ.
Max 10 seconds
Junction Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS291GP)
0
+70
°C
Ambient Operating Temperature (ICS291GIP)
-40
+85
°C
+3.465
V
4
ms
Power Supply Voltage (measured in respect to GND)
+3.135
Power Supply Ramp Time
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Symbol
Conditions
VDD
VDDO Voltage
VDDO1 and VDDO2
Min.
Typ.
Max.
Units
3.135
3.465
V
1.80
VDD
V
mA
Config. Dependent - See
VersaClockTM Estimates
Operating Supply Current
IDD
Six 33.3333 MHz outs,
VDD=VDDO=3.3 V;
PDTS = 1, no load, Note 1
25
mA
500
µA
V
Input High Voltage
VIH
PDTS = 0, no load
S2:S0
Input Low Voltage
VIL
S2:S0
Input High Voltage, PDTS
VIH
Input Low Voltage, PDTS
VIL
Input High Voltage
VIH
ICLK
Input Low Voltage
VIL
ICLK
Output High Voltage
(CMOS High)
VOH
IOH = -4 mA
Output High Voltage
VOH
IOH = -8 mA (Low Drive);
IOH = -12 mA (High Drive)
Output Low Voltage
VOL
IOL = 8 mA (Low Drive);
IOL = 12 mA (High Drive)
Short Circuit Current
IOS
Low Drive
±40
High Drive
±70
mA
20
Ω
VDD/2+1
0.4
VDD-0.5
V
V
0.4
VDD/2+1
V
V
VDD/2-1
V
VDD-0.4
V
2.4
VDDO-0.4
V
0.4
V
Nom. Output Impedance
ZO
Internal Pull-up Resistor
RPUS
S2:S0, PDTS
190
kΩ
Internal Pull-down
Resistor
RPD
CLK outputs
120
kΩ
Input Capacitance
CIN
Inputs
4
pF
Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Input Frequency
FIN
Output Frequency
Conditions
Min.
Typ.
Max. Units
Fundamental crystal
5
27
MHz
Clock input
3
166
MHz
VDDO=VDD
0.314
200
MHz
1.8 V<VDDO<2.8 V
0.314
150
MHz
Output Rise/Fall Time
tOF
80% to 20%, high drive,
Note 1
1.0
ns
Output Rise/Fall Time
tOF
80% to 20%, low drive,
Note 1
2.0
ns
Output Rise/Fall Time
tOF
80% to 20%, high drive,
1.8 V<VDDO<2.8
Note 2
2.0
ns
Duty Cycle
Note 2
Output Frequency Synthesis Error
Configuration Dependent
Power-up time
PLL lock-time from
power-up
One Sigma Clock Period Jitter
Maximum Absolute Jitter
tja
Pin-to-Pin Skew
40
49-51
60
TBD
%
ppm
4
10
ms
PDTS goes high until
stable CLK output,
Spread Spectrum Off
0.6
2
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
4
7
ms
Configuration Dependent
50
ps
Deviation from Mean.
Configuration Dependent
+200
ps
Low Skew Outputs
-250
250
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θ JA
Still air
93
° C/W
θ JA
1 m/s air flow
78
° C/W
θ JA
3 m/s air flow
65
° C/W
20
° C/W
θ JC
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Marking Diagrams
20
11
######
YYWW
291PGL
1
10
20
11
######
YYWW
291PGIL
1
10
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
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Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
24
Millimeters
Symbol
E1
INDEX
AREA
E
A1
A2
b
C
D
E
E1
e
L
α
1 2
D
Min
Inches
Max
Min
—
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40
6.60
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
Max
—
.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.252
0.260
0.252 BASIC
0.169
0.177
0.0256 Basic
.018
.030
0°
8°
A
A2
A1
c
- Ce
b
SEATING
PLANE
.10 (.004)
C
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L
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Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
291PGLF
see page 7
Tubes
20-pin TSSOP
0 to +70° C
Tubes
20-pin TSSOP
-40 to +85° C
291PGILF
Temperature
291G-XXLF
291GXXL
Tubes
20-pin TSSOP
0 to +70° C
291GI-XXLF
291GIXXL
Tubes
20-pin TSSOP
-40 to +85° C
291G-XXLFT
291GXXL
Tape and Reel
20-pin TSSOP
0 to +70° C
291GI-XXLFT
291GIXXL
Tape and Reel
20-pin TSSOP
-40 to +85° C
“LF” suffix to the part number denotes Pb-Free configuration, RoHS compliant.
The 291G-XXLF and 291GI-XXLF are factory programmed versions of the 291PGLF and 291PGILF. A unique “-XX” suffix is
assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom
part numbers programmed at the factory, please contact your local IDT sales and marketing representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
VersaClockTM is a trademark of IDT, Inc. All rights reserved.
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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