LM34902 300mA Current Limited Power Switch General Description Features The LM34902 is a 0.3A PFET switch used to control the input voltage of electronic devices. It is easily integrated into system designs that have a 2.8V to 5.3V voltage rail. Besides the 0.45Ω PFET switch, the LM34902 can be enabled or disabled by a logic signal. The IC monitors the presence of a downstream electronic device via a dedicated pin to decide whether to turn on the PFET switch. A power good signal generated by the IC can be used by system control to determine the status of the switch. The LM34902 also provides over-current and over-temperature protection. The IC comes in a tiny 6bump Thin Micro SMD package. ● ● ● ● ● ● ● ● ● Input voltage of 2.8V to 5.3V 0.3A maximum switch current 0.64Ω typical total on-resistance Load detection Enable/disable Switch on indicator Peak current limit Thermal shutdown 6-Bump thin micro SMD package Applications ● Handsets, tablets, notebooks ● Portable devices Typical Application Circuit 30194901 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 301949 SNVS804A Copyright © 1999-2012, Texas Instruments Incorporated LM34902 Connection Diagram 30194902 Top View 6-Bump Thin Micro SMD Package See NS Package Number TMD06AAA Ordering Information Order Number Supplied As LM34902ITM/NOPB 250 Units on Tape and Reel LM34902ITMX/NOPB 3000 Units on Tape and Reel Pin Description Name Pin Number Function VCC A1 Power input of the PFET switch. It also provides power to the entire IC. Connect to the voltage rail that the accessory device is expected to work off. GND B1 Common Ground (device substrate). POK C1 Open-drain PFET status indicator. When the PFET is off, this pin floats. When PFET is on, it is grounded. ACC_DET C2 Pull this pin low to tell the IC that the downstream accessory device is plugged in. ENABLE B2 When this pin is low, the PFET will be turned off and POK will be open-drained. Current limit circuitry will also be disabled. The IC will be in a low-power state. This pin should be held low until VCC is established to ensure proper initial state of internal logic. When ENABLE is high, the PFET switch will be allowed to turn on. ACC_PWR A2 Power output terminal of the PFET switch. Connect to input rail of accessory device. Truth Table Input Output TJ Limit Exceeded ENABLE ACC_DET Current Limit Detected 2.8V < VCC < 5.3V PFET Switch Status POK 0 x No No Yes Open Open Drain x 1 No No Yes Open Open Drain 0 to 1 0 No No Yes On Grounded 0 to 1 0 Yes No Yes Current Limited Grounded x x x Yes 2.2V < VCC < 5.3V Open Open Drain 0 x x No 2.2V < VCC < 2.8V Open Open Drain Note: "x" stands for "don't care". 2 Copyright © 1999-2012, Texas Instruments Incorporated LM34902 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VCC ENABLE, POK, ACC_DET, ACC_PWR (Note 2) Junction Temperature (TJ) Storage Temperature Range ESD Susceptibility Human Body Model (Note 3) Operating Ratings -0.3V to 6V -0.3V to 6V +150°C −65°C to +150°C 2kV (Note 1) VCC Voltage (Note 4) Junction Temperature (TJ) LM34902 2.8V to 5.3V -40°C to +85°C Electrical Characteristics Unless otherwise stated, the following conditions apply: VCC = 3V. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating juction temperature (TJ) range. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. Symbol Parameter Conditions VIL Input Low Voltage, ACC_DET, ENABLE VIH Input High Voltage, ACC_DET, ENABLE VIHS Input Hysteresis, ACC_DET, ENABLE ILK Input Current, ACC_DET, ENABLE ACC_DET, ENABLE between 0V and VCC ISD VCC Current in Shutdown Mode VENABLE = 0V IQ VCC Quiescent Current RON Total On Resistance Between VCC and ACC_PWR Pins ILK_ACC ACC_PWR Leakage Current When PFET is Off ILIMIT PFET Switch Current Limit VPOK POK Current Sink Capability POK asserted. 1mA sink current. IPOK POK Leakage Current T1 ACC_DET Response Time T2 ENABLE Response Time T3 Minimum ENABLE Cycle Time (Note 5) Min Typ Max Units 0.45 V V 1.35 55 VVCC = 5.3V VENABLE = 1.8V VVCC = 5.3V, IACC_PWR = 0A VVCC = 3V IACC_PWR = 0.3A mV 1 µA 10 µA 47 100 µA 0.64 1 Ω 1 µA 0.65 A 0.4 V 1 µA VACC_PWR = 0V to VCC VVCC = 5.3V VENABLE = 0V VVCC = 2.8V to 5.3V VACC_PWR = 0V 0.3 0.45 POK de-asserted. VPOK = 3.3V ACC_DET rising to either PFET or POK FET turn-off 40 ns ENABLE rising to either PFET or POK FET turn-on 10 µs ACC_DET tied to ground. ENABLE logic high = 1.8V. VCC = 2.8V to 5.3V. 300 ns Copyright © 1999-2012, Texas Instruments Incorporated 3 LM34902 Thermal Characteristics Symbol Description Conditions Typical Value Unit 104 °C/W θJA1 Junction-to-Ambient Thermal Resistance Mount device on a standard 4-layer 4" x 3" JEDEC board. Apply known amount of power to the package. Measure junction temperature and surrounding air temperature. No air flow. Refer to JESD51-7 for more information. θJA2 Junction-to-Ambient Thermal Resistance Mount device on a 2-layer 2.19" x 2.9" board. Copper thickness is 1 oz per layer. No airflow. Power dissipation is 0.5W. 136 °C/W TSD Thermal Shutdown Threshold Raise TJ from below 150°C until POK is de-asserted. No load is connected at ACC_PWR. 170 °C Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table. Note 2: The voltages on these pins should never exceed VCC+0.3V. Note 3: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-A114. Note 4: For VCC between 2.2V and 2.8V, if ENABLE is a logic low, the LM34902 will not turn on the PFET switch. Note 5: If ENABLE toggles low from a high state, it needs to stay low for at least T3 long before toggling back to high. Otherwise the internal flip-flop may not be set and the PFET switch may not turn on. 4 Copyright © 1999-2012, Texas Instruments Incorporated LM34902 Typical Performance Characteristics Total ON Resistance vs Temperature Unless indicated otherwise, VCC = 3V and TJ = 25°C. Total ON Resistance vs Switch Current 30194904 Total ON Resistance vs VCC 30194905 Current Limit vs Temperature 30194910 30194906 Input Logic High Threshold vs Temperature Input Logic Low Threshold vs Temperature 30194908 30194909 Copyright © 1999-2012, Texas Instruments Incorporated 5 LM34902 Block Diagram 30194903 Application Hints To turn on the PFET switch, both the ENABLE and the ACC_DET pins need to be asserted. In addition, ACC_DET needs to be asserted no later than the rising edge of the ENABLE signal. De-assertion of either the ENABLE or the ACC_DET will result in turned-off PFET switch and de-asserted POK signal. To prevent a glitch in the otherwise asserted ACC_DET from keeping the FETs turned off, it is a good practice to cycle the ENABLE following every falling edge in the ACC_DET signal. When cycling the ENABLE, make sure it stays low for at least T3 long before toggling back high. If ENABLE logic high level is not 1.8V, make sure ENABLE stays low for at least 1µs. When laying out the PCB, try to keep the ENABLE and ACC_DET traces as short as possible and away from noisy traces. 6 Copyright © 1999-2012, Texas Instruments Incorporated LM34902 Physical Dimensions inches (millimeters) unless otherwise noted TMD06AAA Package 6-Bump Thin Micro SMD Package NS Package Number TMD06AAA X1 = 0.815 ±0.03mm X2 = 1.215 ±0.03mm X3 = 0.600 ±0.075mm Copyright © 1999-2012, Texas Instruments Incorporated 7 Notes Copyright © 1999-2012, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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