Intersil ISL85033IRTZ Wide vin dual standard buck regulator with 3a/3a continuous output current Datasheet

Wide VIN Dual Standard Buck Regulator With 3A/3A
Continuous Output Current
ISL85033
Features
The ISL85033 is a dual standard buck regulator capable of 3A
per channel continuous output current. With an input range of
4.5V to 28V, it provides a high frequency power solution for a
variety of point of load applications.
• Wide Input Voltage Range from 4.5V to 28V
• Adjustable Output Voltage with Continuous Output Current
up to 3A
• Current Mode Control
The PWM controller in the ISL85033 drives an internal
switching N-Channel power MOSFET and requires an external
Schottky diode to generate the output voltage. The integrated
power switch is optimized for excellent thermal performance
up to 3A of output current. The PWM regulator switches at a
default frequency of 500kHz and it can be user programmed
or synchronized from 300kHz to 2MHz. The ISL85033 utilizes
peak current mode control to provide flexibility in component
selection and minimize solution size. The protection features
include overcurrent, UVLO and thermal overload protection.
• Adjustable Switching Frequency from 300kHz to 2MHz
• Independent Power-Good Detection
• Selectable In-Phase or Out-of-Phase PWM Operation
• Independent, Sequential, Ratiometric or Absolute Tracking
Between Outputs
• Internal 2ms Soft-start Time
• Overcurrent/Short Circuit Protection, Thermal Overload
Protection, UVLO
The ISL85033 is available in a small 4mmx4mm Thin Quad
Flat Pb-free (TQFN) package.
• Boot Undervoltage Detection
Related Literature
Applications
• See AN1574 “ISL85033DUALEVAL1Z Wide VIN Dual
Standard Buck Regulator With 3A/3A Output Current”
• General Purpose Point of Load DC/DC Power Conversion
• Pb-Free (RoHS Compliant)
• Set-top Boxes
• FPGA Power and STB Power
• DVD and HDD Drives
• LCD Panels, TV Power
• Cable Modems
100
EFFICIENCY (%)
90
12VOUT 1MHz
80
70
60
50
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD, VIN = 28V, TA = +25°C
September 22, 2011
FN6676.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL85033
Pin Configuration
PGOOD1
FS
NC
SGND
SYNCIN
SYNCOUT
PGOOD2
ISL85033
(28 LD TQFN)
TOP VIEW
28
27
26
25
24
23
22
COMP1
1
21 COMP2
FB1
2
20 FB2
SS1
3
19 SS2
PGND1
4
BOOT1
5
17 BOOT2
PHASE1
6
16 PHASE2
PHASE1
7
15 PHASE2
18 PGND2
9
10
11
12
13
VIN1
EN1
VCC
EN2
VIN2
14
VIN2
8
VIN1
PD
Pin Descriptions
PIN NUMBER
SYMBOL
1, 21
COMP1, COMP2
2, 20
FB1, FB2
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB.
In addition, the PWM regulator’s power-good and undervoltage protection circuits use FB1/2 to monitor the
regulator output voltage.
3, 19
SS1, SS2
Soft-Start pins for each controller. The SS1/2 pins control the soft-start and sequence of their respective
outputs. A single capacitor from the SS pin to ground determines the output ramp rate. See the “Output
Tracking and Sequencing” on page 16 for soft-start and output tracking/sequencing details. If SS pins are
tied to VCC, an internal soft-start of 2ms will be used.
4, 18
PGND1, PGND2
Power ground connections. Connect directly to the system GND plane.
5, 17
BOOT1, BOOT2
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external capacitor from this pin to
PHASE.
6, 7, 15, 16
PHASE1, PHASE2
Switch node output. It connects the source of the internal power MOSFET with the external output inductor
and with the cathode of the external diode.
8, 9, 13, 14
VIN1, VIN2
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator
that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from each VIN to GND and
close to the IC for decoupling.
10, 12
EN1, EN2
PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to ground. When
the voltage on this pin rises above 2V, the PWM controller is enabled.
11
VCC
Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7µF ceramic capacitor.
This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).
23
SYNCOUT
2
PIN DESCRIPTION
COMP1/COMP2 is the output of the error amplifier.
Synchronization output. Provides a signal that is the inverse of the SYNCIN signal.
FN6676.4
September 22, 2011
ISL85033
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
PIN DESCRIPTION
24
SYNCIN
Connect to an external signal for synchronization from 300kHz to 2MHz (negative edge trigger). SYNCIN is
not allowed to be floating.
When SYNCIN = logic 0, PHASE1 and PHASE2 are running at 180° out-of-phase.
When SYNCIN = logic 1, PHASE1 and PHASE2 are running at 0° in-phase.
When SYNCIN = an external clock, PHASE1 and PHASE2 are running at 180° out-of-phase.
External SYNC frequency applied to the SYNCIN pin should be at least 2.4 times the internal switching
frequency setting.
25
SGND
26
NC
This is a no connection pin.
27
FS
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for
adjustable frequency from 300kHz to 2MHz.
22, 28
PGOOD1, PGOOD2
-
PD
Signal ground connections. The exposed pad must be connected to SGND and soldered to the PCB. All
voltage levels are measured with respect to this pin.
Open drain power-good output that is pulled to ground when the output voltage is below regulation limits
or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
The exposed pad must be connected to the system GND plane with as many vias as possible for proper
electrical and thermal performance.
Typical Application Schematics
R6
8.06k
FB2
COMP2
C4
68pF
VCC
VCC
SS1 3
VCC
PGOOD2
PGOOD1
L2
7µH
VOUT2
3A
R2
8.06k
C5
470pF
C2
470pF
R8
69.8k
R4
69.8k
21
20
FS 27
SS2 19
C1
68pF
1
2
8/9 VIN1
13/14
C72
ISL85033
28
PHASE2
6/7
C12
10nF
C8
10nF
VOUT1
3A
C9
47µF
D1
B340B
11
VCC
10 25
EN1
26
SGND
12
NC
PGND1/2
23
SYNCOUT
SYNCIN
24
4/18
BOOT2 17
L1
7µH
PHASE1
5 BOOT1
EN2
D2
B340B
C71
20µF
VIN2
10µF
22
15/16
C13
47µF
VOUT1
R1
42.2k
FB1
R5
25.5k
COMP1
VOUT2
4.7µF
FIGURE 2. DUAL 3A OUTPUT (VIN RANGE FROM 4.5V TO 28V)
3
FN6676.4
September 22, 2011
ISL85033
Typical Application Schematics (Continued)
FB2
VOUT1
R5
42.2k
COMP2
C5
1nF
20
VCC
FS
SS2
SS1
Css1
47nF
PHASE2
L2
7µH
FB1
COMP1
FB2
1
2
27
8/9
19
13/14
3
PGOOD2 22
PGOOD1 28
VOUT1
6/7
15/16
10
25
C72
VOUT1
6A
PHASE1
BOOT1
C8
10nF
L1
7µH
D1
B340B
C9
47µF
11
VCC
26
SGND
12
EN1
23
NC
24
4/18
5
17
EN2
BOOT2
PGND1/2
B340B
C71
20µF
VIN2
10µF
C12
10nF
D2
VIN1
ISL85033
SYNCIN
C13
47µF
21
SYNCOUT
Css2
47nF
R8
34k
COMP2
R7
0
FB2
C4
68pF
R6
8.06k
4.7µF
FIGURE 3. SINGLE 6A OUTPUT (VIN RANGE FROM 4.5V TO 28V) CURRENT SHARING
4
FN6676.4
September 22, 2011
ISL85033
BOOT2
COMP2
FB2
PGOOD2
Functional Block Diagram
VCC
5MΩ
BOOT UV
DETECTION
+
-
VCC
-10%
SOFT-START
CONTROL
VOLTAGE
MONITOR
VIN2
CSA2
+
-
SS2
EA
+
-
COMP2
0.8V
REFERENCE
FAULT
MONITOR
EN2
GATE
DRIVE
CSA2
VIN1
LDO
VCC = 5V
BOOT
REFRESH
CONTROL
PGND2
+
SLOPE COMP
POWER-ON
RESET
MONITOR
PHASE2
CSA2
VIN1
THERMAL
MONITOR
+150°C
SYNCOUT
CSA1
FS
OSCILLATOR
SYNCIN
CSA1
+
SLOPE COMP
VIN1
CSA1
EN1
FAULT
MONITOR
0.8V
REFERENCE
DRIVE
GATE
COMP1
+
CONTROL
SOFT-START
-10%
PGND1
BOOT UV
DETECTION
BOOT1
SGND
COMP1
FB1
VCC
5MΩ
PGOOD1
VCC
PHASE1
BOOT
REFRESH
CONTROL
+
SS1
VCC
EA
+
MONITOR
VOLTAGE
EPAD GND
5
FN6676.4
September 22, 2011
ISL85033
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL85033IRTZ
PART
MARKING
850 33IRTZ
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
28 Ld TQFN
PKG.
DWG. #
L28.4x4
NOTES:
1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85033. For more information on MSL please see techbrief TB363.
6
FN6676.4
September 22, 2011
ISL85033
Table of Contents
Absolute Maximum Ratings ...............................................................................................................................................................8
Thermal Information ...........................................................................................................................................................................8
Recommended Operating Conditions ...............................................................................................................................................8
Electrical Specifications ....................................................................................................................................................................8
Detailed Description ........................................................................................................................................................................ 16
Operation Initialization ................................................................................................................................................................... 16
Power-On Reset and Undervoltage Lockout ....................................................................................................................................................... 16
Enable and Disable................................................................................................................................................................................................. 16
Power Good ............................................................................................................................................................................................................. 16
Output Voltage Selection....................................................................................................................................................................................... 16
Output Tracking and Sequencing.................................................................................................................................................... 16
Protection Features ..........................................................................................................................................................................17
Buck Regulator Overcurrent Protection .............................................................................................................................................................. 17
Thermal Overload Protection ................................................................................................................................................................................ 18
BOOT Undervoltage Protection ............................................................................................................................................................................. 18
Application Guidelines .................................................................................................................................................................... 18
Operating Frequency .............................................................................................................................................................................................. 18
Synchronization Control......................................................................................................................................................................................... 18
Output Inductor Selection...................................................................................................................................................................................... 18
Buck Regulator Output Capacitor Selection....................................................................................................................................................... 18
Current Sharing Configuration .............................................................................................................................................................................. 19
Input Capacitor Selection ...................................................................................................................................................................................... 19
Loop Compensation Design .................................................................................................................................................................................. 19
Theory of Compensation........................................................................................................................................................................................ 20
PWM Comparator Gain Fm ................................................................................................................................................................................... 20
Power Stage Transfer Functions .......................................................................................................................................................................... 20
Rectifier Selection .................................................................................................................................................................................................. 21
Power Derating Characteristics............................................................................................................................................................................ 22
Layout Considerations ........................................................................................................................................................................................... 22
Revision History ............................................................................................................................................................................... 24
Products............................................................................................................................................................................................ 24
Package Outline Drawing ................................................................................................................................................................ 25
7
FN6676.4
September 22, 2011
ISL85033
Absolute Maximum Ratings
Thermal Information
VIN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V
PHASE1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT1/2 to PHASE1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
SYNCIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
EN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
PGOOD1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
COMP1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
VCC to GND Short Maximum Duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s
SYNCOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
SS1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .2.2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 4, 5) . . . . . . . . . . . . . .
38
3
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 28V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TA = -40°C to +85°C, VIN = 4.5V to 28V, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
28
V
2.2
mA
SUPPLY VOLTAGE
VIN Voltage Range
VIN
VIN Quiescent Supply Current
IQ
4.5
1.2
VIN Shutdown Supply Current
ISD
EN1/2 = 0V
VCC Voltage
VCC
VIN = 12V; IOUT = 0mA
20
45
µA
4.5
5.1
5.6
V
3.9
4.4
Falling Edge
3.2
3.7
FS = VCC
420
500
POWER-ON RESET
VIN POR Threshold
Rising Edge
V
V
OSCILLATOR
Nominal Switching Frequency
FSW
FS Voltage
VFS
Switching Frequency
kHz
300
kHz
Resistor from FS to GND = 40.2kΩ
2000
kHz
FS = 100kΩ
780
SYNCIN = 600kHz
1.2MHz ≤ SYNCIN ≤ 4MHz
Minimum Off-Time
580
Resistor from FS to GND = 383kΩ
800
820
300
600
tOFF
mV
kHz
2000
130
kHz
ns
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
gm
FB1, FB2 Leakage Current
125
205
285
µA/V
10
100
nA
0.18
0.21
0.24
V/A
0.792
0.8
0.808
V
1.5
2.5
3.5
ms
1.4
2
2.6
µA
VFB = 0.8V
Current Sense Amplifier Gain
RT
Reference Voltage
Soft-Start Ramp Time
SS1/2 = VDD
Soft-Start Charging Current
ISS
8
FN6676.4
September 22, 2011
ISL85033
Electrical Specifications TA = -40°C to +85°C, VIN = 4.5V to 28V, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
91
94
82.5
85.5
%
%
UNITS
POWER-GOOD
PG1, PG2 Trip Level PG to PGOOD1,
PGOOD2
Rise
PG1, PG2 Propagation Delay
Percentage of the soft-start time
10
PG1, PG2 Low Voltage
ISINK = 3mA
100
Fall
%
300
mV
-1
1
µA
0.8
V
Float Level
1.0
1.4
V
High Level
2
ENABLE INPUT
EN1, EN2 Leakage Current
EN1/2 = 0V/5V
EN1, EN2 Input Threshold Voltage
Low Level
V
SYNC INPUT/OUTPUT
SYNCIN Input Threshold
Falling Edge
SYNCIN Leakage Current
1.1
1.4
Rising Edge
1.6
Hysteresis
200
SYNCIN = 0V/5V
SYNCIN Pulse Width
10
V
1.9
1000
100
SYNCOUT Phase-shift to SYNCIN
Measured from rising edge to rising
edge, if duty cycle is 50%
SYNCOUT Frequency Range
ISYNCOUT = 3mA
VCC - 0.3
SYNCOUT Output Voltage Low
nA
ns
180
600
SYNCOUT Output Voltage High
V
mV
°
4000
VCC -0.08
0.08
kHz
V
0.3
V
FAULT PROTECTION
Thermal Shutdown Temperature
TSD
Rising Threshold
150
°C
THYS
Hysteresis
20
°C
Overcurrent Protection Threshold
(Note 7)
4.1
OCP Blanking Time
5.1
6.1
60
A
ns
POWER MOSFET
Highside
RHDS
IPHASE = 100mA
75
Internal BOOT1, BOOT2 Refresh Lowside
RLDS
IPHASE = 100mA
1
tRISE
VIN = 25V
PHASE Leakage Current
EN1/2 = PHASE1/2 = 0V
PHASE Rise Time
150
mΩ
Ω
300
10
nA
ns
NOTES:
6. Test Condition: VIN = 28V, FB forced above regulation point (0.8V), no switching, and power MOSFET gate charging current not included.
7. Established by both current sense amplifier gain test and current sense amplifier output test @ IL = 0A.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9
FN6676.4
September 22, 2011
ISL85033
Typical Performance Curves
100
100
90
90
80
EFFICIENCY (%)
EFFICIENCY (%)
Circuit of Figure 2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
12VOUT 1MHz
9VOUT 1MHz
70
5VOUT 500kHz
60
3.3VOUT 500kHz
5VOUT
70
3.3VOUT
60
50
50
1.8VOUT 300kHz
40
0.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
2.5
40
0.0
3.0
90
3.5
POWER DISSIPATION (W)
4.2
80
9VIN
12VIN
1.0
1.5
2.0
2.5
3.0
FIGURE 5. EFFICIENCY vs LOAD, TA = +25°C, FSW = 500kHz,
VIN = 12V
100
70
0.5
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD, TA = +25°C, VIN = 28V
EFFICIENCY (%)
80
28VIN
60
50
2.8
2.1
12VIN
1.4
28VIN
0.7
9VIN
40
0
0.0
1
2
3
4
OUTPUT LOAD (A)
5
6
4.8
5.04
4.0
5.03
3.2
2.4
1.6
12VIN
0.8
28VIN
0.0
0
1
2
3
4
OUTPUT LOAD (A)
9VIN
5
FIGURE 8. POWER DISSIPATION vs LOAD, TA = +85°C,
CURRENT SHARING 5VOUT, FSW = 500kHz
10
6
1
2
3
4
OUTPUT LOAD (A)
5
6
FIGURE 7. POWER DISSIPATION vs LOAD, TA = +25°C,
CURRENT SHARING 5VOUT, FSW = 500kHz
OUTPUT VOLTAGE (V)
POWER DISSIPATION (W)
FIGURE 6. EFFICIENCY vs LOAD, TA = +25°C, CURRENT SHARING
5VOUT, FSW = 500kHz
0
5.02
12VIN
5.01
9VIN
5.00
28VIN
4.99
4.98
0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
2.5
3.0
FIGURE 9. VOUT REGULATION vs LOAD, CHANNEL 1,
TA = +25°C, 5VOUT, FSW = 500kHz
FN6676.4
September 22, 2011
ISL85033
Typical Performance Curves
5.04
3.329
5.03
3.328
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Circuit of Figure 2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
5.02
5.01
5.00
9VIN
28VIN
12VIN
4.99
4.98
0
1
2
3
4
5
3.326
18VIN
3.325
3.323
3.322
3.320
0
6
28VIN
12VIN
0.5
1.0
5.02
5.03
5.01
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.04
5.02
5.01
3A
2A
0A
4.99
4.98
0
5
10
15
2.0
2.5
3.0
FIGURE 11. VOUT REGULATION vs LOAD, CHANNEL 2, TA = +25°C,
3.3VOUT, FSW = 500kHz
FIGURE 10. VOUT REGULATION vs LOAD, CURRENT SHARING,
TA = +25°C, 5VOUT, FSW = 500kHz
5.00
1.5
OUTPUT LOAD (A)
OUTPUT LOAD (A)
20
25
30
5.00
0A
4.99
4.98
4A
6A
4.97
4.96
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN, CHANNEL 1,
TA = +25°C, 5VOUT, FSW = 500kHz
FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN, CURRENT
SHARING, TA = +25°C, 5VOUT, FSW = 500kHz
3.340
OUTPUT VOLTAGE (V)
3.335
LX1 5V/DIV
3.330
3.325
VOUT1 RIPPLE 20mV/DIV
3.320
0A
3.315
3.310
0
5
10
2A
15
3A
20
IL1 0.1A/DIV
25
30
INPUT VOLTAGE (V)
FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN, CHANNEL 2,
TA = +25°C, 3.3VOUT, FSW = 500kHz
11
FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
FN6676.4
September 22, 2011
ISL85033
Typical Performance Curves
Circuit of Figure 2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
LX1 5V/DIV
LX2 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
IL1 0.2A/DIV
IL2 0.1A/DIV
FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
(VIN = 9V)
LX1 5V/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
LX2 5V/DIV
VOUT1 RIPPLE 20mV/DIV
IL1 1A/DIV
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1
VOUT2 RIPPLE 20mV/DIV
IL2 1A/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2
LX2 10V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
LX1 10V/DIV
IL1 2A/DIV
FIGURE 20. STEADY STATE OPERATION WITH FULL LOAD CURRENT
SHARING
12
FIGURE 21. LOAD TRANSIENT CHANNEL 1
FN6676.4
September 22, 2011
ISL85033
Typical Performance Curves
Circuit of Figure 2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
EN1 5V/DIV
VOUT1 2V/DIV
VOUT2 RIPPLE 20mV/DIV
IL1 0.5A/DIV
PG1 5V/DIV
IL2 2A/DIV
FIGURE 22. LOAD TRANSIENT CHANNEL 2
EN2 5V/DIV
VOUT2 2V/DIV
IL2 0.5A/DIV
PG2 5V/DIV
FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 2
FIGURE 23. SOFT-START WITH NO LOAD CHANNEL 1
EN1 5V/DIV
VOUT1 2V/DIV
IL1 2A/DIV
PG1 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD CHANNEL 1
EN2 5V/DIV
VOUT2 2V/DIV
EN1 5V/DIV
VOUT1 1V/DIV
IL2 2A/DIV
IL1 0.5A/DIV
PG2 5V/DIV
PG 5V/DIV
FIGURE 26. SOFT-START AT FULL LOAD CHANNEL 2
13
FIGURE 27. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
FN6676.4
September 22, 2011
ISL85033
Typical Performance Curves
Circuit of Figure 2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
VOUT1 2V/DIV
EN2 5V/DIV
VOUT2 2V/DIV
VOUT2 0.5V/DIV
EN1, 2 2V/DIV
IL2 0.5A/DIV
PG 5V/DIV
FIGURE 28. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
FIGURE 29. INDEPENDENT START-UP SEQUENCING AT NO LOAD
VOUT1 2V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
VOUT2 2V/DIV
EN1, 2 2V/DIV
FIGURE 30. RATIOMETRIC START-UP SEQUENCING AT NO LOAD
LX1 10V/DIV
EN1, 2 2V/DIV
FIGURE 31. ABSOLUTE START-UP SEQUENCING AT NO LOAD
LX1 10V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
LX2 10V/DIV
LX2 10V/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 32. STEADY STATE OPERATION CHANNEL 1 AT FULL LOAD WITH
SYNC FREQUENCY = 4MHz
14
FIGURE 33. STEADY STATE OPERATION CHANNEL 2 AT FULL LOAD WITH
SYNC FREQUENCY = 4MHz
FN6676.4
September 22, 2011
ISL85033
Typical Performance Curves
Circuit of Figure 2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE1 10V/DIV
IL1 2A/DIV
VOUT1 2V/DIV
PHASE1 10V/DIV
VOUT1 2V/DIV
IL1 2A/DIV
PG1 5V/DIV
PG1 5V/DIV
FIGURE 34. OUTPUT SHORT CIRCUIT CHANNEL 1
PHASE2 10V/DIV
IL2 2A/DIV
VOUT2 2V/DIV
FIGURE 35. OUTPUT SHORT CIRCUIT HICCUP AND RECOVERY FOR
CHANNEL 1
PHASE2 10V/DIV
VOUT2 2V/DIV
IL2 2A/DIV
PG2 5V/DIV
PG2 5V/DIV
FIGURE 36. OUTPUT SHORT CIRCUIT CHANNEL 2
15
FIGURE 37. OUTPUT SHORT CIRCUIT HICCUP AND RECOVERY FOR
CHANNEL 2
FN6676.4
September 22, 2011
ISL85033
Detailed Description
The ISL85033 combines a standard buck PWM controller with an
integrated switching MOSFET. The buck controller drives an
internal N-Channel MOSFET and requires an external diode to
deliver load current up to 3A. A Schottky diode is recommended
for improved efficiency and performance over a standard diode.
The standard buck regulator can operate from an unregulated DC
source, such as a battery, with a voltage ranging from +4.5V to
+28V. The converter output can be regulated to as low as 0.8V.
These features make the ISL85033 ideally suited for FPGA,
set-top boxes, LCD panels, DVD drives, and wireless chipset
power applications.
The ISL85033 employs a peak current mode control loop which
simplifies feedback loop compensation and rejects input voltage
variation. External feedback loop compensation allows flexibility
in output filter component selection. The regulator switches at a
default 500kHz and it can be adjusted from 300kHz to 2MHz
with a resistor from FS to GND. The ISL85033 is also
synchronizable from 300kHz to 2MHz.
forces PG low until the fault condition is cleared by attempts to
soft-start. There is an internal 5MΩ internal pull-up resistor.
Output Voltage Selection
The regulator output voltages is easily programmed using an
external resistor divider to scale VOUT relative to the internal
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 38.
The output voltage programming resistor, R2, depends on the
value chosen for the feedback resistor, R3, and the desired
output voltage, VOUT, of the regulator. Equation 1 describes the
relationship between VOUT and resistor values. R3 is often
chosen to be in the 1kΩ to 10kΩ range.
R 2 = ( V OUT – 0.8 ) • R 3 ⁄ 0.8
If the desired output voltage is 0.8V, then R3 is left unpopulated
and R2 is zero ohm.
VOUT
Operation Initialization
FB
EA
R2
+
-
The power-ON reset circuitry and enable inputs prevent false
start-up of the PWM regulator output. Once all input criteria are
met, the controller soft-starts the output voltage to the
programmed level.
(EQ. 1)
R3
0.8V
REFERENCE
Power-On Reset and Undervoltage Lockout
The ISL85033 automatically initializes upon receipt of input
power supply. The power-on reset (POR) function continually
monitors VIN1 voltage. While below the POR threshold, the
controller inhibits switching of the internal power MOSFET. Once
exceeded, the controller initializes the internal soft-start circuitry.
If VIN1 supply drops below their falling POR threshold during softstart or operation, the buck regulator is disabled until the input
voltage returns.
Enable and Disable
When EN1 and EN2 are pulled low, the device enters shutdown
mode and the supply current drops to a typical value of 20µA. All
internal power devices are held in a high-impedance state while
in shutdown mode.
The EN pin enables the controller of the ISL85033. When the
voltage on the EN pin exceeds its logic rising threshold, the
controller initiates the 2ms soft-start function for the PWM
regulator. If the voltage on the EN pin drops below the falling
threshold, the buck regulator shuts down.
Power Good
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the FB
pin. PG is actively held low when EN is low and during the buck
regulator soft-start period. After the soft-start period terminates,
PG becomes high impedance as long as the output voltage
(monitored on the FB pin) is above 90% of the nominal regulation
voltage set by FB. When VOUT drops 10% below the nominal
regulation voltage, the ISL85033 pulls PG low. Any fault condition
16
FIGURE 38. EXTERNAL RESISTOR DIVIDER
Output Tracking and Sequencing
Output tracking and sequencing between channels can be
implemented by using the SS1 and SS2 pins. Figures 39, 40 and
41 show several configurations for output tracking/sequencing
for a 2.5V and 1.8V application. Independent soft-start for each
channel is shown in Figure 39 and measured in Figure 29. The
output ramp-time for each channel (tSS) is set by the soft-start
capacitor (CSS).
C SS [ μF ] = 2.5*t SS ( s )
(EQ. 2)
Ratiometric tracking is achieved in Figure 40 by using the same
value for the soft-start capacitor on each channel; it is measured
in Figure 30.
By connecting a feedback network from VOUT1 to the SS2 pin
with the same ratio that sets VOUT2 voltage, absolute tracking
shown in Figure 41 is implemented. The measurement is shown
in Figure 31. If the output of Channel 1 is shorted to GND, it will
enter overcurrent hiccup mode, SS2 will be pulled low through
the added resistor between VOUT1 and SS2 and this will force
Channel 2 into hiccup as well. If the output of Channel 2 is
shorted to GND with VOUT1 in regulation, it will enter overcurrent
hiccup mode with a very short hiccup waiting time. The reason is
that VOUT1 is still in regulation and can pull-up SS2 very quickly
via the resistor added between VOUT1 and SS2.
FN6676.4
September 22, 2011
ISL85033
Figure 42 illustrates output sequencing. When EN1 is high and
EN2 is floating, OUT1 comes up first and OUT2 won't start until
OUT1 > 90% of its regulation point. If EN1 is floating and EN2 is
high, OUT2 comes up first and OUT1 won't start until OUT2 > 90%
of its regulation point. If EN1 = EN2 = high, OUT1 and OUT2 come
up at the same time. Please refer to Table 1 for conditions
related to Figure 42 (Output Sequencing).
VOUT1
SS1
C1
0.22µF
SS2
ISL85033
VOUT2
TABLE 1. OUTPUT SEQUENCING
EN2
VOUT1
VOUT2
High
Floating
First
After VOUT1 > 90%
Floating
High
After VOUT2 > 90%
First
High
High
Same time
as VOUT2
Same time
as VOUT1
Floating Floating
C1
0.1µF
NOTE
R2
8.06k
Not
Allowed
VOUT1
R1
25.5k
FIGURE 41. ABSOLUTE START-UP
5.0V
C3
C3
C1
0.1µF
ISL85033
VOUT2
5.0V
VOUT1
SS1
SS2
C2
0.22µF
3.3V
C4
EN1
SS1
5.0V
C3
SS2
3.3V
C4
C2
0.1µF
EN1
ISL85033
VOUT2
EN2
3.3V
C4
FIGURE 39. INDEPENDENT START-UP
FIGURE 42. OUTPUT SEQUENCING
VOUT1
SS1
5.0V
C3
C1
0.1µF
The ISL85033 limits the current in all on-chip power devices.
Overcurrent protection limits the current on the two buck
regulators and internal LDO for VCC.
SS2
ISL85033
VOUT2
3.3V
C4
C2
0.1µF
FIGURE 40. RATIOMETRIC START-UP
Protection Features
Buck Regulator Overcurrent Protection
During the PWM on-time, the current through the internal
switching MOSFET is sampled and scaled through an internal
pilot device. The sampled current is compared to a nominal 5A
overcurrent limit. If the sampled current exceeds the overcurrent
limit reference level, an internal overcurrent fault counter is set
to 1 and an internal flag is set. The internal power MOSFET is
immediately turned off and will not be turned on again until the
next switching cycle.
The protection circuitry continues to monitor the current and
turns off the internal MOSFET as described. If the overcurrent
condition persists for 17 sequential clock cycles, the overcurrent
fault counter overflows indicating an overcurrent fault condition
exists. The regulator is shut down and power-good goes low.
The buck controller attempts to recover from the overcurrent
condition after waiting 8 soft-start cycles. The internal
overcurrent flag and counter are reset. A normal soft-start cycle
is attempted and normal operation continues if the fault
17
FN6676.4
September 22, 2011
ISL85033
condition has cleared. If the overcurrent fault counter overflows
during soft-start, the converter shuts down and this hiccup mode
operation repeats.
Thermal Overload Protection
Thermal overload protection limits maximum junction
temperature in the ISL85033. When the junction temperature
(TJ) exceeds +150°C, a thermal sensor sends a signal to the fault
monitor.
The fault monitor commands the buck regulator to shut down.
When the junction temperature has decreased by 20°C, the
regulator will attempt a normal soft-start sequence and return to
normal operation. For continuous operation, the +125°C
junction temperature rating should not be exceeded.
BOOT Undervoltage Protection
If the BOOT capacitor voltage falls below 2.5V, the BOOT
undervoltage protection circuit will pull the phase pin low through
a 1Ω switch for 400ns to recharge the capacitor. This operation
may arise during long periods of no switching as in no load
situations.
Application Guidelines
The ISL85033 operates at a default switching frequency of
500kHz if FS is tied to VCC. Tie a resistor from FS to GND to
program the switching frequency from 300kHz to 2MHz, as
shown in Equation 3.
(EQ. 3)
Where:
t is the switching period in µs.
300
RFS (kΩ)
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNCIN pin. The falling edge on
the SYNCIN triggers the rising edge of PHASE1/2. The switching
frequency for each output is half of the SYNCIN frequency.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, ΔI. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 4:
V IN – V OUT V OUT
L = ---------------------------- × ------------Fs × ΔI
V IN
(EQ. 4)
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it will not saturate in
overcurrent conditions.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
Operating Frequency
R FS [ kΩ ] = 122kΩ∗ ( t – 0.17μs )
Synchronization Control
200
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
100
0
500
750
1000
1250
1500
FS (kHz)
FIGURE 43. RFS SELECTION vs FS
1750
2000
For the ceramic capacitors (low ESR): =
ΔI
V OUTripple = ----------------------------------8∗ F SW∗ C OUT
(EQ. 5)
where ΔI is the inductor’s peak to peak ripple current, FSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = ΔI*ESR
18
(EQ. 6)
FN6676.4
September 22, 2011
ISL85033
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The following equation
determines the required output capacitor value in order to
achieve a desired overshoot relative to the regulated voltage.
If capacitors other than MLCC are used, attention must be paid to
ripple and surge current ratings.
I RMS
------------ =
Io
D – D2
(EQ. 9)
where D = VO/VIN
The input ripple current is graphically represented in Figure 45.
0.6
I OUT 2 * L
C OUT = ------------------------------------------------------------------------------------V OUT 2 * ( V OUTMAX ⁄ V OUT ) 2 – 1 )
(EQ. 7)
0.5
I OUT 2 * L
C OUT = ---------------------------------------------------V OUT 2 * ( 1.05 2 – 1 )
(EQ. 8)
0.4
IRMS/IO
where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load. For an overshoot of 5%,
the equation becomes:
0.3
0.2
The graph in Figure 44 shows the relationship of COUT and %
overshoot at 3 different output voltages. L is assumed to be 7µH
and IOUT is 3A.
0.1
0
0
0.2
0.4
0.6
0.8
D
FIGURE 45. IRMS/IO vs DUTY CYCLE
COUT (µF)
80
A minimum of 10µF ceramic capacitance is required on each VIN
pin. The capacitors must be as close to the IC as physically
possible. Additional capacitance may be used.
60
3.3VOUT
Loop Compensation Design
40
20
0
1.02
5VOUT
ISL85033 uses a constant frequency current mode control
architecture to achieve simplified loop compensation and fast
loop transient response.
12VOUT
1.04
1.06
1.08
1.10
VOUTMAX/VOUT
FIGURE 44. COUT vs OVERSHOOT VOUTMAX/VOUT
Current Sharing Configuration
In current sharing configuration, FB1 is connected to FB2, EN1 to
EN2, COMP1 to COMP2 and VOUT1 to VOUT2 as shown in
Figure 3. As a result, the equivalent gm doubles its single
channel value. Since the two channels are out-of-phase, the
frequency will be 2X the channel switching frequency. Ripple
current cancellation will reduce the ripple current seen by the
output capacitors and thus lower the ripple voltage. This results
in the ability to use less capacitance than would be required by a
single phase design of similar rating. Ripple current cancellation
also reduces the ripple current seen at the input capacitors.
Input Capacitor Selection
To reduce the resulting input voltage ripple and to minimize EMI by
forcing the very high frequency switching current into a tight local loop,
an input capacitor is required. The input capacitor must have adequate
ripple current rating which can be approximated by the Equation 9.
19
The compensator schematic is shown in Figure 47. As mentioned
in the COUT selection, ISL85033 allows the usage of low ESR
output capacitor. Choice of the loop bandwidth fc is somewhat
arbitrary but should not exceed 1/4 of the switching frequency.
As a starting point, the lower of 100kHz or 1/6 of the switching
frequency is reasonable. The following equations determine
initial component values for the compensation, allowing the
designer to make the selection with minimal effort. Further detail
is provided in “Theory of Compensation” on page 20 to allow fine
tuning of the compensator.
Compensation resistor R1 is given by Equation 10:
2πf c V o C o R T
R 1 = --------------------------------g m V FB
(EQ. 10)
which when applied to ISL85033 becomes:
R 1 [ kΩ ] = 0.008247∗ f c∗ V o∗ C o
(EQ. 11)
where Co is the output capacitor value [µF], fc = loop bandwidth
[kHz] and Vo is the output voltage [V].
Compensation capacitors C1 [nF], C2 [pF] are given by
Equation 12:
3
6
C o × V o × ( 10 )
C o × R c × ( 10 )
C 1 = ---------------------------------------- ,C 2 = ---------------------------------------Io × R1
R1
(EQ. 12)
FN6676.4
September 22, 2011
ISL85033
where Io [A] is the output load current, R1 (Ω) and Rc (Ω) is the
ESR of the output capacitor Co.
Example: Vo = 5V, Io = 3A, fs = 500kHz, fc = 50kHz,
Co = 47µF/Rc = 5mΩ, then the compensation resistance
R1 = 96kΩ.
2
C1 = 815pF, C2 = 2.5pF (There is approximately 3pF parasitic
capacitance from VCOMP to GND; therefore, C2 is optional).
Theory of Compensation
The sensed current signal is injected into the voltage loop to
achieve current mode control to simplify the loop compensation
design. The inductor is not considered as a state variable for
current mode control and the system becomes a single order
system. It is much easier to design a compensator to stabilize the
voltage loop than voltage mode control. Figure 46 shows the
small signal model of the synchronous buck regulator.
^
VIN
+
^i
IN
ILd^
1:D
RT
Transfer function F1(S) from control to output voltage is
calculated in Equation 16:
S
1 + -----------ω esr
v̂ o
F 1 ( S ) = ------ = V in -------------------------------------2
d̂
S
S
------- + -------------- + 1
2 ω Q
o p
ωo
(EQ. 16)
C
1
1
Where ω esr = ------------- ,Q p ≈ Ro -----o- ,ω o = -------------L
LC o
(EQ. 17)
1
Ti(S)
K
Fm
+
Power Stage Transfer Functions
S
1 + -----V in
ωz
Î o
F 2 ( S ) = ---- = ------------------- -------------------------------------Ro + RL 2
d̂
S
S
------- + -------------- + 1
2 ω Q
o
p
ωo
Rc
Ro
Co
d^
2
Transfer function F2(S) from control to inductor current is given
by Equation 17:
VINd^
+
(EQ. 15)
Where Qn and ωn are given by Qn = – --π-, = ω n = πf s .
Rc Co
^
VO
L
In current loop, the current signal is sampled every switching
cycle. Equation 15 shows the transfer function:
S
S
H e ( S ) = ------- + -------------- + 1
2 ω Q
n n
ωn
The compensation capacitors are:
^
iL
CURRENT SAMPLING TRANSFER FUNCTION He(S)
Where ω z = ------------Ro Co .
Current loop gain Ti(S) is expressed as Equation 18:
^
VCOMP
The voltage loop gain with open current loop is calculated in
Equation 19:
-Av(S)
FIGURE 46. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
The PWM comparator gain Fm for peak current mode control is
given by Equation 13:
(EQ. 13)
Where Se is the slew rate of the slope compensation and Sn is
given by Equation 14.
V in – V o
S n = R t -------------------L
(EQ. 14)
Where:
RT is trans-resistance, and is the product of the current sensing
resistance and gain of the current amplifier in current loop.
20
(EQ. 19)
T v ( S ) = KF m F 1 ( S )A v ( S )
The voltage loop gain with current loop closed is given by
Equation 20:
PWM Comparator Gain Fm
1
d̂
F m = ---------------- = -----------------------------( S e + S n )T s
v̂ comp
(EQ. 18)
T i ( S ) = R T F m F 2 ( S )H e ( S )
Tv(S)
He(S)
Tv ( S )
L v ( S ) = ----------------------1 + Ti ( S )
(EQ. 20)
V FB
K = --------- , V
FB is the feedback voltage of the voltage
Vo
Where
error amplifier. If Ti(S)>>1, then Equation 20 can be simplified as
shown in Equation 21:
S
1 + -----------V FB R o + R L
ω esr A v ( S )
1
L v ( S ) = --------- ------------------- ---------------------- --------------- , ω p ≈ ------------RT
Vo
Ro Co
S He ( S )
1 + ------ωp
(EQ. 21)
From Equation 21, it is shown that the system is a single order
system, which has a single pole located at ω P before the half
switching frequency. Therefore, a simple type II compensator can
be easily used to stabilize the system.
FN6676.4
September 22, 2011
ISL85033
Put the compensator zero at 6.6kHz (~1.5x CoRo), and put the
compensator pole at ESR zero, which is 1.45MHz. The
compensator capacitors are:
Vo
R2
C3
V FB
-
V REF
R3
C1 = 470pF, C2 = 3pF (There is approximately 3pF parasitic
capacitance from VCOMP to GND; therefore, C2 is optional).
V COMP
GM
Figure 48A shows the simulated voltage loop gain. It is shown
that it has 80kHz loop bandwidth with 69° phase margin and
15dB gain margin. Optional addition phase boost can be added
to the overall loop response by using C3.
+
R1
C2
C1
60
45
FIGURE 47. TYPE II COMPENSATOR
30
Figure 47 shows the type II compensator and its transfer function
is expressed as Equation 22:
15
S ⎞⎛
S
⎛ 1 + -----------1 + ------------⎞
⎝
gm
ω cz1⎠ ⎝
ω cz2⎠
v̂ comp
A v ( S ) = ---------------- = ------------------- --------------------------------------------------------C1 + C2
S
v̂ FB
S ⎛ 1 + ----------⎞
⎝
ω ⎠
GAIN (dB)
0
(EQ. 22)
cp
-15
-30
Where:
100
1•103
1•104
1•105
1•106
1•105
1•106
FIGURE 48A.
C1 + C2
1
1
ω cz1 = -------------- , ω cz2 = --------------, ω cp = --------------------R1 C1 C2
R1 C1
R2 C3
(EQ. 23)
100
the compensator design goal is:
80
High DC gain
⎛1
1⎞
- f
Loop bandwidth fc: ⎝ --4- to -----10⎠ s
60
Gain margin: >10dB
40
Phase margin: 40°
20
The compensator design procedure is shown in Equation 24:
1
Put compensator zero ω cz1 = ( 1to3 ) --------------R C
(EQ. 24)
O O
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower.
The loop gain Tv(S) at crossover frequency of fc has unity gain.
Therefore, the compensator resistance R1 is determined by
Equation 25:
2πf c V o C o R T
R 1 = --------------------------------g m V FB
(EQ. 25)
where gm is the trans-conductance of the voltage error amplifier,
typically 200µA/V. Compensator capacitor C1 is then given by
Equation 26:
1
1
C 1 = ----------------- ,C 2 = ------------------------R 1 ω cz
2πR 1 f esr
(EQ. 26)
Example: VIN = 12V, Vo = 5V, Io = 3A, fs = 500kHz,
Co = 220µF/5mΩ, L = 5.6µH, gm = 200µs, RT = 0.21,
VFB = 0.8V, Se = 1.1×105V/s, Sn = 3.4×105V/s, fc = 80kHz, then
compensator resistance R1 = 72kΩ.
21
PHASE (°)
0
-20
100
1•103
1•104
FIGURE 48B.
Rectifier Selection
Current circulates from ground to the junction of the external
Schottky diode and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is negative
with respect to ground. This voltage is approximately -0.5V (a
Schottky diode drop) during the off-time. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating factor.
The power dissipation when the Schottky diode conducts is
expressed in Equation 27:
V OUT⎞
⎛
P D [ W ] = I OUT ⋅ V D ⋅ ⎜ 1 – -------------⎟
V IN ⎠
⎝
(EQ. 27)
Where:
VD is the voltage drop of the Schottky diode. Selection of the
Schottky diode is critical in terms of the high temperature
reverse bias leakage current which is very dependent on VIN and
FN6676.4
September 22, 2011
ISL85033
exponentially increasing with temperature. Due to the nature of
reverse bias leakage vs temperature, the diode should be
carefully selected to operate in the worst case circuit conditions.
Catastrophic failure is possible if the diode chosen experiences
thermal runaway at elevated temperatures. Please refer to
Application Note for diode selection.
Power Derating Characteristics
To prevent the ISL85033 from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 28:
(EQ. 28)
T RISE = ( PD ) ( θ JA )
where PD is the power dissipated by the regulator and θJA is the
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by
Equation 29:
(EQ. 29)
T J = ( T A + T RISE )
where TA is the ambient temperature. For the QFN package, the
θJA is +38°C/W.
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C When considering
the thermal design, remember to consider the thermal needs of
the rectifier diode.
MAXIMUM AMBIENT
TEMPERATURE (°C)
The ISL85033 delivers full current at ambient temperatures up
to +85°C if the thermal impedance from the thermal pad
maintains the junction temperature below the thermal shutdown
level, depending on the Input Voltage/Output Voltage
combination and the switching frequency. The device power
dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 49
illustrates the power derating versus ambient temperature for
the ISL85033 EVAL kit. Note that the EVAL kit derating curve is
based on total circuit dissipation, not IC dissipation alone.
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
3
4
5
6
7
8
9 10
ISL85033EVAL1ZB EVAL BOARD
TOTAL POWER DISSIPATION (W)
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the Schottky diode. Any parasitic inductance in
the switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight layout
of the critical components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in the ISL85033
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next, are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 50
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminals to the output
inductor short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
In order to dissipate heat generated by the internal LDO and MOSFET,
the ground pad should be connected to the internal ground plane
through at least four vias. This allows the heat to move away from the IC
and also ties the pad to the ground plane through a low impedance
path.
The switching components should be placed close to the
ISL85033 first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible. Position the
output inductor and output capacitors between the upper and
Schottky diode and the load.
ΘJA = 38°C/W
1
can degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
11
12
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin with
vias tied straight to the ground plane as required.
FIGURE 49. POWER DERATING CURVE
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently between 100kHz
and 600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
22
FN6676.4
September 22, 2011
D1
Cout1
ISL85033
SL85033
.. .. ..
vias
Cin1 Cin2
LX2 trace
L2
D2
Cout2
VOUT2
VOUT2
VIN1
VIN2
VOUT1
Cboot
LX1 trace
Fb2
Cboot
Comp1
Fb1
L1
Comp2
ISL85033
FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
23
FN6676.4
September 22, 2011
ISL85033
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
9/14/11
8/9/11
4/5/11
REVISION
CHANGE
FN6676.4 In the “Pin Descriptions” on page 3, for “SYNCIN”, replaced “Set the internal switching frequency 20% lower than the external
SYNC frequency applied to the SYNCIN pin" with "External SYNC frequency applied to the SYNCIN pin should be at least 2.4
times the internal switching frequency setting"
On page 8, changed parameter name from “Syncronization Frequency” to “Switching Frequency”.
FN6676.3 Converted to new template
Updated Intersil Trademark statement at bottom of page 1 per directive from Legal.
Page 2 in the pin table definition, please add the following sentence to the Pin 11 (VCC) description after “Output of the internal
5V linear regulator. Decouple to PGND with a minimum of 4.7μF ceramic capacitor.”
“This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).”
Page 8 all Absolute Max Ratings that are “5.5” should be changed to “5.9”
10/15/10 FN6676.2 Added the following sentence to the “SYNCIN” description in the “Pin Descriptions” table on page 3:
“Set the internal switching frequency 20% lower than the external SYNC frequency applied to the SYNCIN pin.”
Added the following sentence to “Synchronization Control” on page 18: “The switching frequency for each output is half of the
SYNCIN frequency.”
Revised tape and reel note in “Ordering Information” on page 6 from:
“Add “-T” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications”
to:
“Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications”
This is in order to delineate all tape and reel options.
9/14/10
Corrected Eq. 1 on page 16 from:
R 2 x0.8V
R 3 = ------------------------------V OUT – 0.8V
to:
R 2 = ( V OUT – 0.8 ) • R 3 ⁄ 0.8
Revised preceding paragraph from:
“The output voltage programming resistor, R3, depends on the value chosen for the feedback resistor, R2, and the desired
output voltage, VOUT, of the regulator. Equation 1 describes the relationship between VOUT and resistor values. R2 is often
chosen to be in the 1kΩ to 10kΩ range.”
to:
“The output voltage programming resistor, R2, depends on the value chosen for the feedback resistor, R3, and the desired
output voltage, VOUT, of the regulator. Equation 1 describes the relationship between VOUT and resistor values. R3 is often
chosen to be in the 1kΩ to 10kΩ range.”
6/21/10
FN6676.1 Changed MIN/MAX for “Soft-Start Charging Current” on page 8 from 1.5/2.5µA to 1.4/2.6µA
6/18/10
FN6676.0 Initial Release.
24
FN6676.4
September 22, 2011
ISL85033
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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25
FN6676.4
September 22, 2011
ISL85033
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/06
A
4 . 00
2 . 50
PIN #1 INDEX AREA
CHAMFER 0 . 400 X 45°
0 . 40
22
28
1
0 . 40
15
3 . 20
2 . 50
4 . 00
21
0 . 4 x 6 = 2.40 REF
B
PIN 1
INDEX AREA
7
0 . 10
2X
14
8
0 . 20 ±0 . 05
0 . 10 M C A B
0 . 4 x 6 = 2 . 40 REF
TOP VIEW
3 . 20
BOTTOM VIEW
SEE DETAIL X''
0 . 10 C
(3 . 20)
C
PACKAGE BOUNDARY
MAX. 0 . 80
SEATING PLANE
(28X 0 . 20)
0 . 00 - 0 . 05
0 . 20 REF
0 . 08 C
(3 . 20)
(2 . 50)
SIDE VIEW
(0 . 40)
C
(0 . 40)
0 . 20 REF
5
0 ~ 0 . 05
(2 . 50)
(28X 0 . 60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994.
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
26
FN6676.4
September 22, 2011