ON MTB50P03HDLT4G P-channel power mosfet Datasheet

MTB50P03HDL,
MVB50P03HDLT4G
P-Channel Power MOSFET
50 A, 30 V, Logic Level D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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50 AMPERES
30 VOLTS
RDS(on) = 25 mW
Features
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
•
•
•
•
•
•
P−Channel
D
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured − Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
MVB Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
G
S
4
1
D2PAK
CASE 418B
STYLE 2
2
Symbol
Value
Unit
Drain−Source Voltage
VDSS
30
Vdc
Drain−Gate Voltage (RGS = 1.0 MW)
VDGR
30
Vdc
Gate−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
MARKING DIAGRAM
& PIN ASSIGNMENT
VGS
VGSM
±15
± 20
Vdc
Vpk
4
Drain
ID
ID
50
31
150
Adc
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when
mounted with min. recommended pad size
PD
125
1.0
2.5
W
W/°C
W
Operating and Storage Temperature Range
TJ, Tstg
− 55 to 150
°C
EAS
1250
mJ
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak
IL = 50 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient, when mounted with
the minimum recommended pad size
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
IDM
RqJC
RqJA
RqJA
1.0
62.5
50
TL
260
Apk
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 7
1
3
M
TB
50P03HG
AYWW
1
Gate
MTB50P03H
A
Y
WW
G
2
Drain
3
Source
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
MTB50P03HDL/D
MTB50P03HDL, MVB50P03HDLT4G
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
30
−
−
26
−
−
−
−
−
−
1.0
10
−
−
100
1.0
−
1.5
4.0
2.0
−
−
20.9
25
−
−
0.83
−
1.5
1.3
15
20
−
Ciss
−
3500
4900
Coss
−
1550
2170
Crss
−
550
770
td(on)
−
22
30
tr
−
340
466
td(off)
−
90
117
tf
−
218
300
QT
−
74
100
Q1
−
13.6
−
Q2
−
44.8
−
Q3
−
35
−
−
−
2.39
1.84
3.0
−
trr
−
106
−
ta
−
58
−
Unit
OFF CHARACTERISTICS
(Cpk ≥ 2.0) (Note 3)
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 3.0) (Note 3)
Static Drain−Source On−Resistance
(VGS = 5.0 Vdc, ID = 25 Adc)
(Cpk ≥ 3.0) (Note 3)
Drain−Source On−Voltage (VGS = 5.0 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ =125°C)
VGS(th)
RDS(on)
VDS(on)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)
gFS
Vdc
mV/°C
mW
Vdc
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD= 15 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc, RG = 2.3 W)
Fall Time
Gate Charge (See Figure 8)
(VDS = 24 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 50 Adc, VGS = 0 Vdc)
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 15)
(IS = 50 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
VSD
Vdc
ns
tb
−
48
−
QRR
−
0.246
−
mC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
−
3.5
−
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
−
7.5
−
nH
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
Max limit − Typ
3. Reflects typical values.
Cpk =
3 x SIGMA
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MTB50P03HDL, MVB50P03HDLT4G
TYPICAL ELECTRICAL CHARACTERISTICS
100
TJ = 25°C
VGS = 10 V
8V
80
6V
4V
4.5 V
60
VDS ≥ 5 V
5V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
100
3.5 V
40
3V
20
TJ = -55°C
25°C
100°C
80
60
40
20
2.5 V
0.4
0.2
0.6
0.8
1.0
1.2
1.6
1.4
1.9
2.3
2.7
3.9
3.5
3.1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = 5 V
0.027
0.025
TJ = 100°C
0.023
25°C
0.021
0.019
-55°C
0.017
0.015
0
1.5
2.0
1.8
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
0
0.029
0
20
40
60
80
100
4.3
0.022
VGS = 5 V
TJ = 25°C
0.021
0.020
0.019
0.018
0.017
10 V
0.016
0.015
0
20
40
60
80
100
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.35
1.25
1000
VGS = 0 V
VGS = 5 V
ID = 25 A
I DSS, LEAKAGE (nA)
R DS(on) , DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
0
1.15
1.05
TJ = 125°C
100
0.95
100°C
0.85
-50
10
-25
0
25
50
75
100
125
150
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage
Current versus Voltage
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3
30
MTB50P03HDL, MVB50P03HDLT4G
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring which
is common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a
function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also complicates
the mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to
measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
14000
C, CAPACITANCE (pF)
VDS = 0 V
C
iss
12000
VGS = 0 V
TJ = 25°C
10000
8000
Crss
6000
Ciss
4000
Coss
2000
Crss
0
10
0
5
VGS
5
10
15
20
VDS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
25
30
QT
5
25
VGS
Q1
Q2
4
20
15
3
ID = 50 A
TJ = 25°C
2
10
5
1
Q3
0
0
10
VDS
20
30
40
50
VDD = 30 V
VGS = 10 V
ID = 50 A
TJ = 25°C
tr
tf
0
80
70
60
1000
t, TIME (ns)
6
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
MTB50P03HDL, MVB50P03HDLT4G
td(off)
100
td(on)
10
1
10
QT, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (Ohms)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
I S , SOURCE CURRENT (AMPS)
50
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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5
MTB50P03HDL, MVB50P03HDLT4G
di/dt = 300 A/ms
Standard Cell Density
trr
I S , SOURCE CURRENT
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RqJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
100 ms
1 ms
10
1
0.1
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0
1400
ID = 50 A
1200
1000
800
600
400
200
0
10
100
25
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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MTB50P03HDL, MVB50P03HDLT4G
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RqJC(t)
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
t, TIME (s)
Figure 14. Thermal Response
PD, POWER DISSIPATION (WATTS)
3
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
2.5
2.0
1.5
1
0.5
0
IS
RqJA = 50°C/W
Board material = 0.065 mil FR−4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (°C)
Figure 16. D2PAK Power Derating Curve
Figure 15. Diode Reverse Recovery Waveform
ORDERING INFORMATION
Package
Shipping†
MTB50P03HDLG
D2PAK
(Pb−Free)
50 Units / Rail
MTB50P03HDLT4G
D2PAK
(Pb−Free)
800 / Tape & Reel
MVB50P03HDLT4G*
D2PAK
(Pb−Free)
800 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*MVB Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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MTB50P03HDL, MVB50P03HDLT4G
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
J
G
D 3 PL
0.13 (0.005)
VARIABLE
CONFIGURATION
ZONE
W
H
M
T B
M
N
R
P
L
L
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
U
L
M
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
MTB50P03HDL, MVB50P03HDLT4G
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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MTB50P03HDL/D