HD74HC166 Parallel-load 8-bit Shift Register REJ03D0582-0300 Rev.3.00 Jan 31, 2006 Description This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Features • • • • • • High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC166P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC166FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Clear Shift/Load Clock Inhibit Parallel Clock Serial A ··· H Internal outputs QA L X X X X X L H X L L X X QA0 X a ··· h a H L L H X H H H L L X L H H L X X QA0 H X H QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H: High level L: Low level X: Irrelevant Rev.3.00, Jan 31, 2006 page 1 of 6 QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0 HD74HC166 Pin Arrangement Serial 1 Input 16 VCC A 2 15 Shift/Load B 3 Parallel 14 Input H C 4 13 Output QH D 5 12 G Clock Inhibit 6 11 F Clock 7 10 E GND 8 9 Clear Parallel Inputs Parallel Inputs (Top view) Timing Diagram Clock Clock Inhibit Clear Serial Input Shift/Load Parallel Inputs A H B L C H D L E H F L G H H H Output QH H Serial Shift Clear Rev.3.00, Jan 31, 2006 page 2 of 6 Inhibit Load H L H L H Serial Shift L H L HD74HC166 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Symbol VCC VIN, VOUT Ta Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 tr, tf Unit V V °C ns 0 to 400 Note: Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Iin Quiescent supply current ICC Min 2.0 1.5 4.5 6.0 Ta = 25°C Typ Max Ta = –40 to+85°C Unit Min Max — — 1.5 — 3.15 — — 3.15 — 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — 6.0 5.68 — — 5.63 — 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 6.0 6.0 6.0 — — — — — — 0.26 ±0.1 4.0 — — — 0.33 ±1.0 40 Rev.3.00, Jan 31, 2006 page 3 of 6 Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC166 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax tPHL, tPLH tPHL Setup time tsu Hold time th Pulse width tw Output rise/fall time Input capacitance tTLH, tTHL Cin 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — Rev.3.00, Jan 31, 2006 page 4 of 6 Ta = 25°C Ta = –40 to +85°C Unit Min Typ Max Min Max — — — — — — — — — 150 30 26 100 20 17 5 5 5 80 16 14 — — — — — — — — 14 — — 12 — — 2 — — 1 — — 0 — — 6 — — 5 — 5 5 25 29 175 35 30 150 30 26 — — — — — — — — — — — — 75 15 13 10 — — — — — — — — — 190 38 33 125 25 21 5 5 5 100 20 17 — — — — 4 20 24 220 44 37 190 38 33 — — — — — — — — — — — — 95 19 16 10 Test Conditions MHz ns Clock to QH ns Clear to QH ns Shift/Load to Clock ns Data to Clock ns Clock to Data ns Clock, Clear ns pF HD74HC166 Test Circuit Measurement point CL* Note: CL includes the probe and fig capacitance. Waveforms tW VCC Clear 50% 50% tn tn+1 tn 0V tn+1 VCC Clock 50% 50% 50% 50% 0V tW tsu th tsu th VCC Data 50% 50% 50% 50% 0V tPHL tPLH tPHL VOH Output QH 50% 50% 50% VOL Notes 1. Input wavwform : PRR ≤ 1 MHz㧘Zo = 50 Ω㧘tr ≤ 6 ns㧘tf ≤ 6 ns 2. Propagation delay time (tPLH and tPHL)are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test. 3. tn : bit time before clocking transition. ޓtn+1 : bit time after one clocking transition. ޓtn+8 : bit time after eight clocking transition. Rev.3.00, Jan 31, 2006 page 5 of 6 HD74HC166 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jan 31, 2006 page 6 of 6 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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