327 CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM Features • • • • • • • • • • • • • • • • • • • Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V –5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs JTAG boundary scan Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low-profile JEDEC standard 100-pin TQFP package Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), Global Write (GW), and Data Input Enable (DEN). Asynchronous inputs include the Burst Mode Control (MODE), the Output Enable (OE) and the Match Output Enable (MOE). The data outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Data inputs are registered with Data Input Enable (DEN) and chip enable pins (CE, CE2, and CE2). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1–DQ9. WEH controls DQ10–DQ18. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The CY7C1359C/GVT71256T18 operates from a +3.3V power supply with output power supply being +2.5V or +3.3V. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 8 MB secondary cache. Selection Guide 7C1359A-166 71256T36-6 7C1359A-150 71256T36-6.7 7C1359A-133 71256T36-7.5 7C1359A-100 71256T36-10 Maximum Access Time (ns) 3.5 3.8 4.0 4.5 Maximum Operating Current (mA) 310 275 250 190 Maximum CMOS Standby Current (mA) 20 20 20 20 Cypress Semiconductor Corporation Document #: 38-05120 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 13, 2001 CY7C1359A/GVT71256T18 Functional Block Diagram—256Kx18[1] HIGHER BYTE WRITE WEH# BWE# D Q D Q LOWER BYTE WRITE D Q CE# lo byte write GW# ENABLE CE2 Latch D Q D Q hi byte write WEL# CE2# ZZ Power Down Logic OE# D ADSP# Q MATCH MOE# Compare Input Register DEN# Latch CLK 16 Address Register CLR ADV# A1-A0 Binary Counter & Logic OUTPUT REGISTER D Q Output Buffers ADSC# 256K x 9 x 2 SRAM Array A DQ1DQ18 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05120 Rev. ** Page 2 of 24 CY7C1359A/GVT71256T18 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP Top View NC NC NC CY7C1359A/GVT71256T18 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VCCQ VSSQ NC DQ9 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ MATCH DEN MOE MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCCQ VSSQ NC NC DQ10 DQ11 VSSQ VCCQ DQ12 DQ13 NC VCC NC VSS DQ14 DQ15 VCCQ VSSQ DQ16 DQ17 DQ18 NC VSSQ VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 119-Lead BGA Top View 1 2 3 4 5 6 7 A VCCQ A A ADSP A A VCCQ B NC CE2 A ADSC A CE2 NC C NC A A VCC A A NC D DQ10 NC VSS NC VSS DQ9 NC E NC DQ11 VSS CE VSS NC DQ8 F VCCQ NC VSS OE VSS DQ7 VCCQ G NC DQ12 WEH ADV VSS NC DQ6 H DQ13 NC VSS GW VSS DQ5 NC J VCCQ VCC NC VCC NC VCC VCCQ K NC DQ14 VSS CLK VSS NC DQ4 L DQ15 NC VSS NC WEL DQ3 NC M VCCQ DQ16 VSS BWE VSS MATCH VCCQ N DQ17 NC VSS A1 VSS DQ2 DEN P NC DQ18 VSS A0 VSS MOE DQ1 R NC A MODE VCC NC A NC T NC A A NC A A ZZ U VCCQ TMS TDI TCK TDO NC VCCQ Document #: 38-05120 Rev. ** Page 3 of 24 CY7C1359A/GVT71256T18 Pin Descriptions BGA Pins TQFP Pins Name Type Description 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 A0 A1 A InputSynchronous Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. 5L 3G 93 94 WEL WEH InputSynchronous Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. WEL controls DQ1–DQ9. WEH controls DQ10–DQ18. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. 4M 87 BWE InputSynchronous Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. 4H 88 GW InputSynchronous Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. 4K 89 CLK InputSynchronous Clock: This signal registers the addresses, data, chip enables, write control, and data input enable control input on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. 4E 98 CE InputSynchronous Chip Enable: This active LOW input is used to enable the device and to gate ADSP. 6B 92 CE2 InputSynchronous Chip Enable: This active LOW input is used to enable the device. 2B 97 CE2 inputSynchronous Chip Enable: This active HIGH input is used to enable the device. 4F 86 OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. 4G 83 ADV InputSynchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP InputSynchronous Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. 4B 85 ADSC InputSynchronous Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. 3R 31 MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. 7T 64 ZZ 7N 52 DEN InputSynchronous Data Input Enable: This active LOW input is used to control the update of data input registers. 6M 53 MATCH Output Match Output: MATCH will be HIGH if data in the data input registers match the data stored in the memory array, assuming MOE being LOW. MATCH will be LOW if data do not match. Document #: 38-05120 Rev. ** InputSnooze: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Page 4 of 24 CY7C1359A/GVT71256T18 Pin Descriptions (continued) BGA Pins TQFP Pins Name Type Description 6P 51 MOE Input Match Output Enable: This active LOW asynchronous input enables the MATCH output drivers. 7P, 6N, 6L, 7K, 6H, 7G, 6F, 7E, 6D, 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 DQ1– DQ18 Input/ Output Data Inputs/Outputs: Input data must meet setup and hold times around the rising edge of CLK. 5U 42 TDO Output IEEE 1149.1 test output. LVTTL-level output. 2U 3U 4U 38 39 43 TMS TDI TCK Input IEEE 1149.1 test inputs. LVTTL-level inputs. 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC Supply Power Supply: +3.3V –5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Ground Ground: GND 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4, 11, 20, 27, 54, 61, 70, 77 VCCQ I/O Supply NC - 1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16, 2D, 4D, 7D, 1E, 25, 28-30, 56, 57, 6E, 2F, 1G, 6G, 66, 75, 78, 79, 95, 2H, 7H, 3J, 5J, 96 1K, 6K, 2L, 4L, 7L, 2N, 1P, 1R, 5R, 7R, 1T, 4T, 6U Output Buffer Supply: +2.5V (from 2.375V to VCC) No Connect: These signals are not internally connected. Burst Address Table (MODE = GND) Burst Address Table (MODE = NC/VCC) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 A...A11 A...A10 A...A01 Partial Truth Table for MATCH[2, 3, 4, 5, 6] Operation E WE DEN MOE OE MATCH DQ READ Cycle L H X X L - Q WRITE Cycle L L L X H - D Fill WRITE Cycle L L H X H - High-Z COMPARE Cycle L H L L H Output D Deselected Cycle (MATCH Out) H X X L X H High-Z Deselected Cycle H X X H X High-Z High-Z Notes: 2. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW. 3. E=L is defined as CE=LOW and CE2=LOW and CE2=HIGH. E =H is defined as CE=HIGH or CE2=HIGH or CE2=LOW. WE is defined as [BWE + WEL*WEH]*GW. 4. All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. Document #: 38-05120 Rev. ** Page 5 of 24 CY7C1359A/GVT71256T18 Truth Table[5, 6, 7, 8, 9, 10, 11] Operation Address Used CE ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X X L X X X L-H High-Z Deselected Cycle, Power Down None L X L L X X X X L-H High-Z Deselected Cycle, Power Down None L H X L X X X X L-H High-Z Deselected Cycle, Power Down None L X L H L X X X L-H High-Z Deselected Cycle, Power Down None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D CE2 CE2 ADSP Partial Truth Table for READ/WRITE[12] Function GW BWE WEH WEL READ H H X X READ H L H H WRITE one byte H L L H WRITE all bytes H L L L WRITE all bytes L X X X Notes: 7. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW. 8. WEL enables write to DQ1–DQ9. WEH enables write to DQ10–DQ18. 9. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 10. Suspending burst generates wait cycle. 11. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. 12. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW. Document #: 38-05120 Rev. ** Page 6 of 24 CY7C1359A/GVT71256T18 IEEE 1149.1 Serial Boundary Scan (JTAG) Overview This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAP’s operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP) TCK - Test Clock (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS - Test Mode Select (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. TDI - Test Data In (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 2.) TDO - Test Data Out (OUTPUT) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.) Document #: 38-05120 Rev. ** Performing a TAP Reset The TAP circuitry does not have a Reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state. Test Access Port (TAP) Registers Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAP’s registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for a x36 device and 51 bits for a x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/ PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit’s position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number. Page 7 of 24 CY7C1359A/GVT71256T18 Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. TAP Controller Instruction Set Overview There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Document #: 38-05120 Rev. ** Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device’s input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. Page 8 of 24 CY7C1359A/GVT71256T18 1 TEST-LOGIC RESET 0 0 REUN-TEST/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-IR CAPTURE-DR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-IR EXIT2-DR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Figure 1. TAP Controller State Diagram[13] Note: 13. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05120 Rev. ** Page 9 of 24 CY7C1359A/GVT71256T18 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register x . . . . 2 Boundary Scan Register [14] TDI TAP Controller TDI Figure 2. TAP Controller Block Diagram TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted) Parameter VIH Description Test Conditions Input High (Logic 1) Voltage[15, 16] [15, 16] Min. Max. Unit 2.0 VCC + 0.3 V –0.3 0.8 V VIl Input Low (Logic 0) Voltage ILI Input Leakage Current 0V < VIN < VCC –5.0 5.0 µA ILO Output Leakage Current Output disabled, 0V < VIN < VCCQ –5.0 5.0 µA VOLC LVCMOS Output Low Voltage[15, 17] IOLC = 100 µA 0.2 V VOHC [15, 17] LVCMOS Output High Voltage IOHC = 100 µA VOLT LVTTL Output Low Voltage[15] IOLT = 8.0 mA VOHT [15] IOHT = 8.0 mA LVTTL Output High Voltage VCC – 0.2 V 0.4 2.4 V V Notes: 14. X = 53 for this device. 15. All Voltage referenced to VSS (GND). 16. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as GW, ADSC, etc.) may not have pulse widths less than tKHKL (min.). 17. This parameter is sampled. Document #: 38-05120 Rev. ** Page 10 of 24 CY7C1359A/GVT71256T18 TAP AC Switching Characteristics Over the Operating Range[18, 19] Parameter Description Min. Max Unit Clock tTHTH Clock Cycle Time 20 ns fTF Clock Frequency tTHTL Clock HIGH Time 8 ns tTLTH Clock LOW Time 8 ns tTLQX TCK LOW to TDO Unknown 0 tTLQV TCK LOW to TDO Valid tDVTH TDI Valid to TCK HIGH 5 ns tTHDX TCK HIGH to TDI Invalid 5 ns tMVTH TMS Set-up 5 ns tCS Capture Set-up 5 ns tTHMX TMS Hold 5 ns tCH Capture Hold 5 ns 50 MHz Output Times ns 10 ns Set-up Times Hold Times Notes: 18. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 19. Test conditions are specified using the load in TAP AC Test Conditions. Document #: 38-05120 Rev. ** Page 11 of 24 CY7C1359A/GVT71256T18 TAP Timing and Test Conditions ALL INPUT PULSES TDO 3.0V 50Ω Z0 = 50Ω 20 pF 1.5V VSS 1.0 ns 1.0 ns Vt = 1.5V Figure 5 (a) TAP AC OUTPUT LOAD EQUIVALENT t tTHTH THTL t TLTH TEST CLOCK (TCK) tMVTH tTHMX tDVTH t TEST MODE SELECT (TMS) THDX TEST DATA IN (TDI) t TLQV tTLQX TEST DATA OUT (TDO) Document #: 38-05120 Rev. ** Page 12 of 24 CY7C1359A/GVT71256T18 Identification Register Definitions Instruction Field 512K x 18 Description REVISION NUMBER (31:28) XXXX Reserved for revision number. DEVICE DEPTH (27:23) 00111 Defines depth of 256K words. DEVICE WIDTH (22:18) 00011 Defines width of x18 bits. XXXXXX Reserved for future use. RESERVED (17:12) CYPRESS JEDEC ID CODE (11:1) 00011100100 ID Register Presence Indicator (0) 1 Allows unique identification of DEVICE vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 54 Instruction Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant. IDCODE 001 Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction does not affect device operations. SAMPLE-Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. RESERVED 011 Do not use these instructions; they are reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not affect device operations. This instruction does not implement IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant. RESERVED 101 Do not use these instructions; they are reserved for future use. RESERVED 110 Do not use these instructions; they are reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. Document #: 38-05120 Rev. ** Page 13 of 24 CY7C1359A/GVT71256T18 Boundary Scan Order (continued) Boundary Scan Order Bit# Signal Name TQFP Bump ID Bit# Signal Name TQFP Bump ID 1 A 44 2R 35 CE 98 4E 2 A 45 2T 36 A 99 3A 3 A 46 3T 37 A 100 2A DQ10 8 ID 4 A 47 5T 38 5 A 48 6R 39 DQ11 9 2E 6 A 49 3B 40 DQ12 12 2G 7 A 50 5B 41 DQ13 13 1H NC 14 5R 8 MOE 51 6P 42 9 DEN 52 7N 43 DQ14 18 2K 10 MATCH 53 6M 44 DQ15 19 1L 11 DQ1 58 7P 45 DQ16 22 2M DQ17 23 1N 12 DQ2 59 6N 46 13 DQ3 62 6L 47 DQ18 24 2P 14 DQ4 63 7K 48 MODE 31 3R 15 ZZ 64 7T 49 A 32 2C A 33 3C 16 DQ5 68 6H 50 17 DQ6 69 7G 51 A 34 5C 18 DQ7 72 6F 52 A 35 6C 19 DQ8 73 7E 53 A1 36 4N 6D 54 A0 37 4P 20 DQ9 74 21 A 80 6T 22 A 81 6A 23 A 82 5A 24 ADV 83 4G Voltage on VCC Supply Relative to VSS ..........–0.5V to +4.6V 25 ADSP 84 4A VIN .......................................................... –0.5V to VCC+0.5V 26 ADSC 85 4B Storage Temperature (plastic) ................... –55°C to +150°C 27 OE 86 4F Junction Temperature ............................................... +150°C 28 BWE 87 4M Power Dissipation.......................................................... 1.0W 29 GW 88 4H Short Circuit Output Current........................................ 50 mA 30 CLK 89 4K Operating Range 31 CE2 92 6B 32 WEL 93 5L 33 WEH 94 3G 34 CE2 97 2B Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Range Com’l Ambient Temperature[20] VCC 0°C to +70°C 3.3V −5%/+10% Note: 20. TA is the case temperature. Document #: 38-05120 Rev. ** Page 14 of 24 CY7C1359A/GVT71256T18 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [15, 21] VIHD Input High (Logic 1) Voltage VIH VIl Input Low (Logic 0) Voltage Min. Max. Unit Data Inputs (DQxx) 1.7 VCC+0.3 V All Other Inputs 1.7 4.6 V –0.3 0.8 V –2 2 µA 2 µA [15, 21] [22] ILI Input Leakage Current 0V < VIN < VCC ILO Output Leakage Current Output(s) disabled, 0V < VOUT < VCC –2 VOH Output High Voltage[15, 23] IOH = –4.0 mA at VCCQ = 3.135V 2.4 IOH = –4.0 mA at VCCQ = 2.375V 1.7 VOH VOL Output Low Voltage [15, 23] IOL = 8.0 mA [15] VCC Supply Voltage VCCQ I/O Supply Voltage[15] V 0.4 V 3.135 3.6 V 2.375 VCC V Conditions Typ. 166 MHz/ -6 Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open 100 310 275 250 190 mA CMOS Standby[25, 26] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC – 0.2; all inputs static; CLK frequency = 0 5 10 10 10 10 mA ISB3 TTL Standby[25, 26] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 10 20 20 20 20 mA ISB4 Clock Running[25, 26] Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min. 40 80 70 60 50 mA Parameter Description ICC Power Supply Current: Operating[24, 25, 26] ISB2 150 MHz/ -6.7 133 MHz/ -7.5 100 MHz/ -10 Unit Capacitance[17] Parameter Description Test Conditions CI Input Capacitance CO Input/Output Capacitance (DQ) TA = 25°C, f = 1 MHz, VCC = 3.3V Typ. Max. Unit 4 5 pF 7 8 pF Thermal Resistance Description Test Conditions Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer PCB Thermal Resistance (Junction to Case) Symbol BGA Typ. TQFP Typ. Unit ΘJA 19 25 °C/W ΘJC 9 9 °C/W Note: 21. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. Undershoot:VIL ≤ –2.0V for t ≤ tKC /2. 22. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 23. AC I/O curves are available upon request. 24. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 25. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 26. Typical values are measured at 3.3V, 25°C, and 8.5-ns cycle time. Document #: 38-05120 Rev. ** Page 15 of 24 CY7C1359A/GVT71256T18 AC Test Loads and Waveforms ALL INPUT PULSES +2.5v DQ Z0 = 50Ω 2.5V 50Ω 30 pF 90% 10% 90% 0V DQ Vt = 1.25V 10% 1,667Ω 1,538Ω (a) ≤ 1.8 ns ≤ 1.8 ns 5 pF (c) (b) (b) Switching Characteristics Over the Operating Range[27] -6 166 MHz Parameter Description Min. Max. -6.7 150 MHz Min. Max. -7.5 133 MHz Min. Max. -10 100 MHz Min. Max. Unit Clock tKC Clock Cycle Time 6.0 6.7 7.5 8.5 ns tKF Clock Frequency tKH Clock HIGH Time 2.4 2.6 2.8 3.4 ns Clock LOW Time tKL 2.4 2.6 2.8 3.4 ns Output Times tKQ Clock to Output Valid tKM Clock to MATCH Valid tKQX Clock to Output Invalid tKMX Clock to MATCH Invalid tKQLZ Clock to Output in Low-Z[17, 28, 29] tKQHZ Clock to Output in High-Z 3.5 [17, 28, 29] OE to Output Valid tMOEM MOE to MATCH Valid[30] tOELZ OE to Output in Low-Z[17, 28, 29] 4.0 4.0 ns 1.5 1.5 1.5 1.5 ns 0 0 0 0 ns 1.5 [30] tOEQ 3.8 6.0 1.5 3.5 0 6.7 1.5 3.5 0 7.5 1.5 3.8 0 8.5 ns 3.8 ns 0 ns [17, 28, 29] tMOELZ MOE to MATCH in Low-Z tOEHZ OE to Output in High-Z[17, 28, 29] tMOEHZ MOE to MATCH in High-Z[17, 28, 29] 3.5 3.5 3.8 3.8 ns Set-up Times tS Address, Controls, and Data In[31] 1.5 1.5 1.5 2.0 ns Address, Controls, and Data In[31] 0.5 0.5 0.5 0.5 ns Hold Times tH Notes: 27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted. 28. Output loading is specified with CL = 5 pF as in AC Test Loads. 29. At any given temperature and voltage condition, tKQHZ is less than tKQLZ, tOEHZ is less than tOELZ and tMOEHZ is less than tMOELZ. 30. OE is a “Don’t Care” after a write cycle begins To prevent bus contention, OE should be negated prior before the start of write cycle. 31. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table. Document #: 38-05120 Rev. ** Page 16 of 24 CY7C1359A/GVT71256T18 Typical Output Buffer Characteristics Output High Voltage Pull-Up Current Output Low Voltage Pull-Down Current IOL (mA) Min. IOL(mA) Max. VOH (V) IOH (mA) Min. IOH (mA) Max. VOL (V) –0.5 –38 –105 –0.5 0 0 0 –38 –105 0 0 0 0.8 –38 –105 0.4 10 20 1.25 –26 –83 0.8 20 40 1.5 –20 –70 1.25 31 63 2.3 0 –30 1.6 40 80 2.7 0 –10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 Document #: 38-05120 Rev. ** Page 17 of 24 CY7C1359A/GVT71256T18 Switching Waveforms Read Timing with Burst Feature[32, 33] tKC tKL CLK tKH tS ADSP# tH ADSC# tS ADDRESS A1 A2 tH WEL#, WEH#, BWE#, GW# tS CE# tS ADV# tH OE# tKQ DQ tKQLZ tOELZ Q(A1) tOEQ tKQ Q(A2) Q(A2+1) SINGLE READ Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Notes: 32. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active. 33. In this timing diagram, it is assumed that DEN is tied to LOW (VSS). Document #: 38-05120 Rev. ** Page 18 of 24 CY7C1359A/GVT71256T18 Switching Waveforms (continued) Write Timing with Burst Feature[32, 33] CLK tS ADSP# tH ADSC# tS A1 ADDRESS A2 A3 tH WEL#, WEH#, BWE# GW# CE# tS ADV# tH OE# tKQX DQ Q tOEHZ D(A1) SINGLE WRITE Document #: 38-05120 Rev. ** D(A2) D(A2+1) D(A2+1) D(A2+2) BURST WRITE D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page 19 of 24 CY7C1359A/GVT71256T18 Switching Waveforms (continued) Read/Write Timing with Burst Feature[32, 33] CLK tS ADSP# tH ADSC# tS ADDRESS A1 A2 A3 A4 A5 tH WEL#, WEH#, BWE#, GW# CE# ADV# OE# DQ Q(A1) Single Reads Document #: 38-05120 Rev. ** Q(A2) D(A3) Single Write Q(A4) Q(A4+1) Burst Read Q(A4+2) D(A5) D(A5+1) Burst Write Page 20 of 24 CY7C1359A/GVT71256T18 Switching Waveforms (continued) Read/Write Timing without Burst Feature[32, 34, 35] tKH tKC tKL CLK tS ADDRESS A1 A2 A3 A4 A5 A6 A7 A8 D(A5) D(A6) D(A7) D(A8) tH WE# CE# DEN# tOEQ tOEHZ OE# DQ tKQHZ tOELZ tKQLZ tKQX tKQ Q(A1) Q(A2) Reads Q(A3) Q(A4) Writes Notes: 34. In this timing diagram, it is assumed that burst feature is not used and therefore ADSP is tied to HIGH (VCC) and ADSC is tied to LOW (VSS). The logic state of ADV is a “Don’t Care”. 35. In this timing diagram, it is assumed that WE = [BWE + WEL*WEH]*GW. Document #: 38-05120 Rev. ** Page 21 of 24 CY7C1359A/GVT71256T18 Switching Waveforms (continued) Compare/Fill Write Timing[32, 34, 35] tKH tKC tKL CLK tS ADDRESS A1 A1 A2 tH WE# CE# DEN# OE# DQ D(A1) D(A2) tKM MOE# tMOEHZ tMOEM MATCH HIGH CHIP DESELECTED tMOELZ MATCH tKMX MISS Document #: 38-05120 Rev. ** FILL WRITE HIT Page 22 of 24 CY7C1359A/GVT71256T18 Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range Commercial 166 CY7C1359A-166AC/ GVT71256T18T-6 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 150 CY7C1359A-150AC/ GVT71256T18T-6.7 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 133 CY7C1359A-133AC/ GVT71256T18T-7.5 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100 CY7C1359A-100AC/ GVT71256T18T-10 A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1359A/GVT71256T18 Document Title: CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM Document Number: 38-05120 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 108311 09/25/01 BRI New Cypress spec—converted from Galvantech format Document #: 38-05120 Rev. ** Page 24 of 24