Cypress CY7C1329-75AC 64k x 32 synchronous-pipelined cache ram Datasheet

CY7C1329
64K x 32 Synchronous-Pipelined Cache RAM
Features
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns (133-MHz
device).
• Supports 133-MHz bus for Pentium® and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
The CY7C1329 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
— 7.0 ns (for 75-MHz device
• User-selectable burst counter supporting Intel®
Pentium interleaved or linear burst sequences
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write circuitry.
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
MODE
(A[1:0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[15:0]
GW
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Q
16
14
ADDRESS
CE REGISTER
D
D
BWE
BW 3
16
14
64KX32
MEMORY
ARRAY
DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
BW2
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
D
Q
DQ[7:0]
BYTEWRITE
REGISTERS
BW1
BW0
CE1
CE2
CE3
32
32
D
ENABLE Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
D
Q
ENABLE DELAY
REGISTER
CLK
OE
ZZ
SLEEP
CONTROL
DQ[31:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 6, 1999
CY7C1329
Pin Configuration
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100-Pin TQFP
BYTE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1329
BYTE1
BYTE0
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE3
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
Selection Guide
Maximum Access Time (ns)
7C1329-133
7C1329-100
7C1329-75
4.2
5.5
7.0
Maximum Operating Current (mA)
Commercial
325
310
260
Maximum CMOS Standby Current (mA)
Commercial
5
5
5
2
CY7C1329
Pin Definitions
Pin Number
49–44, 81,82,
99, 100,
32–37
96–93
Name
A[15:0]
I/O
InputSynchronous
BW[3:0]
88
GW
InputSynchronous
InputSynchronous
87
BWE
89
CLK
98
CE1
InputSynchronous
97
CE2
92
CE3
86
OE
InputSynchronous
InputSynchronous
InputAsynchronous
83
ADV
84
ADSP
85
ADSC
InputSynchronous
64
ZZ
InputAsynchronous
I/OSynchronous
29, 28,
DQ[31:0]
25–22, 19,
18,13,12,
9–6, 3, 2, 79,
78, 75–72,
69, 68, 63, 62
59–56, 53, 52
15, 41, 65, 91 VDD
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
31
VSS
VDDQ
VSSQ
MODE
1, 14, 16, 30, NC
38, 39, 42, 43,
50, 51, 66, 80
InputSynchronous
Input-Clock
InputSynchronous
InputSynchronous
Power Supply
Ground
I/O Power
Supply
I/O Ground
InputStatic
-
Description
Address Inputs used to select one of the 64K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[3:0] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if
CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of
a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[15:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQ [31:0] are placed in a three-state
condition.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects burst order. When tied to GND selects linear burst sequence. When tied
to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation.
No Connects.
3
CY7C1329
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BW[3:0] signals. The CY7C1329 provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte
Write Enable input (BWE) with the selected Byte Write
(BW[3:0]) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 4.2 ns (133-MHz
device).
The CY7C1329 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the
address for the rest of the burst access.
Because the CY7C1329 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ [31:0] are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW [3:0]) are asserted active to conduct a write to
the desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented to
A[15:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ[31:0] is written into the
corresponding address location in the RAM core. If a byte write
is conducted, only the selected bytes are written. Bytes not
selected during a byte write operation will remain unaltered. A
Synchronous self-timed write mechanism has been provided
to simplify the write operations.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs (A[15:0])
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 4.2 ns (133-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Because the CY7C1329 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ [31:0] are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1329 provides a two-bit wraparound counter, fed by
A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
Interleaved Burst Sequence
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A [15:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW0–BW3) and ADV inputs are
ignored during this first cycle.
First
Address
A[1:0]
00
01
10
11
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ[31:0] inputs is written into the corre-
4
Second
Address
A[1:0]
01
00
11
10
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
CY7C1329
Sleep Mode
Linear Burst Sequence
First
Address
Second
Address
Third
Address
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE 1, CE 2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Snooze mode
standby current
tZZS
tZZREC
Min
Max
Unit
ZZ > VDD − 0.2V
3
mA
Device operation to
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Cycle Descriptions[1,2,3]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
L
Unselected
None
L
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
L
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
L
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
L
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
1
0
X
X
Hi-Z
read
Continue Read
Next
L
X
X
X
1
1
0
1
Hi-Z
read
Continue Read
Next
L
X
X
X
1
1
0
0
DQ
read
Continue Read
Next
L
X
X
1
X
1
0
1
Hi-Z
read
Continue Read
Next
L
X
X
1
X
1
0
0
DQ
read
Suspend Read
Current
L
X
X
X
1
1
1
1
Hi-Z
read
Suspend Read
Current
L
X
X
X
1
1
1
0
DQ
read
Suspend Read
Current
L
X
X
1
X
1
1
1
Hi-Z
read
Suspend Read
Current
L
X
X
1
X
1
1
0
DQ
read
Begin Write
Current
L
X
X
X
1
1
1
X
Hi-Z
write
Begin Write
Current
L
X
X
1
X
1
1
X
Hi-Z
write
Begin Write
External
L
0
1
0
1
0
X
X
Hi-Z
write
Continue Write
Next
L
X
X
X
1
1
0
X
Hi-Z
write
Continue Write
Next
L
X
X
1
X
1
0
X
Hi-Z
write
Suspend Write
Current
L
X
X
X
1
1
1
X
Hi-Z
write
Suspend Write
Current
L
X
X
1
X
1
1
X
Hi-Z
write
ZZ “sleep”
None
H
X
X
X
X
X
X
X
Hi-Z
X
Notes:
1. X=”Don't Care”, 1=HIGH, 0=LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5
CY7C1329
Write Cycle Descriptions[4,5,6]
Function
GW
BWE
BW3
BW2
BW1
BW0
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 - DQ[7:0]
1
0
1
1
1
0
Write Byte 1 - DQ[15:8]
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 - DQ[23:16]
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 - DQ[31:24]
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND .........−0.5V to +4.6V
Range
Ambient
Temperature[8]
DC Voltage Applied to Outputs
in High Z State[7] .....................................−0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
DC Input Voltage[7] ..................................−0.5V to VDDQ + 0.5V
VDD
VDDQ
3.3V
−5%/+10%
3.3V
−5%/+10%
Notes:
4. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a “don't care” for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or
when the device is deselected, and DQ=data when OE is active.
7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
6
CY7C1329
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.3V −5%/+10%
3.135
3.6
V
VDDQ
I/O Supply Voltage
3.3V −5%/+10%
3.135
3.6
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VDD = Min., IOH = −4.0 mA
VDD = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[7]
IX
Input Load Current
except ZZ and MODE
−5
2.4
0.4
V
2.0
VDDQ + 0.3V
V
–0.3
0.8
V
5
µA
GND ≤ V I ≤ VDDQ
Input Current of MODE Input = VSS
Input = VDDQ
–30
Input Current of ZZ
–5
Input = VSS
Input = VDDQ
Output Leakage
Current
GND ≤ V I ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CS
Power-Down
Current—TTL Inputs
µA
µA
5
IOZ
ISB1
V
Max. V DD, Device Deselected,
VIN ≥ VIH or VIN ≤ V IL
f = fMAX = 1/tCYC
−5
µA
30
µA
5
µA
7.5-ns cycle, 133 MHz
325
mA
10-ns cycle, 100 MHz
260
mA
13.3-ns cycle, 75 MHz
260
mA
7.5-ns cycle, 133 MHz
60
mA
10-ns cycle, 100 MHz
50
mA
13.3-ns cycle, 75 MHz
50
mA
ISB2
Automatic CS
Max. V DD, Device Deselected, VIN All speeds
Power-Down
≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
Current—CMOS Inputs
5
mA
ISB3
Automatic CS
Max. VDD, Device Deselected, or
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
40
mA
10-ns cycle, 100 MHz
30
mA
13.3-ns cycle, 75 MHz
30
mA
25
mA
ISB4
Automatic CS
Power-Down
Current—TTL Inputs
Max. V DD, Device Deselected,
VIN ≥ VIH or VIN ≤ V IL, f = 0
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
7
Max.
Unit
4
pF
4
pF
4
pF
CY7C1329
AC Test Loads and Waveforms
R=317Ω
3.3V
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 =50Ω
3.3V
5 pF
R=351Ω
VL = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
90%
10%
RL =50Ω
[10]
GND
< 3.3 ns
< 3.3 ns
(c)
(b)
Switching Characteristics Over the Operating Range[11,12,13]
-133
Parameter
Description
Min.
-100
Max.
Min.
-75
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
7.5
10
13.3
ns
tCH
Clock HIGH
1.9
3.2
5.0
ns
tCL
Clock LOW
1.9
3.2
5.0
ns
tAS
Address Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
ns
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.5
1.5
2.0
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
ns
tWES
BWE, GW, BW[3:0] Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tWEH
BWE, GW, BW[3:0] Hold After CLK Rise
0.5
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
tCES
Chip Select Set-Up
2.5
2.5
2.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
ns
[12]
tCHZ
Clock to High-Z
tCLZ
Clock to Low-Z[12]
tEOHZ
tEOLZ
tEOV
4.2
1.5
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid
3.5
0
[12, 13]
5.0
1.5
3.5
[12, 13]
0
[12]
5
0
2
6
0
5.5
0
4.2
7.0
ns
ns
6
0
5.0
ns
ns
ns
6
ns
Notes:
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL /IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. t CHZ, t CLZ, tEOV, t EOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than t EOLZ and t CHZ is less than tCLZ.
8
CY7C1329
Switching Waveforms
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data- High-Z
In
1a
1a
2a
2c
2b
= UNDEFINED
2d
3a
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
9
High-Z
CY7C1329
Switching Waveforms (continued)
Read Cycle Timing[14, 16]
Single Read
tCYC
Burst Read
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tCEH
tDOE
tOEHZ
tDOH
DataOut
tCO
1a
1a
2a
2b
2c 2c
2d
3a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
10
CY7C1329
Switching Waveforms (continued)
Read/Write Cycle Timing[14,15,16, 17]
Single Read
tCYC
Single Write
Unselected
Burst Read
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC
tADVS
tADH
ADV
tAS
ADD
tADVH
RD1
WD2
RD3
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tDOE
OE
tOEHZ
DataIn/Out
tOELZ
tCO
See Note 17
1a
1a
Out
tDS
tDH
2a
In
2a
Out
= DON’T CARE
= UNDEFINED
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
11
3a
Out
tDOH
3b
Out
3c
Out
3d
Out
TCHZ
CY7C1329
Switching Waveforms (continued)
Pipeline Timing[18,19]
tCH
tCYC
tCL
CLK
tAS
ADD
RD1
tADS
RD2
RD3
WD1
RD4
WD2
WD3
WD4
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWEH
tWES
WE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data In/Out
1a
Out
2a
Out
3a
Out
1a
In
4a
Out
2a
In
3a
In
tCO
tDOH
Back to Back Reads
tCHZ
= UNDEFINED
= DON’T CARE
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
12
4a
D(C)
In
CY7C1329
Switching Waveforms (continued)
ZZ Mode Timing[20, 21]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Note:
20. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
13
CY7C1329
Ordering Information
Speed
(MHz)
Ordering Code
Package
Name
A101
Package Type
133
CY7C1329-133AC
100-Lead Thin Quad Flat Pack
100
CY7C1329-100AC
A101
100-Lead Thin Quad Flat Pack
75
CY7C1329-75AC
A101
100-Lead Thin Quad Flat Pack
Operating
Range
Commercial
Document #: 38-00561–A
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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