CA555, CA555C, LM555C T CT DUC PRO PRODU E T E E L T O U OBS UBSTIT 5 S 5 5 E 7 L ICM SSIB Semiconductor December 1999 File Number 834.6 PO 1 • Accurate Timing From Microseconds Through Hours • Astable and Monostable Operation • Adjustable Duty Cycle • Output Capable of Sourcing or Sinking up to 200mA • Output Capable of Driving TTL Devices • Normally ON and OFF Outputs • High Temperature Stability . . . . . . . . . . . . . . . . 0.005%/oC • Directly Interchangeable with SE555, NE555, MC1555, and MC1455 Applications • Precision Timing • Sequential Timing • Time Delay Generation • Pulse Generation • Pulse Detector • Pulse Width and Position Modulation Functional Block Diagram TRIGGER COMPAR 3 6 OUTPUT THRESHOLD COMPAR 7 FLIP-FLOP 4 DISCHARGE OUTPUT V+ TRIGGER CONTROL 8 VOLTAGE 5 2 THRESHOLD [ /Title The CA555 and CA555C are highly stable timers for use in (CA55 precision timing and oscillator applications. As timers, these 5, monolithic integrated circuits are capable of producing CA555 accurate time delays for periods ranging from microseconds through hours. These devices are also useful for astable C, LM555 oscillator operation and can maintain an accurately controlled free running frequency and duty cycle with only C) two external resistors and one capacitor. /SubThe circuits of the CA555 and CA555C may be triggered by ject the falling edge of the waveform signal, and the output of (Tim- these circuits can source or sink up to a 200mA current or ers for drive TTL circuits. Timing These types are direct replacements for industry types in Delays packages with similar terminal arrangements e.g. SE555 and and NE555, MC1555 and MC1455, respectively. The CA555 Oscilla- type circuits are intended for applications requiring premium electrical performance. The CA555C type circuits are tor Appli- intended for applications requiring less stringent electrical cations characteristics. in Part Number Information ComPART NUMBER TEMP. PKG. mer(BRAND) RANGE (oC) PACKAGE NO. cial, CA0555E -55 to 125 8 Ld PDIP E8.3 IndusCA0555CE 0 to 70 8 Ld PDIP E8.3 trial LM555CN 0 to 70 8 Ld PDIP E8.3 and MiliPinout tary CA555, CA555C, LM555C, (PDIP) EquipTOP VIEW ment) 8 V+ GND 1 /Author 7 DISCHARGE TRIGGER 2 () OUTPUT 3 6 THRESHOLD /Key5 CONTROL RESET 4 words VOLTAGE (Harris Semiconductor, single, timer, Features RESET Timers for Timing Delays and Oscillator Applications in Commercial, Industrial and Military Equipment 1 GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 CA555, CA555C, LM555C Absolute Maximum Ratings Thermal Information DC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range CA555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CA555C, LM555C . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified Electrical Specifications CA555 PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS 4.5 - 18 4.5 - 16 V V+ = 5V, RL = ∞ - 3 5 - 3 6 mA V+ = 15V, RL = ∞ - 10 12 - 10 15 mA - (2/3)V+ - - (2/3)V+ - V V+ = 5V 1.45 1.67 1.9 - 1.67 - V V+ = 15V 4.8 5 5.2 - 5 - V - 0.5 - - 0.5 - µA - 0.1 0.25 - 0.1 0.25 µA Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V Reset Current - 0.1 - - 0.1 - mA V+ = 5V 2.9 3.33 3.8 2.6 3.33 4 V V+ = 15V 9.6 10 10.4 9 10 11 V V+ = 5V, ISINK = 5mA - - - - 0.25 0.35 V ISINK = 8mA - 0.1 0.25 - - - V V+ = 15V, ISINK = 10mA - 0.1 0.15 - 0.1 0.25 V ISINK = 50mA - 0.4 0.5 - 0.4 0.75 V ISINK = 100mA - 2.0 2.2 - 2.0 2.5 V ISINK = 200mA - 2.5 - - 2.5 - V V+ = 5V, ISOURCE = 100mA 3.0 3.3 - 2.75 3.3 - V V+ = 15V, ISOURCE = 100mA 13.0 13.3 - 12.75 13.3 - V ISOURCE = 200mA - 12.5 - - 12.5 - V R1, R2 = 1kΩ to 100kΩ, C = 0.1µF Tested at V+ = 5V, V+ = 15V - 0.5 2 - 1 - % - 30 100 - 50 - ppm/oC - 0.05 0.2 - 0.1 - %/V DC Supply Voltage TEST CONDITIONS CA555C, LM555C V+ DC Supply Current (Low State) (Note 2) I+ Threshold Voltage VTH Trigger Voltage Trigger Current Threshold Current (Note 3) ITH Control Voltage Level Output Voltage VOL Low State Output Voltage VOH High State Timing Error (Monostable) Frequency Drift with Temperature Drift with Supply Voltage Output Rise Time tR - 100 - - 100 - ns Output Fall Time tF - 100 - - 100 - ns NOTES: 2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value. 3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total R1 + R2 = 20MΩ. 2 CA555, CA555C, LM555C Schematic Diagram THRESHOLD COMPARATOR V+ TRIGGER COMPARATOR FLIP-FLOP OUTPUT 8 4.7K 830 4.7K 1K 5K 6.8K D2 D1 Q16 Q10 Q3 Q19 Q4 Q20 7K THRESHOLD 6 Q1 OUTPUT 3.9K 3 Q7 Q2 Q5 D3 4.7K D4 5K 10K Q18 Q11 Q12 CONTROL VOLTAGE 5 220 Q15 5K 2 TRIGGER Q21 Q17 Q13 Q9 4.7K Q14 RESET 4 100K Q8 RESET 7 DISCHARGE 1 Q6 DISCHARGE 100 V- NOTE: Resistance values are in ohms. Typical Applications Reset Timer (Monostable Operation) Figure 1 shows the CA555 connected as a reset timer. In this mode of operation capacitor CT is initially held discharged by a transistor on the integrated circuit. Upon closing the “start” switch, or applying a negative trigger pulse to terminal 2, the integral timer flip-flop is “set” and releases the short circuit across CT which drives the output voltage “high” (relay energized). The action allows the voltage across the capacitor to increase exponentially with the constant t = R1CT. When the voltage across the capacitor equals 2/3 V+, the comparator resets the flip-flop which in turn discharges the capacitor rapidly and drives the output to its low state. Since the charge rate and threshold level of the comparator are both directly proportional to V+, the timing interval is relatively independent of supply voltage variations. Typically, the timing varies only 0.05% for a 1V change in V+. Applying a negative pulse simultaneously to the reset terminal (4) and the trigger terminal (2) during the timing cycle discharges CT and causes the timing cycle to restart. Momentarily closing only the reset switch during the timing interval discharges CT, but the timing cycle does not restart. 3 V+ RESET R1 5V 680 4 7 8 6 EO 3 CA555 1N4001 5 1 10K 2 CT 4.7K 0.01µF 680 RELAY COIL S1 START NOTE: All resistance values are in ohms. FIGURE 1. RESET TIMER (MONOSTABLE OPERATION) CA555, CA555C, LM555C Figure 2 shows the typical waveforms generated during this mode of operation, and Figure 3 gives the family of time delay curves with variations in R1 and CT. SWITCH S1 “OPEN” 3V INPUT VOLTAGE (TERMINAL 2) SWITCH S1 “CLOSED” 0 Repeat Cycle Timer (Astable Operation) Figure 4 shows the CA555 connected as a repeat cycle timer. In this mode of operation, the total period is a function of both R1 and R2. V+ 5V R1 3.3V CAPACITOR VOLTAGE (TERMINALS 6, 7) 0 4 7 R2 8 CA555 6 tD EO 3 RELAY COIL 5 1 2 5V OUTPUT VOLTAGE (TERMINAL 3) CT 0.01µF 0 FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION) FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER T = 0.693 (R1 + 2R2) CT = t1 + t2 100 where t1 = 0.693 (R1 + R2) CT TA = 25oC V+ = 5V and t2 = 0.693 (R2) CT CAPACITANCE (µF) 10 the duty cycle is: R1 = 1kΩ 1 t1 R1 + R2 ---------------- = -----------------------t 1 + t 2 R 1 + 2R 2 10kΩ 100kΩ 1MΩ 0.1 10MΩ Typical waveforms generated during this mode of operation are shown in Figure 5. Figure 6 gives the family of curves of free running frequency with variations in the value of (R1 + 2R2) and CT. 0.01 0.001 10-5 10-4 10-3 10-2 10-1 1 10 TIME DELAY(s) FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE 4 CA555, CA555C, LM555C t1 t2 100 TA = 25oC, V+ = 5V 5V CAPACITANCE (µF) 10 0 3.3V R1 + 2R2 = 1kΩ 10kΩ 1 100kΩ 1MΩ 10MΩ 0.1 0.01 1.7V 0.001 10-1 0 1 102 10 103 104 105 FREQUENCY (Hz) Top Trace: Output voltage (2V/Div. and 0.5ms/Div.) Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.) FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE TIMER WITH VARIATION IN CAPACITANCE AND RESISTANCE 150 10 SUPPLY CURRENT (mA) MINIMUM PULSE WIDTH (ns) Typical Performance Curves TA = -55oC 100 0oC 25oC 70oC 50 125oC TA = 125oC 9 8 25oC 7 6 50oC 5 4 3 2 1 0 0.1 0.2 0.3 0.4 0 MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE) 2.5 5 7.5 10 12.5 15 SUPPLY VOLTAGE (V) NOTE: Where x is the decimal multiplier of the supply voltage. FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE 2.0 10.0 TA = -55oC 1.6 OUTPUT VOLTAGE - LOW STATE (V) SUPPLY VOLTAGE - OUTPUT VOLTAGE (V) FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER VOLTAGE 25oC 1.2 125oC 0.8 0.4 5V ≤ V+ ≤ 15V 0 V+ = 5V TA = -55oC 25oC 1.0 125oC 0.1 0.01 1 10 SOURCE CURRENT (mA) FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs SOURCE CURRENT 5 100 1 10 SINK CURRENT (mA) FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK CURRENT 100 CA555, CA555C, LM555C Typical Performance Curves (Continued) 10.0 V+ = 10V OUTPUT VOLTAGE - LOW STATE (V) OUTPUT VOLTAGE - LOW STATE (V) 10.0 TA = -55oC 1.0 25oC 125oC 125oC 25oC 0.1 V+ = 15V -55oC 1.0 125oC 25oC TA = -55oC 0.1 0.01 0.01 1 10 1 100 10 SINK CURRENT (mA) 100 SINK CURRENT (mA) FIGURE 11. OUTPUT VOLTAGE LOW STATE vs SINK CURRENT FIGURE 12. OUTPUT VOLTAGE LOW STATE vs SINK CURRENT 1.100 NORMALIZED DELAY TIME 1.000 0.990 0.980 0 2.5 5 7.5 10 12.5 15 17.5 1.005 0.995 0.985 -75 -50 -25 0 FIGURE 13. DELAY TIME vs SUPPLY VOLTAGE 250 TA = -55oC 150 0 oC 100 25oC 70oC 50 125oC 0 0.1 0.2 0.3 0.4 MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE) NOTE: Where x is the decimal multiplier of the supply voltage. FIGURE 15. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE 6 50 75 100 FIGURE 14. DELAY TIME vs TEMPERATURE 300 200 25 TEMPERATURE (oC) SUPPLY VOLTAGE (V) PROPAGATION DELAY TIME (ns) NORMALIZED DELAY TIME TA = 25oC 125