Freescale MC9S08GT8AM Microcontroller Datasheet

MC9S08GT16A
MC9S08GT8A
Data Sheet
HCS08
Microcontrollers
MC9S08GT16A
Rev. 1
7/2006
freescale.com
MC9S08GT16A/GT8A Features
8-Bit HCS08 Central Processor Unit (CPU)
•
•
•
40-MHz HCS08 CPU
HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
•
•
•
Memory Options
•
•
FLASH read/program/erase down to 1.8 V
Up to 16K FLASH; up to 2K RAM
Power-Saving Modes
•
•
•
Three very low power stop modes
Reduced power wait mode
Very low power real time interrupt for use in run,
wait, and stop
Development Support
•
•
•
Clock Source Options
•
•
Clock sources to internal hardware frequency
locked-loop (FLL): internal, external, crystal, or
resonator
Internal clock with ±0.2% trimming resolution and
±0.5% deviation across voltage or across
temperature
System Protection
•
•
•
•
•
Optional watchdog computer operating properly
(COP) reset
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
Illegal address detection with reset
FLASH block protect and security
Peripherals
•
•
•
•
•
•
ATD — 8-channel, 10-bit analog-to-digital
converter
SCI — Two serial communications interface
modules
SPI — Serial peripheral interface module
IIC — Inter-integrated circuit bus module
Timer —One 3-channel timer PWM module (TPM)
plus one 2-channel TPM
KBI — 8-pin keyboard interrupt module
Input/Output
•
8 high-current pins (20 mA each)
Software selectable pullups on ports when used as
input
Internal pullup on RESET and IRQ pin to reduce
customer system cost
Up to 38 general-purpose input/output (I/O) pins,
plus one output-only pin, depending on package
selection
•
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
On-chip, in-circuit emulation (ICE) debug module
with real-time bus capture. On-chip ICE debug
module containing two comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data.
Single-wire background debug interface
Package Options
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•
•
•
48-pin QFN
44-pin QFP
42-pin PSDIP
32-pin QFN
MC9S08GT16A/GT8A Data Sheet
Covers: MC9S08GT16A
MC9S08GT8A
MC9S08GT16A
Rev. 1
7/2006
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
1
07/17/2006
Description of Changes
Initial public release
© Freescale Semiconductor, Inc., 2006. All rights reserved.
This product incorporates SuperFlash® Technology licensed from SST.
List of Chapters
Chapter 1
Device Overview ...................................................................... 19
Chapter 2
Pins and Connections ............................................................. 23
Chapter 3
Modes of Operation ................................................................. 33
Chapter 4
Memory ..................................................................................... 41
Chapter 5
Resets, Interrupts, and System Configuration ..................... 63
Chapter 6
Parallel Input/Output ............................................................... 79
Chapter 7
Keyboard Interrupt (S08KBIV1) .............................................. 99
Chapter 8
Central Processor Unit (S08CPUV2) .................................... 105
Chapter 9
Internal Clock Generator (S08ICGV4) .................................. 125
Chapter 10
Timer/PWM (S08TPMV2) ...................................................... 153
Chapter 11
Serial Communications Interface (S08SCIV1)..................... 169
Chapter 12
Serial Peripheral Interface (S08SPIV3) ................................ 187
Chapter 13
Inter-Integrated Circuit (S08IICV1) ....................................... 205
Chapter 14
Analog-to-Digital Converter (S08ATDV3) ............................ 221
Chapter 15
Development Support ........................................................... 237
Appendix A
Electrical Characteristics...................................................... 259
Appendix B
Ordering Information and Mechanical Drawings................ 285
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
7
Contents
Section Number
Title
Page
Chapter 1
Device Overview
1.1
1.2
Introduction .....................................................................................................................................19
1.1.1 Devices in the MC9S08GT16A/GT8A Series ..................................................................19
1.1.2 MCU Block Diagram ........................................................................................................19
System Clock Distribution ..............................................................................................................21
Chapter 2
Pins and Connections
2.1
2.2
2.3
Introduction .....................................................................................................................................23
Device Pin Assignment ...................................................................................................................23
Recommended System Connections ...............................................................................................27
2.3.1 VDD, VSS, VDDAD, VSSAD, VREFH, VREFL — Power and Voltage References ...............28
2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator ......................................................................28
2.3.3 RESET — External Reset Pin ...........................................................................................29
2.3.4 PTG0/BKGD/MS — Background / Mode Select .............................................................29
2.3.5 IRQ — External Interrupt Request Pin .............................................................................30
2.3.6 General-Purpose I/O and Peripheral Ports ........................................................................30
2.3.7 Signal Properties Summary ...............................................................................................31
Chapter 3
Modes of Operation
3.1
3.2
3.3
3.4
3.5
Introduction .....................................................................................................................................33
3.1.1 Features .............................................................................................................................33
Run Mode ........................................................................................................................................33
Active Background Mode ................................................................................................................33
Wait Mode .......................................................................................................................................34
Stop Modes ......................................................................................................................................35
3.5.1 Stop1 Mode .......................................................................................................................35
3.5.2 Stop2 Mode .......................................................................................................................35
3.5.3 Stop3 Mode .......................................................................................................................36
3.5.4 Active BDM Enabled in Stop Mode .................................................................................37
3.5.5 LVD Enabled in Stop Mode ..............................................................................................37
3.5.6 On-Chip Peripheral Modules in Stop Modes ....................................................................38
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
NON-DISCLOSURE AGREEMENT REQUIRED
9
Section Number
Title
Page
Chapter 4
Memory
4.1
4.2
4.3
4.4
4.5
4.6
MC9S08GT16A/GT8A Memory Map ............................................................................................41
4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42
Register Addresses and Bit Assignments ........................................................................................43
RAM ................................................................................................................................................48
FLASH ............................................................................................................................................48
4.4.1 Features .............................................................................................................................48
4.4.2 Program and Erase Times .................................................................................................49
4.4.3 Program and Erase Command Execution .........................................................................49
4.4.4 Burst Program Execution ..................................................................................................51
4.4.5 Access Errors ....................................................................................................................53
4.4.6 FLASH Block Protection ..................................................................................................53
4.4.7 Vector Redirection ............................................................................................................54
Security ............................................................................................................................................54
Register Definition ..........................................................................................................................56
4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................56
4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................57
4.6.3 FLASH Configuration Register (FCNFG) ........................................................................58
4.6.4 FLASH Protection Register (FPROT and NVPROT) .......................................................58
4.6.5 FLASH Status Register (FSTAT) ......................................................................................59
4.6.6 FLASH Command Register (FCMD) ...............................................................................60
Chapter 5
Resets, Interrupts, and System Configuration
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction .....................................................................................................................................63
5.1.1 Features .............................................................................................................................63
MCU Reset ......................................................................................................................................63
Computer Operating Properly (COP) Watchdog .............................................................................64
Interrupts .........................................................................................................................................64
5.4.1 Interrupt Stack Frame .......................................................................................................65
5.4.2 IRQ — External Interrupt Request Pin .............................................................................66
5.4.2.1 Pin Configuration Options ..............................................................................66
5.4.2.2 Edge and Level Sensitivity ..............................................................................67
5.4.3 Interrupt Vectors, Sources, and Local Masks ....................................................................67
Low-Voltage Detect (LVD) System ................................................................................................69
5.5.1 Power-On Reset Operation ...............................................................................................69
5.5.2 LVD Reset Operation ........................................................................................................69
5.5.3 LVD Interrupt Operation ...................................................................................................69
5.5.4 Low-Voltage Warning (LVW) ...........................................................................................69
Real-Time Interrupt (RTI) ...............................................................................................................69
Register Definition ..........................................................................................................................70
MC9S08GT16A/GT8A Data Sheet, Rev. 1
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Freescale Semiconductor
Section Number
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
Title
Page
Interrupt Pin Request Status and Control Register (IRQSC) ............................................71
System Reset Status Register (SRS) .................................................................................72
System Background Debug Force Reset Register (SBDFR) ............................................73
System Options Register (SOPT) .....................................................................................74
System Device Identification Register (SDIDH, SDIDL) ................................................75
System Real-Time Interrupt Status and Control Register (SRTISC) ................................76
System Power Management Status and Control 1 Register (SPMSC1) ...........................77
System Power Management Status and Control 2 Register (SPMSC2) ...........................78
Chapter 6
Parallel Input/Output
6.1
6.2
6.3
6.4
6.5
Introduction .....................................................................................................................................79
6.1.1 Features .............................................................................................................................79
6.1.2 Block Diagram ..................................................................................................................81
External Signal Description ............................................................................................................82
6.2.1 Port A and Keyboard Interrupts ........................................................................................82
6.2.2 Port B and Analog to Digital Converter Inputs .................................................................82
6.2.3 Port C and SCI2, IIC, and High-Current Drivers ..............................................................83
6.2.4 Port D, TPM1 and TPM2 ..................................................................................................83
6.2.5 Port E, SCI1, and SPI ........................................................................................................84
6.2.6 Port G, BKGD/MS, and Oscillator ...................................................................................84
Parallel I/O Controls ........................................................................................................................85
6.3.1 Data Direction Control ......................................................................................................85
6.3.2 Internal Pullup Control .....................................................................................................85
6.3.3 Slew Rate Control .............................................................................................................85
Stop Modes ......................................................................................................................................86
Register Definition ..........................................................................................................................86
6.5.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) .................................................86
6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) .................................................89
6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) .................................................91
6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ...............................................93
6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ..................................................95
6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ...............................................97
Chapter 7
Keyboard Interrupt (S08KBIV1)
7.1
7.2
Introduction .....................................................................................................................................99
7.1.1 Port A and Keyboard Interrupt Pins ..................................................................................99
7.1.2 Features .............................................................................................................................99
7.1.3 KBI Block Diagram ........................................................................................................101
Register Definition ........................................................................................................................101
7.2.1 KBI Status and Control Register (KBISC) .....................................................................102
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
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Section Number
7.3
Title
Page
7.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................103
Functional Description ..................................................................................................................103
7.3.1 Pin Enables ......................................................................................................................103
7.3.2 Edge and Level Sensitivity ..............................................................................................103
7.3.3 KBI Interrupt Controls ....................................................................................................104
Chapter 8
Central Processor Unit (S08CPUV2)
8.1
8.2
8.3
8.4
8.5
Introduction ...................................................................................................................................105
8.1.1 Features ...........................................................................................................................105
Programmer’s Model and CPU Registers .....................................................................................106
8.2.1 Accumulator (A) .............................................................................................................106
8.2.2 Index Register (H:X) .......................................................................................................106
8.2.3 Stack Pointer (SP) ...........................................................................................................107
8.2.4 Program Counter (PC) ....................................................................................................107
8.2.5 Condition Code Register (CCR) .....................................................................................107
Addressing Modes .........................................................................................................................109
8.3.1 Inherent Addressing Mode (INH) ...................................................................................109
8.3.2 Relative Addressing Mode (REL) ...................................................................................109
8.3.3 Immediate Addressing Mode (IMM) ..............................................................................109
8.3.4 Direct Addressing Mode (DIR) ......................................................................................109
8.3.5 Extended Addressing Mode (EXT) ................................................................................110
8.3.6 Indexed Addressing Mode ..............................................................................................110
8.3.6.1 Indexed, No Offset (IX) ................................................................................110
8.3.6.2 Indexed, No Offset with Post Increment (IX+) .............................................110
8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................110
8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................110
8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................110
8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................110
8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................111
Special Operations .........................................................................................................................111
8.4.1 Reset Sequence ...............................................................................................................111
8.4.2 Interrupt Sequence ..........................................................................................................111
8.4.3 Wait Mode Operation ......................................................................................................112
8.4.4 Stop Mode Operation ......................................................................................................112
8.4.5 BGND Instruction ...........................................................................................................113
HCS08 Instruction Set Summary ..................................................................................................114
MC9S08GT16A/GT8A Data Sheet, Rev. 1
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Title
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Chapter 9
Internal Clock Generator (S08ICGV4)
9.1
9.2
9.3
9.4
9.5
Introduction ...................................................................................................................................125
9.1.1 Features ...........................................................................................................................127
9.1.2 Modes of Operation ........................................................................................................128
9.1.3 Block Diagram ................................................................................................................129
External Signal Description ..........................................................................................................129
9.2.1 EXTAL — External Reference Clock / Oscillator Input ................................................129
9.2.2 XTAL — Oscillator Output ............................................................................................129
9.2.3 External Clock Connections ...........................................................................................130
9.2.4 External Crystal/Resonator Connections ........................................................................130
Register Definition ........................................................................................................................131
9.3.1 ICG Control Register 1 (ICGC1) ....................................................................................131
9.3.2 ICG Control Register 2 (ICGC2) ....................................................................................133
9.3.3 ICG Status Register 1 (ICGS1) .......................................................................................134
9.3.4 ICG Status Register 2 (ICGS2) .......................................................................................135
9.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................135
9.3.6 ICG Trim Register (ICGTRM) .......................................................................................136
Functional Description ..................................................................................................................136
9.4.1 Off Mode (Off) ................................................................................................................137
9.4.1.1 BDM Active ..................................................................................................137
9.4.1.2 OSCSTEN Bit Set .........................................................................................137
9.4.1.3 Stop/Off Mode Recovery ..............................................................................137
9.4.2 Self-Clocked Mode (SCM) .............................................................................................137
9.4.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................138
9.4.4 FLL Engaged Internal Unlocked ....................................................................................139
9.4.5 FLL Engaged Internal Locked ........................................................................................139
9.4.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................139
9.4.7 FLL Engaged, External Clock (FEE) Mode ...................................................................139
9.4.7.1 FLL Engaged External Unlocked .................................................................140
9.4.7.2 FLL Engaged External Locked .....................................................................140
9.4.8 FLL Lock and Loss-of-Lock Detection ..........................................................................140
9.4.9 FLL Loss-of-Clock Detection .........................................................................................141
9.4.10 Clock Mode Requirements .............................................................................................142
9.4.11 Fixed Frequency Clock ...................................................................................................143
9.4.12 High Gain Oscillator .......................................................................................................143
Initialization/Application Information ..........................................................................................143
9.5.1 Introduction .....................................................................................................................143
9.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................145
9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................147
9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................149
9.5.5 Example #4: Internal Clock Generator Trim ..................................................................151
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
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Section Number
Title
Page
Chapter 10
Timer/PWM (S08TPMV2)
10.1 Introduction ...................................................................................................................................153
10.1.1 Features ...........................................................................................................................153
10.1.2 Features ...........................................................................................................................155
10.1.3 Block Diagram ................................................................................................................155
10.2 External Signal Description ..........................................................................................................157
10.2.1 External TPM Clock Sources ..........................................................................................157
10.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................157
10.3 Register Definition ........................................................................................................................157
10.3.1 Timer x Status and Control Register (TPMxSC) ............................................................158
10.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ................................................159
10.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ...............................160
10.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ......................................161
10.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ......................................162
10.4 Functional Description ..................................................................................................................163
10.4.1 Counter ............................................................................................................................163
10.4.2 Channel Mode Selection .................................................................................................164
10.4.2.1 Input Capture Mode ......................................................................................164
10.4.2.2 Output Compare Mode .................................................................................165
10.4.2.3 Edge-Aligned PWM Mode ...........................................................................165
10.4.3 Center-Aligned PWM Mode ...........................................................................................166
10.5 TPM Interrupts ..............................................................................................................................167
10.5.1 Clearing Timer Interrupt Flags .......................................................................................167
10.5.2 Timer Overflow Interrupt Description ............................................................................167
10.5.3 Channel Event Interrupt Description ..............................................................................168
10.5.4 PWM End-of-Duty-Cycle Events ...................................................................................168
Chapter 11
Serial Communications Interface (S08SCIV1)
11.1 Introduction ...................................................................................................................................169
11.1.1 Features ...........................................................................................................................171
11.1.2 Modes of Operation ........................................................................................................171
11.1.3 Block Diagram ................................................................................................................172
11.2 Register Definition ........................................................................................................................174
11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ..........................................................174
11.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................175
11.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................176
11.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................177
11.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................179
11.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................179
11.2.7 SCI Data Register (SCIxD) .............................................................................................180
MC9S08GT16A/GT8A Data Sheet, Rev. 1
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11.3 Functional Description ..................................................................................................................181
11.3.1 Baud Rate Generation .....................................................................................................181
11.3.2 Transmitter Functional Description ................................................................................181
11.3.2.1 Send Break and Queued Idle .........................................................................182
11.3.3 Receiver Functional Description .....................................................................................182
11.3.3.1 Data Sampling Technique .............................................................................183
11.3.3.2 Receiver Wakeup Operation .........................................................................183
11.3.3.2.1Idle-Line Wakeup .....................................................................184
11.3.3.2.2Address-Mark Wakeup .............................................................184
11.3.4 Interrupts and Status Flags ..............................................................................................184
11.3.5 Additional SCI Functions ...............................................................................................185
11.3.5.1 8- and 9-Bit Data Modes ...............................................................................185
11.3.5.2 Stop Mode Operation ....................................................................................185
11.3.5.3 Loop Mode ....................................................................................................186
11.3.5.4 Single-Wire Operation ..................................................................................186
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.1 Introduction ...................................................................................................................................187
12.1.1 Features ...........................................................................................................................189
12.1.2 Block Diagrams ..............................................................................................................190
12.1.2.1 SPI System Block Diagram ..........................................................................190
12.1.2.2 SPI Module Block Diagram ..........................................................................190
12.1.3 SPI Baud Rate Generation ..............................................................................................191
12.2 External Signal Description ..........................................................................................................192
12.2.1 SPSCK — SPI Serial Clock ............................................................................................192
12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................192
12.2.3 MISO — Master Data In, Slave Data Out ......................................................................192
12.2.4 SS — Slave Select ...........................................................................................................192
12.3 Modes of Operation .......................................................................................................................193
12.3.1 SPI in Stop Modes ..........................................................................................................193
12.4 Register Definition ........................................................................................................................193
12.4.1 SPI Control Register 1 (SPIC1) ......................................................................................193
12.4.2 SPI Control Register 2 (SPIC2) ......................................................................................194
12.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................195
12.4.4 SPI Status Register (SPIS) ..............................................................................................196
12.4.5 SPI Data Register (SPID) ................................................................................................197
12.5 Functional Description ..................................................................................................................198
12.5.1 SPI Clock Formats ..........................................................................................................198
12.5.2 SPI Interrupts ..................................................................................................................201
12.5.3 Mode Fault Detection .....................................................................................................201
12.6 Initialization/Application Information ..........................................................................................201
MC9S08GT16A/GT8A Data Sheet, Rev. 1
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12.6.1 SPI Module Initialization Example .................................................................................201
12.6.1.1 Initialization Sequence ..................................................................................201
12.6.1.2 Pseudo—Code Example ...............................................................................202
Chapter 13
Inter-Integrated Circuit (S08IICV1)
13.1 Introduction ...................................................................................................................................205
13.1.1 Features ...........................................................................................................................207
13.1.2 Modes of Operation ........................................................................................................207
13.1.3 Block Diagram ................................................................................................................208
13.2 External Signal Description ..........................................................................................................208
13.2.1 SCL — Serial Clock Line ...............................................................................................208
13.2.2 SDA — Serial Data Line ................................................................................................208
13.3 Register Definition ........................................................................................................................208
13.3.1 IIC Address Register (IICA) ...........................................................................................209
13.3.2 IIC Frequency Divider Register (IICF) ...........................................................................209
13.3.3 IIC Control Register (IICC) ............................................................................................212
13.3.4 IIC Status Register (IICS) ...............................................................................................213
13.3.5 IIC Data I/O Register (IICD) ..........................................................................................214
13.4 Functional Description ..................................................................................................................215
13.4.1 IIC Protocol .....................................................................................................................215
13.4.1.1 START Signal ...............................................................................................216
13.4.1.2 Slave Address Transmission .........................................................................216
13.4.1.3 Data Transfer .................................................................................................216
13.4.1.4 STOP Signal ..................................................................................................217
13.4.1.5 Repeated START Signal ...............................................................................217
13.4.1.6 Arbitration Procedure ....................................................................................217
13.4.1.7 Clock Synchronization ..................................................................................217
13.4.1.8 Handshaking .................................................................................................218
13.4.1.9 Clock Stretching ............................................................................................218
13.5 Resets ............................................................................................................................................218
13.6 Interrupts .......................................................................................................................................218
13.6.1 Byte Transfer Interrupt ....................................................................................................219
13.6.2 Address Detect Interrupt .................................................................................................219
13.6.3 Arbitration Lost Interrupt ................................................................................................219
Chapter 14
Analog-to-Digital Converter (S08ATDV3)
14.1 Introduction ...................................................................................................................................223
14.1.1 Features ...........................................................................................................................223
14.1.2 Modes of Operation ........................................................................................................223
14.1.2.1 Stop Mode .....................................................................................................223
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14.2
14.3
14.4
14.5
14.6
Title
Page
14.1.2.2 Power Down Mode .......................................................................................223
14.1.3 Block Diagram ................................................................................................................223
External Signal Description ..........................................................................................................224
14.2.1 ADP7–ADP0 — Channel Input Pins ..............................................................................225
14.2.2 VREFH, VREFL — ATD Reference Pins .........................................................................225
14.2.3 VDDAD, VSSAD — ATD Supply Pins ............................................................................225
Register Definition ........................................................................................................................225
14.3.1 ATD Control (ATDC) .....................................................................................................225
14.3.2 ATD Status and Control (ATDSC) ..................................................................................228
14.3.3 ATD Result Data (ATDRH, ATDRL) .............................................................................229
14.3.4 ATD Pin Enable (ATDPE) ..............................................................................................229
Functional Description ..................................................................................................................230
14.4.1 Mode Control ..................................................................................................................230
14.4.2 Sample and Hold .............................................................................................................230
14.4.3 Analog Input Multiplexer ................................................................................................232
14.4.4 ATD Module Accuracy Definitions ................................................................................232
Resets ............................................................................................................................................235
Interrupts .......................................................................................................................................235
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................237
15.1.1 Features ...........................................................................................................................238
15.2 Background Debug Controller (BDC) ..........................................................................................238
15.2.1 BKGD Pin Description ...................................................................................................239
15.2.2 Communication Details ..................................................................................................240
15.2.3 BDC Commands .............................................................................................................244
15.2.4 BDC Hardware Breakpoint .............................................................................................246
15.3 On-Chip Debug System (DBG) ....................................................................................................247
15.3.1 Comparators A and B ......................................................................................................247
15.3.2 Bus Capture Information and FIFO Operation ...............................................................247
15.3.3 Change-of-Flow Information ..........................................................................................248
15.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................248
15.3.5 Trigger Modes .................................................................................................................249
15.3.6 Hardware Breakpoints ....................................................................................................251
15.4 Register Definition ........................................................................................................................251
15.4.1 BDC Registers and Control Bits .....................................................................................251
15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................252
15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................253
15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................253
15.4.3 DBG Registers and Control Bits .....................................................................................254
15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................254
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
17
Section Number
15.4.3.2
15.4.3.3
15.4.3.4
15.4.3.5
15.4.3.6
15.4.3.7
15.4.3.8
15.4.3.9
Title
Page
Debug Comparator A Low Register (DBGCAL) .........................................254
Debug Comparator B High Register (DBGCBH) .........................................254
Debug Comparator B Low Register (DBGCBL) ..........................................254
Debug FIFO High Register (DBGFH) ..........................................................255
Debug FIFO Low Register (DBGFL) ...........................................................255
Debug Control Register (DBGC) ..................................................................256
Debug Trigger Register (DBGT) ..................................................................257
Debug Status Register (DBGS) .....................................................................258
Appendix A
Electrical Characteristics
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
Introduction ...................................................................................................................................259
Parameter Classification ................................................................................................................259
Absolute Maximum Ratings ..........................................................................................................259
Thermal Characteristics .................................................................................................................260
Electrostatic Discharge (ESD) Protection Characteristics ............................................................262
DC Characteristics .........................................................................................................................262
Supply Current Characteristics ......................................................................................................266
ATD Characteristics ......................................................................................................................272
Internal Clock Generation Module Characteristics .......................................................................274
A.9.1 ICG Frequency Specifications ........................................................................................275
A.10 AC Characteristics .........................................................................................................................276
A.10.1 Control Timing ...............................................................................................................277
A.10.2 Timer/PWM (TPM) Module Timing ..............................................................................278
A.10.3 SPI Timing ......................................................................................................................280
A.11 FLASH Specifications ...................................................................................................................283
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................285
B.1.1 Device Numbering Scheme ............................................................................................285
B.2 Mechanical Drawings ....................................................................................................................285
MC9S08GT16A/GT8A Data Sheet, Rev. 1
18
Freescale Semiconductor
Chapter 1
Device Overview
1.1
Introduction
The MC9S08GT16A/GT8A are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types (see Table 1-1).
1.1.1
Devices in the MC9S08GT16A/GT8A Series
Table 1-1 lists the devices available in the MC9S08GT16A/GT8A series and summarizes the differences
among them.
Table 1-1. Devices in the MC9S08GT16A/GT8A Series
Device
MC9S08GT16A
MC9S08GT8A
1.1.2
FLASH
16K
8K
RAM
2K
1K
TPM
ATD
KBI
I/O
Packages
(1) 3-ch, (1) 2-ch, 16-bit
8
8
39
48 QFN
(2) 2-ch, 16-bit
8
8
36
44 QFP
(2) 2-ch, 16-bit
8
8
34
42 SDIP
(1) 2-ch, (1) 1-ch, 16-bit
4
4
24
32 QFN
(1) 3-ch, (1) 2-ch, 16-bit
8
8
39
48 QFN
(2) 2-ch, 16-bit
8
8
36
44 QFP
(2) 2-ch, 16-bit
8
8
34
42 SDIP
(1) 2-ch, (1) 1-ch, 16-bit
4
4
24
32 QFN
MCU Block Diagram
This block diagrams show the structure of the MC9S08GT16A/GT8A MCUs.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
19
VREFL
VREFH
VSSAD
VDDAD
Device Overview
BKGD
8
4
4
COP
IRQ
LVD
SCL
SDA
INTER-IC (IIC)
RXD2
TXD2
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
CH1
CH0
2-CHANNEL TIMER/PWM
(TPM2)
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 1-1. MC9S08GT16A/GT8A Block Diagram
MC9S08GT16A/GT8A Data Sheet, Rev. 1
20
Freescale Semiconductor
Device Overview
Table 1-2 lists the functional versions of the on-chip modules.
Table 1-2. Block Versions
1.2
Module
Version
Analog-to-Digital Converter (ATD)
3
Internal Clock Generator (ICG)
4
Inter-Integrated Circuit (IIC)
1
Keyboard Interrupt (KBI)
1
Serial Communications Interface (SCI)
1
Serial Peripheral Interface (SPI)
3
Timer Pulse-Width Modulator (TPM)
2
Central Processing Unit (CPU)
2
System Clock Distribution
ICGERCLK
SYSTEM
CONTROL
LOGIC
TPM1
TPM2
IIC
SCI1
SCI2
SPI
RTI
FFE
÷2
ICG
FIXED FREQ CLOCK (XCLK)
ICGOUT
÷2
BUSCLK
ICGLCLK*
CPU
BDC
COP
* ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A.
ATD
RAM
ATD has min and max
frequency requirements.
See Chapter 14, “Analog-to-Digital Converter
(S08ATDV3)”
and Appendix A, “Electrical
Characteristics.”
FLASH
FLASH has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics”.
Figure 1-2. System Clock Distribution Diagram
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
21
Device Overview
Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock
connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following:
— The external crystal oscillator
— An external clock source
— The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
Control bits inside the ICG determine which source is connected.
• FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency
of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK.
Otherwise the fixed-frequency clock will be BUSCLK.
• ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed
up BDC communications in systems where the bus clock is slow.
• ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
22
Freescale Semiconductor
Chapter 2
Pins and Connections
2.1
Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
PTA2/KBIP2
37
PTA4/KBIP4
39
38 PTA3/KBIP3
PTA5/KBIP5
40
41 PTA6/KBIP6
42 PTA7/KBIP7
VDDAD
44 VSSAD
45 PTG0/BKGD/MS
46 PTG1/XTAL
43
RESET 1
47 PTG2/EXTAL
Device Pin Assignment
48 PTG3
2.2
36
PTA1/KBIP1
IRQ 12
25
PTB0/ADP0
24
PTB1/ADP1
PTD4/TPM2CH1
26
23
PTE1/RxD1 11
PTD3/TPM2CLK/TPM2CH0
PTB2/ADP2
22
27
PTD2/TPM1CH2
PTE0/TxD1 10
21
PTB3/ADP3
PTD1/TPM1CH1
28
20
PTC7 9
PTD0/TPM1CLK/TPM1CH0
PTB4/ADP4
19
29
VDD
PTC6 8
18
30 PTB5/ADP5
VSS2
PTC5 7
17
31 PTB6/ADP6
VSS1
PTC4 6
16
32 PTB7/ADP7
PTE5/SPSCK
PTC3/SCL 5
15
33 VREFH
PTE4/MOSI
PTC2/SDA 4
14
34 VREFL
PTE3/MISO
PTC1/RxD2 3
13
35 PTA0/KBIP0
PTE2/SS
PTC0/TxD2 2
Figure 2-1. MC9S08GT16A/GT8A in 48-Pin QFN Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
23
PTA3/KBIP3
PTA2/KBIP2
34
PTA6/KBIP6
38
35
PTA7/KBIP7
39
PTA4/KBIP4
VDDAD
40
36
VSSAD
41
PTA5/KBIP5
PTG0/BKGD/MS
42
37
PTG1/XTAL
43
PTB6/ADP6
PTC5
7
27
PTB5/ADP5
PTC6
8
26
PTB4/ADP4
PTE0/TxD1
9
25
PTB3/ADP3
PTE1/RxD1
10
24
PTB2/ADP2
23
PTB1/ADP1
IRQ 11
22
28
PTB0/ADP0
6
21
PTC4
PTD4/TPM2CH1
PTB7/ADP7
20
29
PTD3/TPM2CLK/TPM2CH0
5
19
PTC3/SCL
PTD1/TPM1CH1
VREFH
18
30
PTD0/TPM1CLK/TPM1CH0
4
17
PTC2/SDA
VDD
VREFL
16
31
VSS
3
15
PTC1/RxD2
PTE5/SPSCK
PTA0/KBIP0
14
32
PTE4/MOSI
2
13
PTA1/KBIP1
PTE3/MISO
PTC0/TxD2
PTG2/EXTAL
33
12
1
PTE2/SS
RESET
44
Pins and Connections
Figure 2-2. MC9S08GT16A/GT8A in 44-Pin QFP Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
24
Freescale Semiconductor
Pins and Connections
VDDAD
1
42
PTA7/KBIP7
VSSAD
2
41
PTA6/KBIP6
PTG0/BKGD/MS
3
40
PTA5/KBIP5
PTG1/XTAL
4
39
PTA4/KBIP4
PTG2/EXTAL
5
38
PTA3/KBIP3
RESET
6
37
PTA2/KBIP2
PTC0/TxD2
7
36
PTA1/KBIP1
PTC1/RXD2
8
35
PTA0/KBIP0
PTC2/SDA
9
34
VREFL
PTC3/SCL
10
33
VREFH
PTC4
11
32
PTB7/ADP7
PTE0/TxD1
12
31
PTB6/ADP6
PTE1/RxD1
13
30
PTB5/ADP5
IRQ
14
29
PTB4/ADP4
PTE2/SS
15
28
PTB3/ADP3
PTE3/MISO
16
27
PTB2/ADP2
PTE4/MOSI
17
26
PTB1/ADP1
PTE5/SPSCK
18
25
PTB0/ADP0
VSS
19
24
PTD4/TPM2CH1
VDD
20
23
PTD3/TPM2CLK/TPM2CH0
PTD0/TPM1CLK/TPM1CH0
21
22
PTD1/TPM1CH1
Figure 2-3. MC9S08GT16A/GT8A in 42-Pin SDIP Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
25
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD
VSSAD
VDDAD
PTA7/KBIP7
PTA6/KBIP6
PTA5/KBIP5
Pins and Connections
32
31
30
29
28
27
26
25
24 PTA4/KBIP4
RESET 1
PTC0/TxD2 2
23 VREFL
PTC1/RxD2 3
22 VREFH
PTC2/SDA 4
21 PTB3/ADP3
PTC3/SCL 5
20 PTB2/ADP2
PTE0/TxD1 6
19
PTE1/RxD1 7
18 PTB0/ADP0
PTB1/ADP1
17 PTD3/TPM2CLK/TPM2CH0
9
10
11
12
13
14
15
16
PTE2/SS
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
VSS
VDD
PTD0/TPM1CLK/TPM1CH0
PTD1/TPM1CH1
IRQ 8
Figure 2-4. MC9S08GT16A/GT8A in 32-Pin QFN Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
26
Freescale Semiconductor
Pins and Connections
2.3
Recommended System Connections
Figure 2-5 shows pin connections that are common to almost all MC9S08GT16A application systems. A
more detailed discussion of system connections follows.
VREFH
CBYAD
0.1 µF
+
3V
CBLK +
10 µF
PTA1/KBIP1
MC9S08GT16A
PTA2/KBIP2
VSSAD
VREFL
VDD
VDD
SYSTEM
POWER
VDDAD
PTA0/KBIP0
PORT
A
PTA3/KBIP3
PTA4/KBIP4
PTA5/KBIP5
PTA6/KBIP6
CBY
0.1 µF
PTA7/KBIP7
VSS
VSS
NOTE4
PTB0/ADP0
PTB1/ADP1
BACKGROUND HEADER
PTB2/ADP2
BKGD/MS
VDD
PORT
B
VDD
PTB3/ADP3
PTB4/ADP4
PTB5/ADP5
PTB6/ADP6
4.7 kΩ–10 kΩ
PTB7/ADP7
RESET
NOTE 3
0.1 µF
PTC0/TxD2
PTC1/RxD2
OPTIONAL
MANUAL
RESET
PTC2/SDA
VDD
ASYNCHRONOUS
INTERRUPT
INPUT
PORT
C
4.7 kΩ–10 kΩ
PERIPHERAL
INTERFACE TO
APPLICATION
SYSTEM
PTC3/SCL
PTC4
PTC5
IRQ
NOTE 3
0.1 µF
I/O AND
PTC6
PTC7
PTD0/TPM1CLK/TPM1CH0
PTG0/BKDG/MS
PTD1/TPM1CH1
PTG1/XTAL
PORT
G
PTG2/EXTAL
PORT
D
PTG3
NOTE 1
RF
PTD2/TPM1CH2
PTD3/TPM2CLK/TPM2CH0
PTD4/TPM2CH1
PTE0/TxD1
RS XTAL
PTE1/RxD1
C1
X1
C2
EXTAL
PORT
E
PTE2/SS
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
NOTES:
1. Not required if using the internal oscillator option.
2. The 48-pin QFN has 2 VSS pins (VSS1 and VSS2), both of which must be connected to GND.
3. RC filters on RESET and IRQ are recommended for EMC-sensitive applications and systems.
Figure 2-5. Basic System Connections
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
27
Pins and Connections
2.3.1
VDD, VSS, VDDAD, VSSAD, VREFH, VREFL — Power and Voltage
References
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-µF ceramic bypass capacitor located as close to the MCU power pins as
practical to suppress high-frequency noise.
NOTE
The 48-pin QFN version of the MC9S08GT16A/GT8A has two adjacent
VSS pins. Both pins must be connected to ground with zero impedance
between them.
VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to
the ATD. A 0.1-µF ceramic bypass capacitor should be located as close to the MCU power pins as practical
to suppress high-frequency noise.
VREFH and VREFL are the reference voltages for the analog-to-digital converter and for most accurate
performance, they must be connected directly to VDDAD and VSSAD with the shortest traces possible.
2.3.2
PTG1/XTAL, PTG2/EXTAL — Oscillator
Immediately after reset, the MCU uses an internally generated clock (self-clocked mode — fSelf_reset), that
is approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup
and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay.
This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the
MCU. For more information on the ICG, see Chapter 9, “Internal Clock Generator (S08ICGV4).”
The oscillator amplitude on XTAL and EXTAL is gain limited for low-power oscillation. Typically, these
pins have a 1-V peak-to-peak signal. For noisy environments, the high gain output (HGO) bit can be set to
enable rail-to-rail oscillation.
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in
either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or
ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output
pin can be used as general I/O. The external oscillator amplitude must not exceed VDD.
Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity
and lower values reduce gain and (in extreme cases) could prevent startup.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
28
Freescale Semiconductor
Pins and Connections
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2 which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.3.3
RESET — External Reset Pin
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of fSelf_reset, released, and sampled again approximately
38 cycles of fSelf_reset later. If reset was caused by an internal source such as low-voltage reset or watchdog
timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause
of reset and records it by setting a corresponding bit in the system control reset status register (SRS).
For EMC-sensitive applications, an external RC filter is recommended on the RESET pin. See Figure 2-5
for an example.
2.3.4
PTG0/BKGD/MS — Background / Mode Select
The background/mode select (BKGD/MS) shares its function with an I/O port pin. While in reset, the pin
functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and
can be used for background debug communication. While functioning as a background/mode select pin,
the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew
rate control. When used as an I/O port (PTG0) the pin is limited to output only.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there should never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
29
Pins and Connections
2.3.5
IRQ — External Interrupt Request Pin
IRQ is a dedicated pin with both pullup and pulldown devices built in. This pin has no output capabilities.
After a system reset, the IRQ pin is disabled and must be enabled before use. See Section 5.4.2, “IRQ —
External Interrupt Request Pin” for more details.
For EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for
an example.
2.3.6
General-Purpose I/O and Peripheral Ports
The remaining 36 pins are shared among general-purpose I/O and on-chip peripheral functions such as
timers and serial I/O systems. (Three of these pins are not bonded out on the 44-pin package, five are not
bonded out on the 42-pin package, and 15 are not bonded out on the 32-pin package.) Immediately after
reset, all 36 of these pins are configured as high-impedance general-purpose inputs with internal pullup
devices disabled.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from Table 2-1.
Table 2-1. Pin Sharing References
Port Pins
Reference1
Alternate Function
PTA7–PTA0
KBIP7–KBIP0
Chapter 7, “Keyboard Interrupt (S08KBIV1)”
PTB7–PTB0
ADP7–ADP0
Chapter 14, “Analog-to-Digital Converter (S08ATDV3)”
PTC3–PTC2
SCL–SDA
Chapter 13, “Inter-Integrated Circuit (S08IICV1)”
PTC1–PTC0
RxD2–TxD2
Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTD4–PTD3
TPM2CH1–TPM2CH0, TPM2CLK
Chapter 10, “Timer/PWM (S08TPMV2)”
PTD2–PTD0
TPM1CH2–TPM1CH0, TPM1CLK
Chapter 10, “Timer/PWM (S08TPMV2)”
PTE5
PTE4
PTE3
PTE2
SPSCK
MISO
MOSI
SS
Chapter 12, “Serial Peripheral Interface (S08SPIV3)”
PTE1–PTE0
RxD1–TxD1
Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTG2–PTG1
EXTAL–XTAL
Chapter 9, “Internal Clock Generator (S08ICGV4)”
PTG0
BKGD/MS
Chapter 15, “Development Support”
PTC7–PTC4
PTG3
1
See this section for information about modules that share these pins.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
30
Freescale Semiconductor
Pins and Connections
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output,” for details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured
as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device
rather than a pullup device.
2.3.7
Signal Properties Summary
Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hardwired to internal circuits.
Table 2-2. Signal Properties
Pin
Name
High Current
Pin
Output
Slew 1
Pull-Up2
VDD
—
—
—
VSS
—
—
—
VDDAD
—
—
—
VSSAD
—
—
—
VREFH
—
—
—
VREFL
—
—
—
Y
N
Y
Pin contains integrated pullup.
IRQPE must be set to enable IRQ function.
IRQ does not have a clamp diode to VDD.
IRQ should not be driven above VDD.
Pullup/pulldown active when IRQ pin
function enabled. Pullup forced on when
IRQ enabled for falling edges; pulldown
forced on when IRQ enabled for rising
edges.
RESET
Dir
I/O
IRQ
I
—
—
Y
PTA0/KBIP0
I/O
N
SWC
SWC
PTA1/KBIP1
I/O
N
SWC
SWC
PTA2/KBIP2
I/O
N
SWC
SWC
PTA3/KBIP3
I/O
N
SWC
SWC
PTA4/KBIP4
I/O
N
SWC
SWC
PTA5/KBIP5
I/O
N
SWC
SWC
PTA6/KBIP6
I/O
N
SWC
SWC
PTA7/KBIP7
I/O
N
SWC
SWC
PTB0/ADP0
I/O
N
SWC
SWC
PTB1/ADP1
I/O
N
SWC
SWC
PTB2/ADP2
I/O
N
SWC
SWC
Comments
The 48-pin QFN package has two VSS pins
— VSS1 and VSS2.
Pullup/pulldown active when KBI pin
function enabled. Pullup forced on when
KBIPx enabled for falling edges; pulldown
forced on when KBIPx enabled for rising
edges.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
31
Pins and Connections
Table 2-2. Signal Properties (continued)
1
2
Pin
Name
Dir
High Current
Pin
Output
Slew 1
Pull-Up2
PTB3/ADP3
I/O
N
SWC
SWC
PTB4/ADP4
I/O
N
SWC
SWC
Not available on 32-pin pkg
PTB5/ADP5
I/O
N
SWC
SWC
Not available on 32-pin pkg
PTB6/ADP6
I/O
N
SWC
SWC
Not available on 32-pin pkg
PTB7/ADP7
I/O
N
SWC
SWC
Not available on 32-pin pkg
PTC0/TxD2
I/O
Y
SWC
SWC
PTC1/RxD2
I/O
Y
SWC
SWC
When pin is configured for SCI function, pin
is configured for partial output drive.
PTC2/SDA
I/O
Y
SWC
SWC
PTC3/SCL
I/O
Y
SWC
SWC
PTC4
I/O
Y
SWC
SWC
Not available on 32-pin pkg
PTC5
I/O
Y
SWC
SWC
Not available on 32-pin or 42-pin pkg
PTC6
I/O
Y
SWC
SWC
Not available on 32-pin or 42-pin pkg
Not available on 32-pin, 42- or 44-pin pkg
PTC7
I/O
Y
SWC
SWC
PTD0/TPM1CLK/TPM1CH0
I/O
N
SWC
SWC
PTD1/TPM1CH1
I/O
N
SWC
SWC
PTD2/TPM1CH2
I/O
N
SWC
SWC
PTD3/TPM2CLK/TPM2CH0
I/O
N
SWC
SWC
PTD4/TPM2CH1
I/O
N
SWC
SWC
Comments
Not available on 32-pin, 42- or 44-pin pkg
Not available on 32-pin pkg
PTE0/TxD1
I/O
N
SWC
SWC
PTE1/RxD1
I/O
N
SWC
SWC
PTE2/SS
I/O
N
SWC
SWC
PTE3/MISO
I/O
N
SWC
SWC
PTE4/MOSI
I/O
N
SWC
SWC
PTE5/SPSCK
I/O
N
SWC
SWC
PTG0/BKGD/MS
O
N
SWC
SWC
Pullup enabled and slew rate disabled when
BDM function enabled.
PTG1/XTAL
I/O
N
SWC
SWC
Pullup and slew rate disabled when XTAL
pin function.
PTG2/EXTAL
I/O
N
SWC
SWC
Pullup and slew rate disabled when EXTAL
pin function.
PTG3
I/O
N
SWC
SWC
Not available on 32-pin, 42-, or 44-pin pkg
SWC is software controlled slew rate, the register is associated with the respective port.
SWC is software controlled pullup resistor, the register is associated with the respective port.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
32
Freescale Semiconductor
Chapter 3
Modes of Operation
3.1
Introduction
The operating modes of the MC9S08GT16A/GT8A are described in this section. Entry into each mode,
exit from each mode, and functionality while in each of the modes are described.
3.1.1
•
•
•
3.2
Features
Active background mode for code development
Wait mode:
— CPU shuts down to conserve power
— System clocks running
— Full voltage regulation maintained
Stop modes:
— Stop1 — Full power down of internal circuits for maximum power savings
— Stop2 — Partial power down of internal circuits, RAM contents retained
— Stop3 — All internal circuits powered for fast recovery
Run Mode
This is the normal operating mode for the MC9S08GT16A/GT8A. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.3
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip ICE debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
33
Modes of Operation
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user’s application program.
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed while the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can be executed only while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user’s application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the
MC9S08GT16A/GT8A is shipped from the Freescale Semiconductor factory, the FLASH program
memory is erased by default unless specifically noted so there is no program that could be executed in run
mode until the FLASH memory is initially programmed. The active background mode can also be used to
erase and reprogram the FLASH memory after it has been previously programmed.
For additional information about the active background mode, refer to Chapter 15, “Development
Support.”
3.4
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
34
Freescale Semiconductor
Modes of Operation
3.5
Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the
system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set
when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
Table 3-1. Stop Mode Behavior
1
2
Mode
PDC
PPDC
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ATD
Regulator
I/O Pins
RTI
Stop1
1
0
Off
Off
Off
Disabled1
Off
Reset
Off
Stop2
1
1
Off
Standby
Off
Disabled
Standby
States
held
Optionally on
Stop3
0
Don’t
care
Standby
Standby
Off2
Disabled
Standby
States
held
Optionally on
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
3.5.1
Stop1 Mode
The stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry
of the MCU to be powered down. Stop1 can be entered only if the LVD circuit is not enabled in stop modes
(either LVDE or LVDSE not set).
When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned
off. The voltage regulator is in a low-power standby state, as is the ATD.
Exit from stop1 is performed by asserting either of the wake-up pins on the MCU: RESET or IRQ. IRQ is
always an active low input when the MCU is in stop1, regardless of how it was configured before entering
stop1.
Entering stop1 mode automatically asserts LVD. Stop1 cannot be exited until VDD > VLVDH/L rising (VDD
must rise above the LVI rearm voltage).
Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will
take the reset vector.
3.5.2
Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop
modes (either LVDE or LVDSE not set).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
35
Modes of Operation
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2,
these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a 1 is written to PPDACK in SPMSC2.
Exit from stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI
interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured
before entering stop2.
Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.5.3
Stop3 Mode
Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the
internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched
at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the
pins being maintained.
Exit from stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time
interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
MC9S08GT16A/GT8A Data Sheet, Rev. 1
36
Freescale Semiconductor
Modes of Operation
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
3.5.4
Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM
is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain
active when the MCU enters stop mode so background debug communication is still possible. In addition,
the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.
Table 3-2. BDM Enabled Stop Mode Behavior
1
Mode
PDC
PPDC
Stop3
Don’t
care
Don’t
care
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ATD
Regulator
I/O Pins
RTI
Standby
Standby
Active
Disabled1
Active
States
held
Optionally on
Either ATD stop mode or power-down mode depending on the state of ATDPU.
3.5.5
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
1
Mode
PDC
PPDC
Stop3
Don’t
care
Don’t
care
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ATD
Regulator
I/O Pins
RTI
Standby
Standby
Standby
Disabled1
Active
States
held
Optionally on
Either ATD stop mode or power-down mode depending on the state of ATDPU.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
37
Modes of Operation
3.5.6
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.5.1, “Stop1
Mode,” Section 3.5.2, “Stop2 Mode,” and Section 3.5.3, “Stop3 Mode,” for specific information on system
behavior in stop modes.
I/O Pins
• All I/O pin states remain unchanged when the MCU enters stop3 mode.
• If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop.
• If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state
upon entry into stop.
Memory
• All RAM and register contents are preserved while the MCU is in stop3 mode.
• All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and
pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped
register data into RAM before entering stop2 and restore the data upon exit from stop2.
• All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved.
The MCU must be initialized as upon reset. The contents of the FLASH memory are nonvolatile
and are preserved in any of the stop modes.
ICG — In stop3 mode, the ICG enters its low-power standby state. Either the oscillator or the internal
reference may be kept running when the ICG is in standby by setting the appropriate control bit. In both
stop2 and stop1 modes, the ICG is turned off. Neither the oscillator nor the internal reference can be kept
running in stop2 or stop1, even if enabled within the ICG module.
TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules
halt operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM modules will be reset
upon wake-up from stop and must be reinitialized.
ATD — When the MCU enters stop mode, the ATD will enter a low-power standby state. No conversion
operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the ATD will
be reset upon wake-up from stop and must be reinitialized.
KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are
capable of waking the MCU from stop3. The KBI is disabled in stop1 and stop2 and must be reinitialized
after waking up from either of these modes.
SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules
halt operation. If the MCU is configured to go into stop2 or stop1 mode, the SCI modules will be reset
upon wake-up from stop and must be reinitialized.
SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from
stop and must be reinitialized.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
38
Freescale Semiconductor
Modes of Operation
IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from
stop and must be reinitialized.
Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any
of the stop modes unless the LVD is enabled in stop mode or BDM is enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
39
Modes of Operation
MC9S08GT16A/GT8A Data Sheet, Rev. 1
40
Freescale Semiconductor
Chapter 4
Memory
4.1
MC9S08GT16A/GT8A Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08GT16A/GT8A series of MCUs consists of RAM,
FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers
are divided into three groups:
• Direct-page registers (0x0000 through 0x007F)
• High-page registers (0x1800 through 0x182B)
• Nonvolatile registers (0xFFB0 through 0xFFBF)
0x0000
0x0000
DIRECT PAGE REGISTERS
0x007F
0x0080
RAM 2048 BYTES
0x087F
0x0880
DIRECT PAGE REGISTERS
RAM 1024 BYTES
Reserved 1024 BYTES
0x047F
0x0480
0x087F
0x0880
UNIMPLEMENTED
UNIMPLEMENTED
UNIMPLEMENTED
4992
3968BYTES
BYTES
3968 BYTES
0x17FF
0x1800
0x17FF
0x1800
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
0x182B
0x182C
0x182B
0x182C
UNIMPLEMENTED
UNIMPLEMENTED
42964 BYTES
42964 BYTES
0xBFFF
0xC000
FLASH
Reserved
0xBFFF
0xC000
8192 BYTES
16384 BYTES
FLASH
8192 BYTES
0xDFFF
0xE000
0xFFFF
0xFFFF
MC9S08GT16A
0x007F
0x0080
MC9S08GT8A
Figure 4-1. MC9S08GT16A/GT8A Memory Map
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
41
Memory
4.1.1
Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale-provided equate file for the MC9S08GT16A/GT8A. For more details
about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets,
Interrupts, and System Configuration.”
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
Vector
Vector Name
0xFFC0:FFC1
Unused Vector Space
(available for user program)
0xFFCA:FFCB
0xFFCC:FFCD
RTI
Vrti
0xFFCE:FFCF
IIC
Viic
0xFFD0:FFD1
ATD Conversion
Vatd
0xFFD2:FFD3
Keyboard
Vkeyboard
0xFFD4:FFD5
SCI2 Transmit
Vsci2tx
0xFFD6:FFD7
SCI2 Receive
Vsci2rx
0xFFD8:FFD9
SCI2 Error
Vsci2err
0xFFDA:FFDB
SCI1 Transmit
Vsci1tx
0xFFDC:FFDD
SCI1 Receive
Vsci1rx
0xFFDE:FFDF
SCI1 Error
Vsci1err
0xFFE0:FFE1
SPI
Vspi
0xFFE2:FFE3
TPM2 Overflow
Vtpm2ovf
0xFFE4:FFE9
Unused Vector Space
(available for user program)
0xFFEA:FFEB
TPM2 Channel 1
Vtpm2ch1
0xFFEC:FFED
TPM2 Channel 0
Vtpm2ch0
0xFFEE:FFEF
TPM1 Overflow
Vtpm1ovf
0xFFF0:FFF1
TPM1 Channel 2
Vtpm1ch2
0xFFF2:FFF3
TPM1 Channel 1
Vtpm1ch1
0xFFF4:FFF5
TPM1 Channel 0
Vtpm1ch0
0xFFF6:FFF7
ICG
Vicg
0xFFF8:FFF9
Low Voltage Detect
Vlvd
0xFFFA:FFFB
IRQ
Virq
0xFFFC:FFFD
SWI
Vswi
0xFFFE:FFFF
Reset
Vreset
MC9S08GT16A/GT8A Data Sheet, Rev. 1
42
Freescale Semiconductor
Memory
4.2
Register Addresses and Bit Assignments
The registers in the MC9S08GT16A/GT8A are divided into these three groups:
• Direct-page registers are located in the first 128 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at
0xFFB0–0xFFBF.
Nonvolatile register locations include:
— Three values which are loaded into working registers at reset
— An 8-byte backdoor comparison key which optionally allows a user to gain controlled access
to secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only
requires the lower byte of the address. Because of this, the lower byte of the address in column one is
shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In
Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart
from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with
a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
43
Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address
Register Name
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
PTAD
PTAPE
PTASE
PTADD
PTBD
PTBPE
PTBSE
PTBDD
PTCD
PTCPE
PTCSE
PTCDD
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
0x001A
0x001B
0x001C
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
PTDD
PTDPE
PTDSE
PTDDD
PTED
PTEPE
PTESE
PTEDD
IRQSC
Reserved
KBISC
KBIPE
SCI1BDH
SCI1BDL
SCI1C1
SCI1C2
SCI1S1
SCI1S2
SCI1C3
SCI1D
SCI2BDH
SCI2BDL
SCI2C1
SCI2C2
SCI2S1
SCI2S2
SCI2C3
SCI2D
Bit 7
6
5
4
3
2
1
Bit 0
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
PTAPE7
PTAPE6
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
PTASE7
PTASE6
PTASE5
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
PTADD7
PTADD6
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
PTADD0
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
PTCD7
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
PTCPE7
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
PTCSE7
PTCSE6
PTCSE5
PTCSE4
PTCSE3
PTCSE2
PTCSE1
PTCSE0
PTCDD7
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
PTCDD0
0
0
0
PTDD4
PTDD3
PTDD2
PTDD1
PTDD0
0
0
0
PTDPE4
PTDPE3
PTDPE2
PTDPE1
PTDPE0
0
0
0
PTDSE4
PTDSE3
PTDSE2
PTDSE1
PTDSE0
0
0
0
PTDDD4
PTDDD3
PTDDD2
PTDDD1
PTDDD0
0
0
PTED5
PTED4
PTED3
PTED2
PTED1
PTED0
0
0
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
0
0
PTESE5
PTESE4
PTESE3
PTESE2
PTESE1
PTESE0
0
0
PTEDD5
PTEDD4
PTEDD3
PTEDD2
PTEDD1
PTEDD0
0
0
IRQEDG
IRQPE
IRQF
IRQACK
IRQIE
IRQMOD
—
—
—
—
—
—
—
—
KBEDG7
KBEDG6
KBEDG5
KBEDG4
KBF
KBACK
KBIE
KBIMOD
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
0
0
0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0
0
0
0
0
0
0
RAF
R8
T8
TXDIR
0
ORIE
NEIE
FEIE
PEIE
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0
0
0
0
0
0
0
RAF
R8
T8
TXDIR
0
ORIE
NEIE
FEIE
PEIE
Bit 7
6
5
4
3
2
1
Bit 0
MC9S08GT16A/GT8A Data Sheet, Rev. 1
44
Freescale Semiconductor
Memory
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address
Register Name
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
0x0030
0x0031
0x0032
0x0033
SPIC1
SPIC2
SPIBR
SPIS
Reserved
SPID
Reserved
Reserved
TPM1SC
TPM1CNTH
TPM1CNTL
TPM1MODH
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
0x003E–
0x0043
0x0044
0x0045
0x0046
0x0047
0x0048
0x0049
0x004A
0x004B
0x004C
0x004D
0x004E
0x004F
0x0050
0x0051
0x0052
0x0053
TPM1MODL
TPM1C0SC
TPM1C0VH
TPM1C0VL
TPM1C1SC
TPM1C1VH
TPM1C1VL
TPM1C2SC
TPM1C2VH
TPM1C2VL
Reserved
PTGD
PTGPE
PTGSE
PTGDD
ICGC1
ICGC2
ICGS1
ICGS2
ICGFLTU
ICGFLTL
ICGTRM
Reserved
ATDC
ATDSC
ATDRH
ATDRL
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
SPRF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
PTGD3
PTGD2
PTGD1
PTGD0
0
0
0
0
PTGPE3
PTGPE2
PTGPE1
PTGPE0
0
0
0
0
PTGSE3
PTGSE2
PTGSE1
PTGSE0
0
PTGDD2
PTGDD1
PTGDD0
OSCSTEN
LOCD
0
0
0
0
HGO
RANGE
REFS
LOLRE
PTGDD3
CLKS
MFD
CLKST
LOCRE
RFD
REFST
LOLS
LOCK
LOCS
0
0
0
0
0
0
0
0
0
0
ERCS
ICGIF
0
DCOS
0
0
FLT
FLT
TRIM
0
0
0
0
ATDPU
DJM
RES8
SGN
0
0
CCF
ATDIE
ATDCO
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
PRS
ATDCH
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
45
Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address
0x0054
0x0055–
0x0057
0x0058
0x0059
0x005A
0x005B
0x005C
0x005D–
0x005F
0x0060
0x0061
0x0062
0x0063
0x0064
0x0065
0x0066
0x0067
0x0068
0x0069
0x006A
0x006B–
0x007F
Register Name
ATDPE
Reserved
IICA
IICF
IICC
IICS
IICD
Reserved
TPM2SC
TPM2CNTH
TPM2CNTL
TPM2MODH
TPM2MODL
TPM2C0SC
TPM2C0VH
TPM2C0VL
TPM2C1SC
TPM2C1VH
TPM2C1VL
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
ATDPE7
ATDPE6
ATDPE5
ATDPE4
ATDPE3
ATDPE2
ATDPE1
ATDPE0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADDR
0
MULT
ICR
IICEN
IICIE
MST
TX
TXAK
RSTA
0
0
TCF
IAAS
BUSY
ARBL
0
SRW
IICIF
RXAK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
Bit 15
14
13
12
11
10
9
Bit 8
DATA
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary
Address
0x1800
0x1801
0x1802
0x1803 –
0x1805
0x1806
0x1807
0x1808
0x1809
0x180A
0x180B–
0x180F
0x1810
Register Name
SRS
SBDFR
SOPT
Reserved
SDIDH
SDIDL
SRTISC
SPMSC1
SPMSC2
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
ICG
LVD
0
0
0
0
0
0
0
0
BDFR
COPE
COPT
STOPE
—
0
0
BKGDPE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTIF
RTIACK
RTICLKS
RTIE
0
RTIS2
RTIS1
RTIS0
LVDF
LVDACK
LVDIE
LVDRE
LVDSE
LVDE
0
0
LVWF
LVWACK
LVDV
LVWV
PPDF
PPDACK
PDC
PPDC
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DBGCAH
Bit 15
14
13
12
11
10
9
Bit 8
MC9S08GT16A/GT8A Data Sheet, Rev. 1
46
Freescale Semiconductor
Memory
Table 4-3. High-Page Register Summary (continued)
Address
0x1811
0x1812
0x1813
0x1814
0x1815
0x1816
0x1817
0x1818
0x1819–
0x181F
0x1820
0x1821
0x1822
0x1823
0x1824
0x1825
0x1826
0x1827–
0x182B
Register Name
DBGCAL
DBGCBH
DBGCBL
DBGFH
DBGFL
DBGC
DBGT
DBGS
Reserved
FCDIV
FOPT
Reserved
FCNFG
FPROT
FSTAT
FCMD
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
TRGSEL
BEGIN
0
0
TRG3
TRG2
TRG1
TRG0
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIVLD
PRDIV8
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
—
—
—
—
—
—
—
—
0
0
KEYACC
0
0
0
0
0
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
FPDIS
FCBEF
FCCF
FPVIOL
FACCERR
0
FBLANK
0
0
FCMD7
FCMD6
FCMD5
FCMD4
FCMD3
FCMD2
FCMD1
FCMD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
Table 4-4. Nonvolatile Register Summary
Address
0xFFB0 –
0xFFB7
0xFFB8 –
0xFFBC
0xFFBD
0xFFBE
0xFFBF
1
Register Name
Bit 7
6
5
NVBACKKEY
Reserved
NVPROT
NVICGTRM1
NVOPT
4
3
2
1
Bit 0
8-Byte Comparison Key
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
FPDIS
0
SEC01
SEC00
NVTRIM
KEYEN
FNORED
0
0
0
NVICGTRM is the factory trim value. This value must be copied to ICGTRM in user code.
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
47
Memory
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3
RAM
The MC9S08GT16A/GT8A includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08GT16A/GT8A, it is usually best to re-initialize the stack pointer to the top of the RAM so the
direct page RAM can be used for frequently accessed RAM variables and bit-addressable program
variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast
is equated to the highest address of the RAM in the Freescale-provided equate file).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.5, “Security,” for a detailed
description of the security feature.
4.4
FLASH
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire background debug interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMV1/D.
4.4.1
Features
Features of the FLASH memory include:
• FLASH Size
— MC9S08GT16A — 16384 bytes (32 pages of 512 bytes each)
— MC9S08GT8A — 8192 bytes (16 pages of 512 bytes each)
• Single power supply program and erase down to 1.8 V
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
MC9S08GT16A/GT8A Data Sheet, Rev. 1
48
Freescale Semiconductor
Memory
•
•
•
4.4.2
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (fFCLK) between 150 kHz and
200 kHz (see Table 4.6.1). This register can be written only once, so normally this write is done during
reset initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user
must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting
clock (1/fFCLK) is used by the command processor to time program and erase pulses. An integer number
of these timing pulses is used by the command processor to complete a program or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where tFCLK = 5 µs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5. Program and Erase Times
Parameter
1
4.4.3
Cycles of FCLK
Time if FCLK = 200 kHz
Byte program
9
45 µs
Byte program (burst)
4
20 µs1
Page erase
4000
20 ms
Mass erase
20,000
100 ms
Excluding start/end overhead
Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this
write is latched into the FLASH interface. This write is a required first step in any command
sequence. For erase and blank check commands, the value of the data is not important. For page
erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For
mass erase and blank check commands, the address can be any address in the FLASH memory.
Whole pages of 512 bytes are the smallest blocks of FLASH that may be erased.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
49
Memory
NOTE
Do not program any byte in the FLASH more than once after a successful
erase operation. Reprogramming bits in a byte which is already
programmed is not allowed without first erasing the page in which the byte
resides or mass erasing the entire FLASH memory. Programming without
first erasing may disturb data stored in the FLASH.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase
(0x41). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Aborting a command in this way sets the FACCERR access error flag which must be cleared before
starting a new command.
A strictly monitored procedure must be adhered to, or the command will not be accepted. This minimizes
the possibility of any unintended change to the FLASH memory contents. The command complete flag
(FCCF) indicates when a command is complete. The command sequence must be completed by clearing
FCBEF to launch the command. Figure 4-2 is a flowchart for executing all of the commands except for
burst programming. The FCDIV register must be initialized before using any FLASH commands. This
must be done only once following a reset.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
50
Freescale Semiconductor
Memory
WRITE TO FCDIV (Note 1)
Note 1: Required only once after reset.
START
FACCERR ?
0
1
CLEAR ERROR
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (Note 2)
FPVIOL OR
FACCERR ?
Note 2: Wait at least four bus cycles
before checking FCBEF or FCCF.
YES
ERROR EXIT
NO
0
FCCF ?
1
DONE
Figure 4-2. FLASH Program and Erase Flowchart
4.4.4
Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the FLASH
array does not need to be disabled between program operations. Ordinarily, when a program or erase
command is issued, an internal charge pump associated with the FLASH memory must be enabled to
supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When
a burst program command is issued, the charge pump is enabled and then remains enabled after completion
of the burst program operation if the following two conditions are met:
1. The next burst program command has been queued before the current program operation has
completed.
2. The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
51
Memory
program time provided that the conditions above are met. In the case the next sequential address is the
beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
Note 1: Required only once after reset.
WRITE TO FCDIV (Note 1)
START
FACCERR ?
1
0
CLEAR ERROR
FCBEF ?
1
0
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND ($25) TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (Note 2)
FPVIO OR
FACCERR ?
NO
YES
Note 2: Wait at least four bus cycles before
checking FCBEF or FCCF.
YES
ERROR EXIT
NEW BURST COMMAND ?
NO
0
FCCF ?
1
DONE
Figure 4-3. FLASH Burst Program Flowchart
MC9S08GT16A/GT8A Data Sheet, Rev. 1
52
Freescale Semiconductor
Memory
4.4.5
Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
• Writing to a FLASH address before the internal FLASH clock frequency has been set by writing
to the FCDIV register
• Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
• Writing a second time to a FLASH address before launching the previous command (There is only
one write to FLASH for every command.)
• Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
• Writing to any FLASH control register other than FCMD after writing to a FLASH address
• Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)
to FCMD
• Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear
FCBEF and launch the command) after writing the command to FCMD
• The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
• Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
• Writing 0 to FCBEF to cancel a partial command
4.4.6
FLASH Block Protection
The block protection feature prevents the protected region of FLASH from program or erase changes.
Block protection is controlled through the FLASH Protection Register (FPROT). When enabled, block
protection begins at any 512 byte boundary and continues through 0xFFFF. (see Section 4.6.4, “FLASH
Protection Register (FPROT and NVPROT)”).
After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the
nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application
software so a runaway program cannot alter the block protection settings. Since NVPROT is within the last
512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannot be
altered (intentionally or unintentionally) by the application software. FPROT can be written through
background debug commands which allows a way to erase and reprogram a protected FLASH memory.
The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last
address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits as
shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through
0xFFFF), the FPS bits must be set to 1101 111 which results in the value 0xDFFF as the last address of
unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
53
Memory
NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be
programmed into NVPROT to protect addresses 0xE000 through 0xFFFF.
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1
A15
A14
A13
A12
A11
A10
A9
1
1
1
1
1
1
1
1
1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Figure 4-4. Block Protection Mechanism
One use for block protection is to block protect an area of FLASH memory for a bootloader program. This
bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because
the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and
reprogram operation.
4.4.7
Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector
redirection allows users to modify interrupt vector information without unprotecting bootloader and reset
vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register
located at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the FLASH
memory must be block protected by programming the NVPROT register located at address 0xFFBD. All
of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, while the reset vector
(0xFFFE:FFFF) is not.
For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through
0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. Now,
if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vector
instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected
portion of the FLASH with new program code including new interrupt vector values while leaving the
protected area, which includes the default vector locations, unchanged.
4.5
Security
The MC9S08GT16A/GT8A includes circuitry to prevent unauthorized access to the contents of FLASH
and RAM memory. When security is engaged, FLASH and RAM are considered secure resources.
Direct-page registers, high-page registers, and the background debug controller are considered unsecured
resources. Programs executing within secure memory have normal access to any MCU memory locations
and resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in
the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH
into the working FOPT register in high-page register space. A user engages security by programming the
NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state
disengages security while the other three combinations engage security. Notice the erased state (1:1)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
54
Freescale Semiconductor
Memory
makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to
immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU
to remain unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all FLASH locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to
the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to
be compared against the key rather than as the first step in a FLASH program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be done in order, starting with the value for NVBACKKEY and ending with
NVBACKKEY+7. STHX should not be used for these writes because these writes cannot be done
on adjacent bus cycles. User software normally would get the key codes from outside the MCU
system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the
key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security
will be disengaged until the next reset.
The security key can be written only from RAM, so it cannot be entered through background commands
without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in FLASH memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other FLASH memory location. The nonvolatile registers are in the same 512-byte block of
FLASH as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by performing these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase FLASH, if necessary.
3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next
reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
55
Memory
4.6
Register Definition
The FLASH module has registers in the high-page register space, three locations in the nonvolatile register
space in FLASH memory that are copied into three corresponding high-page control registers at reset.
There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the
absolute address assignments for all FLASH registers. This section refers to registers and control bits only
by their names. A Freescale-provided equate or header file normally is used to translate these names into
the appropriate absolute addresses.
4.6.1
FLASH Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
7
R
6
5
4
3
2
1
0
PRDIV8
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
0
0
0
0
0
0
0
DIVLD
W
Reset
0
= Unimplemented or Reserved
Figure 4-5. FLASH Clock Divider Register (FCDIV)
Table 4-6. FCDIV Field Descriptions
Field
Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
5
DIV[5:0]
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 µs
to 6.7 µs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See Equation 4-1 and Equation 4-2. Table 4-7 shows the appropriate values for PRDIV8 and
DIV5:DIV0 for selected bus frequencies.
if PRDIV8 = 0 — fFCLK = fBus ÷ ([DIV5:DIV0] + 1)
Eqn. 4-1
if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × ([DIV5:DIV0] + 1))
Eqn. 4-2
MC9S08GT16A/GT8A Data Sheet, Rev. 1
56
Freescale Semiconductor
Memory
Table 4-7. FLASH Clock Divider Settings
4.6.2
fBus
PRDIV8
(Binary)
DIV5:DIV0
(Decimal)
fFCLK
Program/Erase Timing Pulse
(5 µs Min, 6.7 µs Max)
20 MHz
1
12
192.3 kHz
5.2 µs
10 MHz
0
49
200 kHz
5 µs
8 MHz
0
39
200 kHz
5 µs
4 MHz
0
19
200 kHz
5 µs
2 MHz
0
9
200 kHz
5 µs
1 MHz
0
4
200 kHz
5 µs
200 kHz
0
0
200 kHz
5 µs
150 kHz
0
0
150 kHz
6.7 µs
FLASH Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5
through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning
or effect. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory
as usual and then issue a new MCU reset.
R
7
6
5
4
3
2
1
0
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
W
Reset
This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-6. FLASH Options Register (FOPT)
Table 4-8. FOPT Field Descriptions
Field
Description
7
KEYEN
Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
57
Memory
Table 4-8. FOPT Field Descriptions (continued)
Field
Description
6
FNORED
Vector Redirection Disable — When this bit is 1, vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
1:0
SEC0[1:0]
Security State Code — This 2-bit field determines the security state of the MCU as shown below. When the
MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any
unsecured source including the background debug interface. For more detailed information about security, refer
to Section 4.5, “Security.”
00 Secure
01 Secure
10 Unsecured
11 Secure
SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of FLASH.
4.6.3
FLASH Configuration Register (FCNFG)
Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.
R
7
6
0
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
KEYACC
W
Reset
0
0
0
= Unimplemented or Reserved
Figure 4-7. FLASH Configuration Register (FCNFG)
Table 4-9. FCNFG Field Descriptions
Field
Description
5
KEYACC
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, “Security.”
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
Reads of the FLASH return invalid data.
4.6.4
FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. This
register may be read at any time, but user program writes have no meaning or effect. Background debug
commands can write to FPROT.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
58
Freescale Semiconductor
Memory
7
6
5
4
3
2
1
0
R
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
FPDIS
W
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Reset
This register is loaded from nonvolatile location NVPROT during reset.
Figure 4-8. FLASH Protection Register (FPROT)
1
Background commands can be used to change the contents of these bits in FPROT.
Table 4-10. FPROT Field Descriptions
Field
Description
7:1
FPS[7:1]
FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected
FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or
programmed.
0
FPDIS
4.6.5
FLASH Protection Disable
0 FLASH block specified by FPS2:FPS0 is block protected (program and erase not allowed).
1 No FLASH block is protected.
FLASH Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
7
6
R
5
4
FPVIOL
FACCERR
0
0
FCCF
FCBEF
3
2
1
0
0
FBLANK
0
0
0
0
0
0
W
Reset
1
1
= Unimplemented or Reserved
Figure 4-9. FLASH Status Register (FSTAT)
Table 4-11. FSTAT Field Descriptions
Field
Description
7
FCBEF
FLASH Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command may be written to the command buffer.
6
FCCF
FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no
command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
59
Memory
Table 4-11. FSTAT Field Descriptions (continued)
Field
Description
5
FPVIOL
Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that
attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is
cleared by writing a 1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
4
FACCERR
Access Error Flag — FACCERR is set automatically when the proper command sequence is not followed
exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV
register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed
discussion of the exact actions that are considered access errors, see Section 4.4.5, “Access Errors.” FACCERR
is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error has occurred.
1 An access error has occurred.
2
FBLANK
FLASH Verified as All Blank (Erased) Flag — FBLANK is set automatically at the conclusion of a blank check
command if the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a
new valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is
completely erased (all 0xFF).
4.6.6
FLASH Command Register (FCMD)
Only five command codes are recognized in normal user modes as shown in Table 4-13. Refer to
Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of FLASH
programming and erase operations.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
FCMD7
FCMD6
FCMD5
FCMD4
FCMD3
FCMD2
FCMD1
FCMD0
0
0
0
0
0
0
0
0
Reset
Figure 4-10. FLASH Command Register (FCMD)
Table 4-12. FCMD Field Descriptions
Field
7:0
FCMD[7:0]
Description
FLASH Command Bits -- See Table 4-13 for a description of FCMD[7:0].
MC9S08GT16A/GT8A Data Sheet, Rev. 1
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Memory
Table 4-13. FLASH Commands
Command
FCMD
Equate File Label
Blank check
0x05
mBlank
Byte program
0x20
mByteProg
Byte program — burst mode
0x25
mBurstProg
Page erase (512 bytes/page)
0x40
mPageErase
Mass erase (all FLASH)
0x41
mMassErase
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Blank check is required
only as part of the security unlocking mechanism.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
61
Memory
MC9S08GT16A/GT8A Data Sheet, Rev. 1
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Chapter 5
Resets, Interrupts, and System Configuration
5.1
Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08GT16A/GT8A. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this data manual. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own sections but are part of the system control logic.
5.1.1
Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation:
— Power-on detection (POR)
— Low voltage detection (LVD) with enable
— External RESET pin with enable
— COP watchdog with enable and two timeout choices
— Illegal opcode
— Illegal address
— Serial command from a background debug host
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)
5.2
MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08GT16A/GT8A has eight sources for reset:
• Power-on reset (POR)
• Low-voltage detect (LVD)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
63
Resets, Interrupts, and System Configuration
•
•
•
•
•
•
Computer operating properly (COP) watchdog timer
Illegal opcode detect
Illegal address detect
Background debug forced reset
The reset pin (RESET)
Clock generator loss of lock and loss of clock reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module
switches to self-clocked mode with the frequency of fSelf_reset selected. The reset pin is driven low for 34
internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin
is the cause of the MCU reset.
5.3
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it
times out, a system reset is generated to force the system back to a known starting point. The COP
watchdog is enabled by the COPE bit in SOPT (see Section 5.7.4, “System Options Register (SOPT)” for
additional information). The COP timer is reset by writing any value to the address of SRS. This write does
not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a
reset signal to the COP timer.
After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing
as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE
bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods
(218 or 213 cycles of the bus rate clock). Even if the application will use the reset default settings in COPE
and COPT, the user should still write to write-once SOPT during reset initialization to lock in the settings.
That way, they cannot be changed accidentally if the application program gets lost.
The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
When the MCU is in active background mode, the COP timer is temporarily disabled.
5.4
Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
64
Freescale Semiconductor
Resets, Interrupts, and System Configuration
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is set to 1 to enable the interrupt. The I bit
in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset,
which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and
performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction
and consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared
inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be
serviced without waiting for the first service routine to finish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the
stack.
NOTE
For compatibility with the M68HC08, the H register is not automatically
saved and restored. It is good programming practice to push H onto the stack
at the start of the interrupt service routine (ISR) and restore it just before the
RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced
first (see Table 5-1).
5.4.1
Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
65
Resets, Interrupts, and System Configuration
UNSTACKING
ORDER
TOWARD LOWER ADDRESSES
7
0
SP AFTER
INTERRUPT STACKING
5
1
CONDITION CODE REGISTER
4
2
ACCUMULATOR
3
3
INDEX REGISTER (LOW BYTE X)*
2
4
PROGRAM COUNTER HIGH
1
5
PROGRAM COUNTER LOW
STACKING
ORDER
SP BEFORE
THE INTERRUPT
TOWARD HIGHER ADDRESSES
* High byte (H) of index register is not automatically stacked.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address just recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
5.4.2
IRQ — External Interrupt Request Pin
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.4.2.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the
interrupt request (IRQ) input. When the pin is configured as an IRQ input, the user can choose the polarity
of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD),
and whether an event causes an interrupt or only sets the IRQF flag (which can be polled by software).
When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather than
a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is
configured to act as the IRQ input.
NOTE
The voltage measured on the pulled up IRQ pin may be as low as VDD –
0.7 V. The internal gates connected to this pin are pulled all the way to VDD.
All other pins with enabled pullup resistors will have an unloaded
measurement of VDD.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
66
Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.4.2.2
Edge and Level Sensitivity
The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.4.3
Interrupt Vectors, Sources, and Local Masks
Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU
registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
67
Resets, Interrupts, and System Configuration
Table 5-1. Vector Summary
Vector
Priority
Lower
Higher
Vector
Number
26
through
31
25
Address
(High/Low)
0xFFC0/FFC1
through
0xFFCA/FFCB
0xFFCC/FFCD
24
23
0xFFCE/FFCF
0xFFD0/FFD1
Viic
Vatd
System
control
IIC
ATD
22
21
0xFFD2/FFD3
0xFFD4/FFD5
Vkeyboard
Vsci2tx
KBI
SCI2
20
0xFFD6/FFD7
Vsci2rx
SCI2
19
0xFFD8/FFD9
Vsci2err
SCI2
18
0xFFDA/FFDB
Vsci1tx
SCI1
17
0xFFDC/FFDD
Vsci1rx
SCI1
16
0xFFDE/FFDF
Vsci1err
SCI1
15
0xFFE0/FFE1
Vspi
SPI
14
11
through
13
10
9
8
7
6
5
4
0xFFE2/FFE3
0xFFEC/FFED
through
0xFFE4/FFE5
0xFFEA/FFEB
0xFFEC/FFED
0xFFEE/FFEF
0xFFF0/FFF1
0xFFF2/FFF3
0xFFF4/FFF5
0xFFF6/FFF7
Vtpm2ovf
TPM2
Vtpm2ch1
Vtpm2ch0
Vtpm1ovf
Vtpm1ch2
Vtpm1ch1
Vtpm1ch0
Vicg
TPM2
TPM2
TPM1
TPM1
TPM1
TPM1
ICG
3
0xFFF8/FFF9
Vlvd
2
1
0xFFFA/FFFB
0xFFFC/FFFD
Virq
Vswi
System
control
IRQ
Core
0
0xFFFE/FFFF
Vreset
Vector Name
Module
Source
Enable
Description
Unused Vector Space
(available for user program)
Vrti
System
control
RTIF
RTIE
Real-time interrupt
IICIS
COCO
IICIE
AIEN
IIC control
AD conversion
complete
Keyboard pins
SCI2 transmit
KBF
KBIE
TDRE
TIE
TC
TCIE
IDLE
ILIE
RDRF
RIE
ORIE
OR
NFIE
NF
FEIE
FE
PFIE
PF
TDRE
TIE
TC
TCIE
IDLE
ILIE
RDRF
RIE
ORIE
OR
NFIE
NF
FEIE
FE
PFIE
PF
SPIF
SPIE
MODF
SPIE
SPTEF
SPTIE
TOF
TOIE
Unused Vector Space
(available for user program)
SCI2 receive
SCI2 error
SCI1 transmit
SCI1 receive
SCI1 error
SPI
TPM2 overflow
CH1F
CH0F
TOF
CH2F
CH1F
CH0F
ICGIF
(LOLS/LOCS)
LVDF
CH1IE
CH0IE
TOIE
CH2IE
CH1IE
CH0IE
LOLRE/LOCRE
TPM2 channel 1
TPM2 channel 0
TPM1 overflow
TPM1 channel 2
TPM1 channel 1
TPM1 channel 0
ICG
LVDIE
Low-voltage detect
IRQF
SWI
Instruction
COP
LVD
RESET pin
Illegal opcode
IRQIE
—
IRQ pin
Software interrupt
COPE
LVDRE
—
—
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
MC9S08GT16A/GT8A Data Sheet, Rev. 1
68
Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.5
Low-Voltage Detect (LVD) System
The MC9S08GT16A/GT8A includes a system to protect against low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system comprises a
power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH)
or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected
by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is
set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current
consumption in stop3 with the LVD enabled will be greater.
5.5.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the VLVDL level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.5.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.5.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.5.4
Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it.
There are two user selectable trip voltages for the LVW, one high (VLVWH) and one low (VLVWL). The trip
voltage is selected by LVWV in SPMSC2.
5.6
Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the
source clock's period. The RTI has two source clock choices, the external clock input (ICGERCLK) to the
ICG or the RTI's own internal clock. The RTI can be used in run, wait, stop2 and stop3 modes. It is not
available in stop1 mode.
In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only
the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
69
Resets, Interrupts, and System Configuration
When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and
configured for low bandwidth operation (RANGE = 0).
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable,
RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to
RTIS2:RTIS1:RTIS0 in which case the clock source input is disabled and no interrupts will be generated.
See Section 5.7.6, “System Real-Time Interrupt Status and Control Register (SRTISC),” for detailed
information about this register.
5.7
Register Definition
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 4, “Memory” of this data sheet for the absolute
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
MC9S08GT16A/GT8A Data Sheet, Rev. 1
70
Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.7.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes two unimplemented bits which always read 0, four read/write bits, one
read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status,
and acknowledge IRQ events.
R
7
6
0
0
5
4
IRQEDG
IRQPE
3
2
IRQF
0
W
Reset
1
0
IRQIE
IRQMOD
0
0
IRQACK
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-2. IRQSC Field Descriptions
Field
Description
5
IRQEDG
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can
be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3
IRQF
2
IRQACK
1
IRQIE
0
IRQMOD
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware
interrupt request.
0 Hardware interrupt requests from IRQF disabled (use polling).
1 Hardware interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.4.2.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
71
Resets, Interrupts, and System Configuration
5.7.2
System Reset Status Register (SRS)
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
R
7
6
5
4
3
2
1
0
POR
PIN
COP
ILOP
ILAD
ICG
LVD
0
W
Writing any value to SIMRS address clears COP watchdog timer.
Power-on
reset:
1
0
0
0
0
0
1
0
Low-voltage
reset:
U
0
0
0
0
0
1
0
Any other
reset:
0
Note (1)
Note (1)
Note (1)
0
Note (1)
0
0
U = Unaffected by reset
1
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to
sources that are not active at the time of reset will be cleared.
Figure 5-3. System Reset Status (SRS)
Table 5-3. SRS Field Descriptions
Field
Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
72
Freescale Semiconductor
Resets, Interrupts, and System Configuration
Table 5-3. SRS Field Descriptions (continued)
Field
3
ILAD
Description
Illegal Address — Reset was caused by an attempt to access a designated illegal address.
0 Reset not caused by an illegal address access.
1 Reset caused by an illegal address access.
Illegal address areas in the MC9S08GT16A are:
• 0x0880 - 0x17FF — Gap from end of RAM to start of high page registers
• 0x182C - 0xBFFF — Gap from end of high page registers to start of Flash memory
Unused and reserved locations in register areas are not considered designated illegaladdresses and do not
triggerillegal address resets.
2
ICG
Internal Clock Generation Module Reset — Reset was caused by an ICG module reset.
0 Reset not caused by ICG module.
1 Reset caused by ICG module.
1
LVD
Low Voltage Detect — If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip
voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop. To maintain LVD operation
in stop, the LVDSE bit must be set.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.7.3
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset
BDFR
Note (1)
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1
BDFR is writable only through serial background debug commands, not from user programs.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-4. SBDFR Field Descriptions
Field
Description
0
BDFR
Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be
written from a user program.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
73
Resets, Interrupts, and System Configuration
5.7.4
System Options Register (SOPT)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
should be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
7
6
5
COPE
COPT
STOPE
1
1
0
4
R
3
2
0
0
1
0
BKGDPE
W
Reset
1
0
0
1
1
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT)
Table 5-5. SOPT Field Descriptions
Field
Description
7
COPE
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected (213 cycles of BUSCLK).
1 Long timeout period selected (218 cycles of BUSCLK).
5
STOPE
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE
Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as
BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This
pin always defaults to BKGD/MS function after any reset.
0 BKGD pin disabled.
1 BKGD pin enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
74
Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.7.5
System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
7
6
5
4
R
3
2
1
0
ID11
ID10
ID9
ID8
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. System Device Identification Register High (SDIDH)
Table 5-6. SDIDH Field Descriptions
Field
3:0
ID[11:8]
R
Description
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits in Table 5-7.
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
0
0
0
1
1
0
1
W
Reset
= Unimplemented or Reserved
Figure 5-7. System Device Identification Register Low (SDIDL)
Table 5-7. SDIDL Field Descriptions
Field
7:0
ID[7:0]
Description
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits in Table 5-6.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
75
Resets, Interrupts, and System Configuration
5.7.6
System Real-Time Interrupt Status and Control Register (SRTISC)
This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay
selects, and three unimplemented bits, which always read 0.
R
7
6
RTIF
0
W
5
4
RTICLKS
RTIE
0
0
3
2
1
0
RTIS2
RTIS1
RTIS0
0
0
0
0
RTIACK
Reset
0
0
0
= Unimplemented or Reserved
Figure 5-8. System RTI Status and Control Register (SRTISC)
Table 5-8. SRTISC Field Descriptions
Field
Description
7
RTIF
Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out.
0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
6
RTIACK
Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.
5
RTICLKS
Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal oscillator.
1 Real-time interrupt request clock source is external clock.
4
RTIE
Real-Time Interrupt Enable — This read-write bit enables real-time interrupts.
0 Real-time interrupts disabled.
1 Real-time interrupts enabled.
2:0
RTIS[2:0]
Real-Time Interrupt Period Selects — These read/write bits select the wakeup period for the RTI. One clock
source for the real-time interrupt is its own internal clock source, which oscillates with a period of approximately
tRTI and is independent of other MCU clock sources. Using an external clock source the delays will be crystal
frequency divided by value in RTIS2:RTIS1:RTIS0. See Table 5-9.
Table 5-9. Real-Time Interrupt Period
1
2
RTIS2:RTIS1:RTIS0
Internal Clock Source 1
(tRTI = 1.15 ms, Nominal)
External Clock Source 2
Period = text
0:0:0
9.2 ms
Disable periodic wakeup timer
0:0:1
18.4 ms
text x 256
0:1:0
36.8 ms
tex x 1024
0:1:1
73.6 ms
tex x 2048
1:0:0
147.2 ms
tex x 4096
1:0:1
294.4 ms
text x 8192
1:1:0
588.8 ms
text x 16384
1:1:1
1177.6 ms
tex x 32768
See Table A-12 tRTI in Appendix A, “Electrical Characteristics,” for the tolerance on these values.
text is based on the external clock source, resonator, or crystal selected by the ICG configuration. See Table A-11 for details.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
76
Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.7.7
R
System Power Management Status and Control 1 Register (SPMSC1)
7
6
LVDF
0
W
Reset
5
4
3
2
1
0
LVDRE
Note (1)
LVDSE
Note (1)
LVDE
Note (1)
0
0
LVDIE
0
1
1
1
0
0
LVDACK
0
0
= Unimplemented or Reserved
1
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-10. SPMSC1 Field Descriptions
Field
Description
7
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
77
Resets, Interrupts, and System Configuration
5.7.8
System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
R
7
6
LVWF
0
W
5
4
LVDV
LVWV
2
PPDF
0
LVWACK
1
0
PDC
PPDC
PPDACK
Power-on
reset:
0
Note (1)
0
0
0
0
0
0
0
LVD reset:
0
Note (1)
0
U
U
0
0
0
0
Any other
reset:
0
Note (1)
0
U
U
0
0
0
0
= Unimplemented or Reserved
1
3
U = Unaffected by reset
LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-11. SPMSC2 Field Descriptions
Field
7
LVWF
6
LVWACK
Description
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1
to LVWACK clears LVWF to 0 if a low voltage warning is not present.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (VLVD).
0 Low trip point selected (VLVD = VLVDL).
1 High trip point selected (VLVD = VLVDH).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (VLVW).
0 Low trip point selected (VLVW = VLVWL).
1 High trip point selected (VLVW = VLVWH).
3
PPDF
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
1
PDC
Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
0
PPDC
Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is
selected.
0 Stop1, full power down, mode enabled if PDC set.
1 Stop2, partial power down, mode enabled if PDC set.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
78
Freescale Semiconductor
Chapter 6
Parallel Input/Output
6.1
Introduction
This section explains software controls related to parallel input/output (I/O). The MC9S08GT16A/GT8A
has six I/O ports which include a total of up to 39 general-purpose I/O pins (one pin, PTG0, is output only).
See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these
pins.
Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or
keyboard interrupts. When these other modules are not controlling the port pins, they revert to
general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output
(write) data, a data direction bit controls the direction of the pin, and a pullup enable bit enables an internal
pullup device (provided the pin is configured as an input), and a slew rate control bit controls the rise and
fall times of the pins.
Pins that are not used in the application must be terminated. This prevents excess current caused by floating
inputs and enhances immunity during noise or transient events. Termination methods include:
• Configuring unused pins as outputs driving high or low
• Configuring unused pins as inputs and using internal or external pullups
Never connect unused pins to VDD or VSS.
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unconnected pins to outputs so the pins
do not float.
6.1.1
Features
Parallel I/O features, depending on package choice, include:
• A total of 39 general-purpose I/O pins in six ports (PTG0 is output only)
• High-current drivers on port C pins
• Hysteresis input buffers
• Software-controlled pullups on each input pin
• Software-controlled slew rate output buffers
• Eight port A pins shared with KBI
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
79
Parallel Input/Output
•
•
•
•
•
Eight port B pins shared with ATD
Eight high-current port C pins shared with SCI2 and IIC
Five port D pins shared with TPM1 and TPM2
Six port E pins shared with SCI1 and SPI
Four port G pins shared with EXTAL, XTAL, and BKGD/MS
MC9S08GT16A/GT8A Data Sheet, Rev. 1
80
Freescale Semiconductor
Parallel Input/Output
Block Diagram
VREFL
VREFH
VSSAD
VDDAD
6.1.2
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 6-1. Block Diagram Highlighting Parallel Input/Output Pins
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
81
Parallel Input/Output
6.2
External Signal Description
The MC9S08GT16A/GT8A has a total of 39 parallel I/O pins (one is output only) in six 8-bit ports
(PTA–PTE, PTG). Not all pins are bonded out in all packages. Consult the pin assignment in Chapter 2,
“Pins and Connections,” for available parallel I/O pins. All of these pins are available for general-purpose
I/O when they are not used by other on-chip peripheral systems.
After reset, BKGD/MS is enabled and therefore is not usable as an output pin until BKGDPE in SOPT is
cleared. The rest of the peripheral functions are disabled. After reset, all data direction and pullup enable
controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices
disabled.
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.2.1
Port A and Keyboard Interrupts
Port A
MCU Pin:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7/
KBIP7
PTA6/
KBIP6
PTA5/
KBIP5
PTA4/
KBIP4
PTA3/
KBIP3
PTA2/
KBIP2
PTA1/
KBIP1
PTA0/
KBIP0
Figure 6-2. Port A Pin Names
Port A is an 8-bit port shared among the KBI keyboard interrupt inputs and general-purpose I/O. Any pins
enabled as KBI inputs will be forced to act as inputs.
Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction
(PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
Port A can be configured to be keyboard interrupt input pins. Refer to Chapter 7, “Keyboard Interrupt
(S08KBIV1),” for more information about using port A pins as keyboard interrupts pins.
6.2.2
Port B and Analog to Digital Converter Inputs
j
Port B
MCU Pin:
Bit 7
6
5
4
3
2
1
Bit 0
PTB7/
ADP7
PTB6/
ADP6
PTB5/
ADP5
PTB4/
ADP4
PTB3/
ADP3
PTB2/
ADP2
PTB1/
ADP1
PTB0/
ADP0
Figure 6-3. Port B Pin Names
Port B is an 8-bit port shared among the ATD inputs and general-purpose I/O. Any pin enabled as an ATD
input will be forced to act as an input.
Port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD), data direction
(PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
When the ATD module is enabled, analog pin enables are used to specify which pins on port B will be used
as ATD inputs. Refer to Chapter 14, “Analog-to-Digital Converter (S08ATDV3),” for more information
about using port B pins as ATD pins.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
82
Freescale Semiconductor
Parallel Input/Output
6.2.3
Port C and SCI2, IIC, and High-Current Drivers
Port C
MCU Pin:
Bit 7
6
5
3
3
2
1
Bit 0
PTC7
PTC6
PTC5
PTC4
PTC3/
SCL
PTC2/
SDA
PTC1/
RxD2
PTC0/
TxD2
Figure 6-4. Port C Pin Names
Port C is an 8-bit port which is shared among the SCI2 and IIC modules, and general-purpose I/O. When
SCI2 or IIC modules are enabled, the pin direction will be controlled by the module or function. Port C
has high current output drivers.
Port C pins are available as general-purpose I/O pins controlled by the port C data (PTCD), data direction
(PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
When the SCI2 module is enabled, PTC0 serves as the SCI2 module’s transmit pin (TxD2) and PTC1
serves as the receive pin (RxD2). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1),”
for more information about using PTC0 and PTC1 as SCI pins
When the IIC module is enabled, PTC2 serves as the IIC modules’s serial data input/output pin (SDA) and
PTC3 serves as the clock pin (SCL). Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV1),” for more
information about using PTC2 and PTC3 as IIC pins.
6.2.4
Port D, TPM1 and TPM2
Port D
MCU Pin:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
PTD4/
TPM2CH1
PTD3/
TPM2CLK/
TPM2CH0
PTD2/
TPM1CH2
PTD1/
TPM1CH1
PTD0/
TPM1CLK/
TPM1CH0
Figure 6-5. Port D Pin Names
Port D is an 5-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O.
When the TPM1 or TPM2 modules are enabled in output compare or input capture modes of operation,
the pin direction will be controlled by the module function.
Port D pins are available as general-purpose I/O pins controlled by the port D data (PTDD), data direction
(PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
The TPM2 module can be configured to use PTD4–PTD3 as either input capture, output compare, PWM,
or external clock input pins (PTD3 only). Refer to Chapter 10, “Timer/PWM (S08TPMV2),” for more
information about using PTD4–PTD3 as timer pins.
The TPM1 module can be configured to use PTD2–PTD0 as either input capture, output compare, PWM,
or external clock input pins (PTD0 only). Refer to Chapter 10, “Timer/PWM (S08TPMV2),” for more
information about using PTD2–PTD0 as timer pins.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
83
Parallel Input/Output
6.2.5
Port E, SCI1, and SPI
Port E
MCU Pin:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
PTE5/
SPSCK
PTE4/
MOSI
PTE3/
MISO
PTE2/
SS
PTE1/
RxD1
PTE0/
TxD1
Figure 6-6. Port E Pin Names
Port E is an 6-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI
or SPI modules are enabled, the pin direction will be controlled by the module function.
Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction
(PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to Section 6.3, “Parallel
I/O Controls” for more information about general-purpose I/O control.
When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1
serves as the receive pin (RxD1). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1)” for
more information about using PTE0 and PTE1 as SCI pins.
When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as
the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5
serves as the SPI clock pin (SPSCK1). Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3) for
more information about using PTE5–PTE2 as SPI pins.
6.2.6
Port G, BKGD/MS, and Oscillator
Port G
MCU Pin:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
PTG3
PTG2/
EXTAL
PTG1/
XTAL
PTG0/
BKGD/MS
Figure 6-7. Port G Pin Names
Port G is an 4-bit port which is shared among the background/mode select function, oscillator, and
general-purpose I/O. When the background/mode select function or oscillator is enabled, the pin direction
will be controlled by the module function.
Port G pins are available as general-purpose I/O pins controlled by the port G data (PTGD), data direction
(PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
The internal pullup for PTG0 is enabled when the background/mode select function is enabled, regardless
of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU
exits reset, the BKGD/MS pin becomes the background communications input/output pin. The PTG0 can
be configured to be a general-purpose output pin. Refer to Section 5.7.4, “System Options Register
(SOPT),” for selecting BKGD or PTG0. Refer to Chapter 3, “Modes of Operation,”, Chapter 5, “Resets,
Interrupts, and System Configuration,” and Chapter 15, “Development Support,” for more information
about using this pin.
The ICG module can be configured to use PTG2–PTG1 ports as crystal oscillator or external clock pins.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
84
Freescale Semiconductor
Parallel Input/Output
Refer to Chapter 9, “Internal Clock Generator (S08ICGV4),” for more information about using these pins
as oscillator pins.
6.3
Parallel I/O Controls
Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that
are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), a pullup enable
register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, or G.
Reads of the data register return the pin value (if PTxDDn = 0) or the contents of the port data register (if
PTxDDn = 1). Writes to the port data register are latched into the port register whether the pin is controlled
by an on-chip peripheral or the pin is configured as an input. If the corresponding pin is not controlled by
a peripheral and is configured as an output, this level will be driven out the port pin.
6.3.1
Data Direction Control
The data direction control bits determine whether the pin output driver is enabled, and they control what
is read for port data register reads. Each port pin has a data direction control bit. When PTxDDn = 0, the
corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the
corresponding pin is an output and reads of PTxD return the last value written to the port data register.
When a peripheral module or system function is in control of a port pin, the data direction control still
controls what is returned for reads of the port data register, even though the peripheral system has
overriding control of the actual pin direction.
For the MC9S08GT16A/GT8A MCU, reads of PTG0/BKGD/MS will return the value on the output pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.3.2
Internal Pullup Control
An internal pullup device can be enabled for each port pin that is configured as an input (PTxDDn = 0).
The pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an
input function as long as the PTxDDn = 0.
For the four configurable KBI module inputs on PTA7–PTA4, when a pin is configured to detect rising
edges, the port pullup enable associated with the pin (PTAPEn) selects a pulldown rather than a pullup
device.
6.3.3
Slew Rate Control
Slew rate control can be enabled for each port pin that is configured as an output (PTxDDn = 1) or if a
peripheral module is enabled and its function is an output. Not all peripheral modules’ outputs have slew
rate control; refer to Chapter 2, “Pins and Connections,” for more information about which pins have slew
rate control.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
85
Parallel Input/Output
6.4
Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
• When the MCU enters stop1 mode, all internal registers including general-purpose I/O control and
data registers are powered down. All of the general-purpose I/O pins assume their reset state:
output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the
MCU had been reset.
• When the MCU enters stop2 mode, the internal registers are powered down as in stop1 but the I/O
pin states are latched and held. For example, a port pin that is an output driving low continues to
function as an output driving low even though its associated data direction and output data registers
are powered down internally. Upon exit from stop2, the pins continue to hold their states until a 1
is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from stop2, the
user must restore the port control and data registers to the values they held before entering stop2.
These values can be stored in RAM before entering stop2 because the RAM is maintained during
stop2.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
6.5
Register Definition
This section provides information about all registers and control bits associated with the parallel I/O ports.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O registers.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
6.5.1
Port A Registers (PTAD, PTAPE, PTASE, and PTADD)
Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as
general-purpose I/O pins are controlled by the port A data (PTAD), data direction (PTADD), pullup enable
(PTAPE), and slew rate control (PTASE) registers.
If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as
an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of
PTAD will return the logic value of the corresponding pin, provided PTADD is 0.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
86
Freescale Semiconductor
Parallel Input/Output
7
6
5
4
3
2
1
0
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-8. Port A Data Register (PTAD)
Table 6-1. PTAD Field Descriptions
Field
Description
7:0
PTAD[7:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
6
5
4
3
2
1
0
PTAPE7
PTAPE6
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-9. Pullup Enable for Port A (PTAPE)
Table 6-2. PTAPE Field Descriptions
Field
Description
7:0
Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether
PTAPE[7:0] internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are configured
as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of
port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits
enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
87
Parallel Input/Output
7
6
5
4
3
2
1
0
PTASE7
PTASE6
PTASE5
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-10. Slew Rate Control Enable for Port A (PTASE)
Table 6-3. PTASE Field Descriptions
Field
Description
7:0
Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits
PTASE[7:0] determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
7
6
5
4
3
2
1
0
PTADD7
PTADD6
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
PTADD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-11. Data Direction for Port A (PTADD)
Table 6-4. PTADD Field Descriptions
Field
Description
7:0
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTADD[7:0] PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
88
Freescale Semiconductor
Parallel Input/Output
6.5.2
Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)
Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as
general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable
(PTBPE), and slew rate control (PTBSE) registers.
If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored.
When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin,
provided PTBDD is 0.
7
6
5
4
3
2
1
0
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-12. Port B Data Register (PTBD)
Table 6-5. PTBD Field Descriptions
Field
Description
7:0
PTBD[7:0]
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7
6
5
4
3
2
1
0
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-13. Pullup Enable for Port B (PTBPE)
Table 6-6. PTBPE Field Descriptions
Field
Description
7:0
Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether
PTBPE[7:0] internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
89
Parallel Input/Output
7
6
5
4
3
2
1
0
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-14. Data Direction for Port A (PTBSE)
Table 6-7. PTBSE Field Descriptions
Field
Description
7:0
Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits
PTBSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
7
6
5
4
3
2
1
0
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-15. Data Direction for Port B (PTBDD)
Table 6-8. PTBDD Field Descriptions
Field
Description
7:0
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBDD[7:0] PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
90
Freescale Semiconductor
Parallel Input/Output
6.5.3
Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD)
Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used
as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup
enable (PTCPE), and slew rate control (PTCSE) registers.
If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding
PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2.
If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the IIC serial data pin (SDA), when in output mode and the IIC clock pin (SCL).
PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC
serial data pin, when in receive mode.
Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0.
7
6
5
4
3
2
1
0
PTCD7
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-16. Port C Data Register (PTCD)
Table 6-9. PTCD Field Descriptions
Field
Description
7:0
PTCD[7:0]
Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
91
Parallel Input/Output
7
6
5
4
3
2
1
0
PTCPE7
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-17. Pullup Enable for Port C (PTCPE)
Table 6-10. PTCPE Field Descriptions
Field
Description
7:0
Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether
PTCPE[7:0] internal pullup devices are enabled. For port C pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
7
6
5
4
3
2
1
0
PTCSE7
PTCSE6
PTCSE5
PTCSE4
PTCSE3
PTCSE2
PTCSE1
PTCSE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-18. Slew Rate Control Enable for Port C (PTCSE)
Table 6-11. PTCSE Field Descriptions
Field
Description
7:0
Slew Rate Control Enable for Port C Bits — For port C pins that are outputs, these read/write control bits
PTCSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
7
6
5
4
3
2
1
0
PTCDD7
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
PTCDD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 6-19. Data Direction for Port C (PTCDD)
Table 6-12. PTCDD Field Descriptions
Field
Description
7:0
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCDD[7:0] PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
92
Freescale Semiconductor
Parallel Input/Output
6.5.4
Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)
Port D includes five pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as
general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable
(PTDPE), and slew rate control (PTDSE) registers.
If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in
output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the
TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding
PTDDD bit is 0, to provide a pullup device on the pin.
Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0.
R
7
6
5
0
0
0
4
3
2
1
0
PTDD4
PTDD3
PTDD2
PTDD1
PTDD0
0
0
0
0
0
W
Reset
0
0
0
Figure 6-20. Port D Data Register (PTDD)
Table 6-13. PTDD Field Descriptions
Field
Description
4:0
PTDD[4:0]
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
R
7
6
5
0
0
0
4
3
2
1
0
PTDPE4
PTDPE3
PTDPE2
PTDPE1
PTDPE0
0
0
0
0
0
W
Reset
0
0
0
Figure 6-21. Pullup Enable for Port D (PTDPE)
Table 6-14. PTDPE Field Descriptions
Field
Description
4:0
Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether
PTDPE[4:0] internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
93
Parallel Input/Output
R
7
6
5
0
0
0
4
3
2
1
0
PTDSE4
PTDSE3
PTDSE2
PTDSE1
PTDSE0
0
0
0
0
0
W
Reset
0
0
0
Figure 6-22. Slew Rate Control Enable for Port D (PTDSE)
Table 6-15. PTDSE Field Descriptions
Field
Description
4:0
Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits
PTDSE[4:0] determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
R
7
6
5
0
0
0
4
3
2
1
0
PTDDD4
PTDDD3
PTDDD2
PTDDD1
PTDDD0
0
0
0
0
0
W
Reset
0
0
0
Figure 6-23. Data Direction for Port D (PTDDD)
Table 6-16. PTDDD Field Descriptions
Field
Description
4:0
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDDD[4:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
94
Freescale Semiconductor
Parallel Input/Output
6.5.5
Port E Registers (PTED, PTEPE, PTESE, and PTEDD)
Port E includes six general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used
as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup
enable (PTEPE), and slew rate control (PTESE) registers.
If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding
PTEDD bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1.
If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SPI serial output pin (MOSI or MISO) and serial clock pin (SPSCK) depending
on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide
a pullup device on the SPI serial input pins (MOSI or MISO) and slave select pin (SS) depending on the
SPI operational mode.
Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0.
R
7
6
0
0
5
4
3
2
1
0
PTED5
PTED4
PTED3
PTED2
PTED1
PTED0
0
0
0
0
0
0
W
Reset
0
0
Figure 6-24. Port E Data Register (PTED)
Table 6-17. PTED Field Descriptions
Field
Description
5:0
PTED[5:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
95
Parallel Input/Output
R
7
6
0
0
5
4
3
2
1
0
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
0
0
0
0
0
0
W
Reset
0
0
Figure 6-25. Pullup Enable for Port E (PTEPE)
Table 6-18. PTEPE Field Descriptions
Field
Description
5:0
Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether
PTEPE[5:0] internal pullup devices are enabled. For port E pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
R
7
6
0
0
5
4
3
2
1
0
PTESE5
PTESE4
PTESE3
PTESE2
PTESE1
PTESE0
0
0
0
0
0
0
W
Reset
0
0
Figure 6-26. Slew Rate Control Enable for Port E (PTESE)
Table 6-19. PTESE Field Descriptions
Field
Description
5:0
Slew Rate Control Enable for Port E Bits — For port E pins that are outputs, these read/write control bits
PTESE[5:0]
determine whether the slew rate controlled outputs are enabled. For port E pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
R
7
6
0
0
5
4
3
2
1
0
PTEDD5
PTEDD4
PTEDD3
PTEDD2
PTEDD1
PTEDD0
0
0
0
0
0
0
W
Reset
0
0
Figure 6-27. Data Direction for Port E (PTEDD)
Table 6-20. PTEDD Field Descriptions
Field
Description
5:0
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTEDD[5:0]
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
96
Freescale Semiconductor
Parallel Input/Output
6.5.6
Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD)
Port G includes four general-purpose I/O pins that are shared with BKGD/MS function and the oscillator
or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data
(PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers.
Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is exits reset, PTG0 can be
configured to be a general-purpose output pin. When BKGD/MS takes control of PTG0, the corresponding
PTGDD, PTGPE, and PTGPSE bits are ignored.
Port pins PTG1 and PTG2 can be configured to be oscillator or external clock pins. When the oscillator
takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored.
Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0.
R
7
6
5
4
0
0
0
0
3
2
1
0
PTGD3
PTGD2
PTGD1
PTGD0
0
0
0
0
W
Reset
0
0
0
0
Figure 6-28. Port PTG Data Register (PTGD)
Table 6-21. PTGD Field Descriptions
Field
Description
3:0
PTGD[3:0]
Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port
G pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
R
7
6
5
4
0
0
0
0
3
2
1
0
PTGPE3
PTGPE2
PTGPE1
PTGPE0
0
0
0
0
W
Reset
0
0
0
0
Figure 6-29. Pullup Enable for Port G (PTGPE)
Table 6-22. PTGPE Field Descriptions
Field
Description
3:0
Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether
PTGPE[3:0] internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
97
Parallel Input/Output
R
7
6
5
4
0
0
0
0
3
2
1
0
PTGSE3
PTGSE2
PTGSE1
PTGSE0
0
0
0
0
W
Reset
0
0
0
0
Figure 6-30. Slew Rate Control Enable for Port G (PTGSE)
Table 6-23. PTGSE Field Descriptions
Field
Description
3:0
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
PTGSE[3:0] determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
R
7
6
5
4
0
0
0
0
3
2
1
0
PTGDD3
PTGDD2
PTGDD1
PTGDD0
Note (1)
0
0
0
0
W
Reset
0
0
0
0
Figure 6-31. Data Direction for Port G (PTGDD)
1
Although PTGDD0 is implemented, this bit actually has no effect on the operation of PTG0/BKGD.
Table 6-24. PTGDD Field Descriptions
Field
Description
3:0
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[3:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
98
Freescale Semiconductor
Chapter 7
Keyboard Interrupt (S08KBIV1)
7.1
Introduction
The MC9S08GT16A/GT8A has one KBI module with eight keyboard interrupt inputs that share port A
pins. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects
of these pins.
7.1.1
Port A and Keyboard Interrupt Pins
MCU Pin:
PTA7/
KBIP7
PTA6/
KBIP6
PTA5/
KBIP5
PTA4/
KBIP4
PTA3/
KBIP3
PTA2/
KBIP2
PTA1/
KBIP1
PTA0/
KBIP0
Figure 7-1. Port A Pin Names
The following paragraphs discuss controlling the keyboard interrupt pins.
Port A is an 8-bit port which is shared among the KBI keyboard interrupt inputs and general-purpose I/O.
The eight KBIPEn control bits in the KBIPE register allow selection of any combination of port A pins to
be assigned as KBI inputs. Any pins which are enabled as KBI inputs will be forced to act as inputs and
the remaining port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD),
data direction (PTADD), and pullup enable (PTAPE) registers.
KBI inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. Bits 3 through 0 of
port A are falling-edge/low-level sensitive while bits 7 through 4 can be configured for
rising-edge/high-level or for falling-edge/low-level sensitivity.
The eight PTAPEn control bits in the PTAPE register allow you to select whether an internal pullup device
is enabled on each port A pin that is configured as an input. When any of bits 7 through 4 of port A are
enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable
pulldown rather than pullup devices.
An enabled keyboard interrupt can be used to wake the MCU from wait or standby (stop3).
7.1.2
Features
The keyboard interrupt (KBI) module features include:
• Keyboard interrupts selectable on eight port pins:
— Four falling-edge/low-level sensitive
— Four falling-edge/low-level or rising-edge/high-level sensitive
— Choice of edge-only or edge-and-level sensitivity
— Common interrupt flag and interrupt enable control
— Capable of waking up the MCU from stop3 or wait mode
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
99
VREFL
VREFH
VSSAD
VDDAD
Keyboard Interrupt (S08KBIV1)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 7-2. Block Diagram Highlighting the KBI Module
MC9S08GT16A/GT8A Data Sheet, Rev. 1
100
Freescale Semiconductor
Keyboard Interrupt (S08KBIV1)
7.1.3
KBI Block Diagram
Figure 7-3 shows the block diagram for a KBI module.
KBIP0
KBIPE0
VDD
KBIPE3
0
SYNCHRONIZER
S
KBIPE4
KEYBOARD
INTERRUPT FF
STOP
STOP BYPASS
KEYBOARD
INTERRUPT
REQUEST
KBIMOD
1
0
KBF
CK
KBEDG4
KBIPn
RESET
D CLR Q
1
KBIP4
BUSCLK
KBACK
KBIP3
KBIE
S
KBIPEn
KBEDGn
Figure 7-3. KBI Block Diagram
7.2
Register Definition
This section provides information about all registers and control bits associated with the KBI module.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all KBI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
101
Keyboard Interrupt (S08KBIV1)
7.2.1
KBI Status and Control Register (KBISC)
7
6
5
4
KBEDG7
KBEDG6
KBEDG5
KBEDG4
R
3
2
KBF
0
W
Reset
1
0
KBIE
KBIMOD
0
0
KBACK
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-4. KBI Status and Control Register (KBISC)
Table 7-1. KBISC Register Field Descriptions
Field
Description
7:4
Keyboard Edge Select for KBI Port Bits — Each of these read/write bits selects the polarity of the edges and/or
KBEDG[7:4] levels that are recognized as trigger events on the corresponding KBI port pin when it is configured as a keyboard
interrupt input (KBIPEn = 1). Also see the KBIMOD control bit, which determines whether the pin is sensitive to
edges-only or edges and levels.
0 Falling edges/low levels
1 Rising edges/high levels
3
KBF
Keyboard Interrupt Flag — This read-only status flag is set whenever the selected edge event has been
detected on any of the enabled KBI port pins. This flag is cleared by writing a 1 to the KBACK control bit. The
flag will remain set if KBIMOD = 1 to select edge-and-level operation and any enabled KBI port pin remains at
the asserted level.
KBF can be used as a software pollable flag (KBIE = 0) or it can generate a hardware interrupt request to the
CPU (KBIE = 1).
0 No KBI interrupt pending
1 KBI interrupt pending
2
KBACK
Keyboard Interrupt Acknowledge — This write-only bit (reads always return 0) is used to clear the KBF status
flag by writing a 1 to KBACK. When KBIMOD = 1 to select edge-and-level operation and any enabled KBI port
pin remains at the asserted level, KBF is being continuously set so writing 1 to KBACK does not clear the KBF
flag.
1
KBIE
Keyboard Interrupt Enable — This read/write control bit determines whether hardware interrupts are generated
when the KBF status flag equals 1. When KBIE = 0, no hardware interrupts are generated, but KBF can still be
used for software polling.
0 KBF does not generate hardware interrupts (use polling)
1 KBI hardware interrupt requested when KBF = 1
KBIMOD
Keyboard Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels. KBI port bits 7
through 4 can be configured to detect either:
• Rising edges-only or rising edges and high levels (KBEDGn = 1)
• Falling edges-only or falling edges and low levels (KBEDGn = 0)
0 Edge-only detection
1 Edge-and-level detection
MC9S08GT16A/GT8A Data Sheet, Rev. 1
102
Freescale Semiconductor
Keyboard Interrupt (S08KBIV1)
7.2.2
KBI Pin Enable Register (KBIPE)
7
6
5
4
3
2
1
0
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
0
0
0
0
0
0
0
0
R
W
Reset
= Unimplemented or Reserved
Figure 7-5. KBI Pin Enable Register (KBIPE)
Table 7-2. KBIPE Register Field Descriptions
Field
Description
7:0
KBIPE[7:0]
7.3
7.3.1
Keyboard Pin Enable for KBI Port Bits — Each of these read/write bits selects whether the associated KBI
port pin is enabled as a keyboard interrupt input or functions as a general-purpose I/O pin.
0 Bit n of KBI port is a general-purpose I/O pin not associated with the KBI
1 Bit n of KBI port enabled as a keyboard interrupt input
Functional Description
Pin Enables
The KBIPEn control bits in the KBIPE register allow a user to enable (KBIPEn = 1) any combination of
KBI-related port pins to be connected to the KBI module. Pins corresponding to 0s in KBIPE are
general-purpose I/O pins that are not associated with the KBI module.
7.3.2
Edge and Level Sensitivity
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI
module must be at the deasserted logic level.
A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level)
during one bus cycle and then a logic 0 (the asserted level) during the next cycle.
A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1
during the next cycle.
The KBIMOD control bit can be set to reconfigure the detection logic so that it detects edges and levels.
In KBIMOD = 1 mode, the KBF status flag becomes set when an edge is detected (when one or more
enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their
deasserted levels), but the flag is continuously set (and cannot be cleared) as long as any enabled keyboard
input pin remains at the asserted level. When the MCU enters stop mode, the synchronous edge-detection
logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous
level-sensitive inputs so they can wake the MCU from stop mode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
103
Keyboard Interrupt (S08KBIV1)
7.3.3
KBI Interrupt Controls
The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If
KBIE = 1 in the KBISC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag
is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit.
When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK.
When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard
input is at its asserted level.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
104
Freescale Semiconductor
Chapter 8
Central Processor Unit (S08CPUV2)
8.1
Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
8.1.1
Features
Features of the HCS08 CPU include:
• Object code fully upward-compatible with M68HC05 and M68HC08 Families
• All registers and memory are mapped to a single 64-Kbyte address space
• 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
• 16-bit index register (H:X) with powerful indexed addressing modes
• 8-bit accumulator (A)
• Many instructions treat X as a second general-purpose 8-bit register
• Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
• Memory-to-memory data move instructions with four address mode combinations
• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
• Efficient bit manipulation instructions
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• STOP and WAIT instructions to invoke low-power operating modes
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
105
Central Processor Unit (S08CPUV2)
8.2
Programmer’s Model and CPU Registers
Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map.
7
0
ACCUMULATOR
A
16-BIT INDEX REGISTER H:X
H INDEX REGISTER (HIGH)
8
15
INDEX REGISTER (LOW)
7
X
0
SP
STACK POINTER
0
15
PROGRAM COUNTER
7
0
CONDITION CODE REGISTER V 1 1 H I N Z C
PC
CCR
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
Figure 8-1. CPU Registers
8.2.1
Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.
8.2.2
Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
106
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
8.2.3
Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
8.2.4
Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF.
The vector stored there is the address of the first instruction that will be executed after exiting the reset
state.
8.2.5
Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
107
Central Processor Unit (S08CPUV2)
7
0
CONDITION CODE REGISTER V 1 1 H I N Z C
CCR
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
Figure 8-2. Condition Code Register
Table 8-1. CCR Register Field Descriptions
Field
Description
7
V
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs.
The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1 Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
1
Z
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7
MC9S08GT16A/GT8A Data Sheet, Rev. 1
108
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
8.3
Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
8.3.1
Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
8.3.2
Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
8.3.3
Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.
8.3.4
Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
109
Central Processor Unit (S08CPUV2)
8.3.5
Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
8.3.6
Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.
8.3.6.1
Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
8.3.6.2
Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
8.3.6.3
Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
8.3.6.4
Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
8.3.6.5
Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
8.3.6.6
SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
110
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
8.3.6.7
SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
8.4
Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
8.4.1
Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
8.4.2
Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
111
Central Processor Unit (S08CPUV2)
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine
does not use any instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.
8.4.3
Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.
8.4.4
Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the Modes of Operation chapter for more details.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
112
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
8.4.5
BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background
mode rather than continuing the user program.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
113
Central Processor Unit (S08CPUV2)
8.5
HCS08 Instruction Set Summary
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Operators
()
←
&
|
⊕
×
÷
:
+
–
=
=
=
=
=
=
=
=
=
=
CPU registers
A =
CCR =
H =
X =
PC =
PCH =
PCL =
SP =
Contents of register or memory location shown inside parentheses
Is loaded with (read: “gets”)
Boolean AND
Boolean OR
Boolean exclusive-OR
Multiply
Divide
Concatenate
Add
Negate (two’s complement)
Accumulator
Condition code register
Index register, higher order (most significant) 8 bits
Index register, lower order (least significant) 8 bits
Program counter
Program counter, higher order (most significant) 8 bits
Program counter, lower order (least significant) 8 bits
Stack pointer
Memory and addressing
M = A memory location or absolute data, depending on addressing mode
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
Condition code register (CCR) bits
V = Two’s complement overflow indicator, bit 7
H = Half carry, bit 4
I = Interrupt mask, bit 3
N = Negative indicator, bit 2
Z = Zero indicator, bit 1
C = Carry/borrow, bit 0 (carry out of bit 7)
CCR activity notation
– = Bit not affected
MC9S08GT16A/GT8A Data Sheet, Rev. 1
114
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
0
1
U
=
=
=
=
Bit forced to 0
Bit forced to 1
Bit set or cleared according to results of operation
Undefined after the operation
Machine coding notation
dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00)
ee = Upper 8 bits of 16-bit offset
ff = Lower 8 bits of 16-bit offset or 8-bit offset
ii = One byte of immediate data
jj = High-order byte of a 16-bit immediate data value
kk = Low-order byte of a 16-bit immediate data value
hh = High-order byte of 16-bit extended address
ll = Low-order byte of 16-bit extended address
rr = Relative offset
Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that
must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a
literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.
n — Any label or expression that evaluates to a single integer in the range 0–7
opr8i — Any label or expression that evaluates to an 8-bit immediate value
opr16i — Any label or expression that evaluates to a 16-bit immediate value
opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit
value as the low order 8 bits of an address in the direct page of the 64-Kbyte address
space (0x00xx).
opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed
addressing
oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a
16-bit address bus, this can be either a signed or an unsigned value.
rel — Any label or expression that refers to an address that is within –128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.
Address modes
INH =
IMM =
DIR =
EXT =
Inherent (no operands)
8-bit or 16-bit immediate
8-bit direct
16-bit extended
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
115
Central Processor Unit (S08CPUV2)
IX
IX+
IX1
IX1+
=
=
=
=
IX2
REL
SP1
SP2
=
=
=
=
16-bit indexed no offset
16-bit indexed no offset, post increment (CBEQ and MOV only)
16-bit indexed with 8-bit offset from H:X
16-bit indexed with 8-bit offset, post increment
(CBEQ only)
16-bit indexed with 16-bit offset from H:X
8-bit relative offset
Stack pointer with 8-bit offset
Stack pointer with 16-bit offset
Description
V H I N Z C
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
AIS #opr8i
AIX #opr8i
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
BCC rel
A ← (A) + (M) + (C)
Add with Carry
↕
A ← (A) + (M)
Add without Carry
Add Immediate Value
(Signed) to Stack Pointer
Add Immediate Value
(Signed) to Index
Register (H:X)
↕
↕
ii
dd
hh ll
ee ff
ff
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
2
3
4
4
3
3
5
4
– – – – – – IMM
A7 ii
2
H:X ← (H:X) + (M)
M is sign extended to a 16-bit value
– – – – – – IMM
AF ii
2
A ← (A) & (M)
C
0 – – ↕
0
b7
C
b7
↕ – – ↕
↕ –
↕
↕
b0
Arithmetic Shift Right
Branch if Carry Bit Clear
↕ – ↕
↕
A9
B9
C9
D9
E9
F9
9ED9
9EE9
AB
BB
CB
DB
EB
FB
9EDB
9EEB
SP ← (SP) + (M)
M is sign extended to a 16-bit value
Logical AND
Arithmetic Shift Left
(Same as LSL)
↕ – ↕
IMM
DIR
EXT
↕ IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
↕ IX2
IX1
IX
SP2
SP1
Bus Cycles1
Operation
Operand
Effect
on CCR
Opcode
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 1 of 7)
b0
Branch if (C) = 0
↕ – – ↕
↕
↕
– – – – – –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
REL
A4
B4
C4
D4
E4
F4
9ED4
9EE4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
24
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
rr
2
3
4
4
3
3
5
4
5
1
1
5
4
6
5
1
1
5
4
6
3
MC9S08GT16A/GT8A Data Sheet, Rev. 1
116
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
V H I N Z C
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – – DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
Bus Cycles1
Description
Operand
Operation
Opcode
Effect
on CCR
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 2 of 7)
5
5
5
5
5
5
5
5
BCLR n,opr8a
Clear Bit n in Memory
Mn ← 0
BCS rel
Branch if Carry Bit Set
(Same as BLO)
Branch if (C) = 1
– – – – – – REL
25 rr
3
BEQ rel
Branch if Equal
Branch if (Z) = 1
– – – – – – REL
27 rr
3
BGE rel
Branch if Greater Than or
Equal To
(Signed Operands)
Branch if (N ⊕ V) = 0
– – – – – – REL
90 rr
3
BGND
Enter Active Background
if ENBDM = 1
Waits For and Processes BDM
Commands Until GO, TRACE1, or
TAGGO
– – – – – – INH
82
5+
BGT rel
Branch if (Z) | (N ⊕ V) = 0
– – – – – – REL
92 rr
3
Branch if (H) = 0
– – – – – – REL
28 rr
3
BHCS rel
Branch if Greater Than
(Signed Operands)
Branch if Half Carry Bit
Clear
Branch if Half Carry Bit
Set
Branch if (H) = 1
– – – – – – REL
29 rr
3
BHI rel
Branch if Higher
Branch if (C) | (Z) = 0
– – – – – – REL
22 rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
Branch if (C) = 0
– – – – – – REL
24 rr
3
BIH rel
Branch if IRQ Pin High
Branch if IRQ pin = 1
3
Branch if IRQ Pin Low
Branch if IRQ pin = 0
– – – – – – REL
– – – – – – REL
2F rr
BIL rel
2E rr
BHCC rel
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
(A) & (M)
(CCR Updated but Operands
Not Changed)
Bit Test
0 – – ↕
IMM
DIR
EXT
↕ – IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9ED5
9EE5
ii
dd
hh ll
ee ff
ff
ee ff
ff
3
2
3
4
4
3
3
5
4
BLO rel
Branch if Less Than
or Equal To
(Signed Operands)
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or Same
Branch if (C) | (Z) = 1
– – – – – – REL
23 rr
3
BLT rel
Branch if Less Than
(Signed Operands)
Branch if Interrupt Mask
Clear
Branch if (N ⊕ V ) = 1
– – – – – – REL
91 rr
3
Branch if (I) = 0
– – – – – – REL
2C rr
3
BLE rel
BMC rel
Branch if (Z) | (N ⊕ V) = 1
– – – – – – REL
93 rr
3
Branch if (C) = 1
– – – – – – REL
25 rr
3
BMI rel
Branch if Minus
Branch if (N) = 1
– – – – – – REL
2B rr
3
BMS rel
Branch if Interrupt Mask
Set
Branch if (I) = 1
– – – – – – REL
2D rr
3
– – – – – – REL
– – – – – – REL
– – – – – – REL
26 rr
3
2A rr
3
20 rr
3
BNE rel
Branch if Not Equal
Branch if (Z) = 0
BPL rel
Branch if Plus
Branch if (N) = 0
BRA rel
Branch Always
No Test
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
117
Central Processor Unit (S08CPUV2)
V H I N Z C
BRCLR n,opr8a,rel
Branch if Bit n in Memory
Clear
Branch if (Mn) = 0
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – ↕ DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRN rel
Branch Never
Uses 3 Bus Cycles
– – – – – – REL
21 rr
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – ↕ DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – – DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
– – – – – – REL
AD rr
BRSET n,opr8a,rel
Branch if Bit n in Memory
Set
BSET n,opr8a
Set Bit n in Memory
BSR rel
Branch to Subroutine
Branch if (Mn) = 1
Mn ← 1
PC ← (PC) + 0x0002
push (PCL); SP ← (SP) – 0x0001
push (PCH); SP ← (SP) – 0x0001
PC ← (PC) + rel
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and Branch if
Equal
CLC
Clear Carry Bit
C←0
CLI
Clear Interrupt Mask Bit
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Clear
Complement
(One’s Complement)
Compare Index Register
(H:X) with Memory
31
41
51
61
71
9E61
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
ii
ii
ff
rr
ff
rr
rr
rr
rr
rr
rr
rr
rr
5
5
5
5
5
5
5
5
3
rr
rr
rr
rr
rr
rr
rr
rr
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
rr
rr
rr
rr
rr
5
4
4
5
5
6
I←0
– – – – – 0 INH
– – 0 – – – INH
9A
1
M ← 0x00
A ← 0x00
X ← 0x00
H ← 0x00
M ← 0x00
M ← 0x00
M ← 0x00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
3F dd
4F
5F
8C
6F ff
7F
9E6F ff
5
1
1
1
5
4
6
A1
B1
C1
D1
E1
F1
9ED1
9EE1
33
43
53
63
73
9E63
3E
65
75
9EF3
2
3
4
4
3
3
5
4
5
1
1
5
4
6
6
3
5
6
(A) – (M)
(CCR Updated But Operands Not
Changed)
Compare Accumulator
with Memory
DIR
IMM
– – – – – – IMM
IX1+
IX+
SP1
01
03
05
07
09
0B
0D
0F
Bus Cycles1
Description
Operand
Operation
Opcode
Effect
on CCR
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 3 of 7)
↕ – – ↕
M ← (M)= 0xFF – (M)
A ← (A) = 0xFF – (A)
X ← (X) = 0xFF – (X)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
0 – – ↕
(H:X) – (M:M + 0x0001)
(CCR Updated But Operands Not
Changed)
↕ – – ↕
IMM
DIR
EXT
IX2
↕ ↕ IX1
IX
SP2
SP1
DIR
INH
↕ 1 INH
IX1
IX
SP1
EXT
↕ ↕ IMM
DIR
SP1
98
1
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
hh ll
jj kk
dd
ff
MC9S08GT16A/GT8A Data Sheet, Rev. 1
118
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
V H I N Z C
CPX
CPX
CPX
CPX
CPX
CPX
CPX
CPX
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
DAA
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
DIV
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Compare X (Index
Register Low) with
Memory
(X) – (M)
(CCR Updated But Operands Not
Changed)
↕ – – ↕
↕
IMM
DIR
EXT
↕ IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9ED3
9EE3
Decimal Adjust
Accumulator After ADD or
ADC of BCD Values
(A)10
U – – ↕ ↕ ↕ INH
72
Decrement and Branch if
Not Zero
Decrement A, X, or M
Branch if (result) ≠ 0
DBNZX Affects X Not H
DIR
INH
– – – – – – INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
Decrement
M ← (M) – 0x01
A ← (A) – 0x01
X ← (X) – 0x01
M ← (M) – 0x01
M ← (M) – 0x01
M ← (M) – 0x01
↕ – – ↕
Divide
A ← (H:A)÷(X)
H ← Remainder
Exclusive OR
Memory with
Accumulator
A ← (A ⊕ M)
M ← (M) + 0x01
A ← (A) + 0x01
X ← (X) + 0x01
M ← (M) + 0x01
M ← (M) + 0x01
M ← (M) + 0x01
Increment
PC ← Jump Address
Jump
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
PC ← Unconditional Address
Jump to Subroutine
Load Accumulator from
Memory
A ← (M)
Load Index Register (H:X)
from Memory
H:X ← (M:M + 0x0001)
DIR
INH
↕ – INH
IX1
IX
SP1
ii
dd
hh ll
ee ff
ff
ee ff
ff
Bus Cycles1
Description
Operand
Operation
Opcode
Effect
on CCR
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 4 of 7)
2
3
4
4
3
3
5
4
1
dd rr
rr
rr
ff rr
rr
ff rr
7
4
4
7
6
8
3A dd
4A
5A
6A ff
7A
9E6A ff
5
1
1
5
4
6
– – – – ↕ ↕ INH
52
6
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX
IX2
IX1
SP1
A8
B8
C8
D8
E8
F8
9ED8
9EE8
3C
4C
5C
6C
7C
9E6C
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
9ED6
9EE6
45
55
32
9EAE
9EBE
9ECE
9EFE
0 – – ↕ ↕ –
↕ – – ↕
↕ –
– – – – – –
– – – – – –
0 – – ↕ ↕ –
0 – – ↕ ↕ –
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
jj kk
dd
hh ll
ee ff
ff
ff
2
3
4
4
3
3
5
4
5
1
1
5
4
6
3
4
4
3
3
5
6
6
5
5
2
3
4
4
3
3
5
4
3
4
5
5
6
5
5
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
119
Central Processor Unit (S08CPUV2)
V H I N Z C
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
Load X (Index Register
Low) from Memory
X ← (M)
Logical Shift Left
(Same as ASL)
0 – – ↕
C
0
b7
b0
0
Logical Shift Right
C
b7
b0
(M)destination ← (M)source
Move
H:X ← (H:X) + 0x0001 in
IX+/DIR and DIR/IX+ Modes
X:A ← (X) × (A)
Unsigned multiply
M ← – (M) = 0x00 – (M)
A ← – (A) = 0x00 – (A)
X ← – (X) = 0x00 – (X)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
IMM
DIR
EXT
IX2
↕ – IX1
IX
SP2
SP1
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
DIR
INH
INH
↕ – – 0 ↕ ↕ IX1
IX
SP1
DIR/DIR
0 – – ↕ ↕ – DIR/IX+
IMM/DIR
IX+/DIR
– 0 – – – 0 INH
ii
dd
hh ll
ee ff
ff
38
48
58
68
78
9E68
34
44
54
64
74
9E64
4E
5E
6E
7E
dd
ee ff
ff
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
2
3
4
4
3
3
5
4
5
1
1
5
4
6
5
1
1
5
4
6
5
5
4
5
42
5
30 dd
40
50
60 ff
70
9E60 ff
5
1
1
5
4
6
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate
(Two’s Complement)
NOP
No Operation
Uses 1 Bus Cycle
– – – – – – INH
9D
1
NSA
Nibble Swap
Accumulator
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
1
IMM
DIR
EXT
↕ – IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9EDA
9EEA
Push (A); SP ← (SP) – 0x0001
– – – – – – INH
87
2
Push (H); SP ← (SP) – 0x0001
– – – – – – INH
8B
2
Push (X); SP ← (SP) – 0x0001
– – – – – – INH
89
2
SP ← (SP + 0x0001); Pull (A)
– – – – – – INH
86
3
SP ← (SP + 0x0001); Pull (H)
– – – – – – INH
8A
3
SP ← (SP + 0x0001); Pull (X)
– – – – – – INH
88
3
39 dd
49
59
69 ff
79
9E69 ff
5
1
1
5
4
6
ORA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Inclusive OR Accumulator
and Memory
Push Accumulator onto
Stack
Push H (Index Register
High) onto Stack
Push X (Index Register
Low) onto Stack
Pull Accumulator from
Stack
Pull H (Index Register
High) from Stack
Pull X (Index Register
Low) from Stack
Rotate Left through Carry
A ← (A) | (M)
– – ↕ ↕
0 – – ↕
↕ – – ↕
C
b7
b0
↕
DIR
INH
↕ INH
IX1
IX
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
Bus Cycles1
Description
Operand
Operation
Opcode
Effect
on CCR
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 5 of 7)
DIR
INH
↕ INH
IX1
IX
SP1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
MC9S08GT16A/GT8A Data Sheet, Rev. 1
120
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
V H I N Z C
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Rotate Right through
Carry
RSP
Reset Stack Pointer
RTI
Return from Interrupt
RTS
Return from Subroutine
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
Subtract with Carry
C
b7
SP ← 0xFF
(High Byte Not Affected)
SP ← (SP) + 0x0001; Pull (CCR)
SP ← (SP) + 0x0001; Pull (A)
SP ← (SP) + 0x0001; Pull (X)
SP ← (SP) + 0x0001; Pull (PCH)
SP ← (SP) + 0x0001; Pull (PCL)
SP ← SP + 0x0001; Pull (PCH)
SP ← SP + 0x0001; Pull (PCL)
A ← (A) – (M) – (C)
SEC
Set Carry Bit
C←1
SEI
Set Interrupt Mask Bit
I←1
STA opr8a
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
STHX opr8a
STHX opr16a
STHX oprx8,SP
STOP
STX
STX
STX
STX
STX
STX
STX
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SWI
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP
Store Accumulator in
Memory
Store H:X (Index Reg.)
Enable Interrupts:
Stop Processing
Refer to MCU
Documentation
Store X (Low 8 Bits of
Index Register)
in Memory
Subtract
Software Interrupt
36 dd
46
56
66 ff
76
9E66 ff
5
1
1
5
4
6
– – – – – – INH
9C
1
↕
↕ INH
80
9
– – – – – – INH
81
6
IMM
DIR
EXT
↕ IX2
IX1
IX
SP2
SP1
A2
B2
C2
D2
E2
F2
9ED2
9EE2
– – – – – 1 INH
– – 1 – – – INH
99
9B
DIR
EXT
IX2
↕ – IX1
IX
SP2
SP1
DIR
↕ – EXT
SP1
B7
C7
D7
E7
F7
9ED7
9EE7
35
96
9EFF
– – 0 – – – INH
8E
DIR
EXT
IX2
↕ – IX1
IX
SP2
SP1
IMM
DIR
EXT
↕ ↕ IX2
IX1
IX
SP2
SP1
BF
CF
DF
EF
FF
9EDF
9EEF
A0
B0
C0
D0
E0
F0
9ED0
9EE0
– – 1 – – – INH
83
↕ – – ↕
↕
b0
M ← (A)
(M:M + 0x0001) ← (H:X)
I bit ← 0; Stop Processing
M ← (X)
A ← (A) – (M)
PC ← (PC) + 0x0001
Push (PCL); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
Push (X); SP ← (SP) – 0x0001
Push (A); SP ← (SP) – 0x0001
Push (CCR); SP ← (SP) – 0x0001
I ← 1;
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
↕
↕
↕
↕ – – ↕
0 – – ↕
0 – – ↕
0 – – ↕
↕ – – ↕
↕
↕
DIR
INH
↕ INH
IX1
IX
SP1
Bus Cycles1
Description
Operand
Operation
Opcode
Effect
on CCR
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 6 of 7)
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
1
1
dd
hh ll
ee ff
ff
ee ff
ff
dd
hh ll
ff
3
4
4
3
2
5
4
4
5
5
2+
dd
hh ll
ee ff
ff
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
2
3
4
4
3
3
5
4
11
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
121
Central Processor Unit (S08CPUV2)
Description
V H I N Z C
TAP
TAX
TPA
Transfer Accumulator to
CCR
Transfer Accumulator to
X (Index Register Low)
Transfer CCR to
Accumulator
CCR ← (A)
↕
↕
↕
↕
↕
Bus Cycles1
Operation
Operand
Effect
on CCR
Opcode
Source
Form
Address
Mode
Table 8-2. HCS08 Instruction Set Summary (Sheet 7 of 7)
↕ INH
84
1
X ← (A)
– – – – – – INH
97
1
A ← (CCR)
– – – – – – INH
85
1
DIR
INH
↕ – INH
IX1
IX
SP1
3D dd
4D
5D
6D ff
7D
9E6D ff
4
1
1
4
3
5
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero
(M) – 0x00
(A) – 0x00
(X) – 0x00
(M) – 0x00
(M) – 0x00
(M) – 0x00
TSX
Transfer SP to Index Reg.
H:X ← (SP) + 0x0001
– – – – – – INH
95
2
TXA
Transfer X (Index Reg.
Low) to Accumulator
A ← (X)
– – – – – – INH
9F
1
TXS
Transfer Index Reg. to SP
SP ← (H:X) – 0x0001
– – – – – – INH
94
2
WAIT
Enable Interrupts; Wait
for Interrupt
I bit ← 0; Halt CPU
– – 0 – – – INH
8F
2+
1
0 – – ↕
Bus clock frequency is one-half of the CPU clock frequency.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
122
Freescale Semiconductor
Central Processor Unit (S08CPUV2)
Table 8-3. Opcode Map (Sheet 1 of 2)
Bit-Manipulation
00
5 10
5
BRSET0
3
01
BRCLR1
3
04
BRSET2
3
05
3
07
BRSET4
3
09
BRSET5
3
0B
BRSET6
3
0D
BRCLR6
3
0E
BRSET7
3
0F
BRCLR7
3
INH
IMM
DIR
EXT
DD
IX+D
INC
DIR 2
5 2F
TST
REL 2
3 3E
CPHX
REL 3
3 3F
BIH
CLR
DIR 1
ASR
INH 2
1 68
INH 1
Relative
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
IMM to DIR
DIR to IX+
ROL
DEC
ROL
DEC
DBNZ
INH 3
1 6C
DBNZ
INC
INH 2
1 6D
INC
IX1 1
4 7D
TST
INH 2
5 6E
MOV
CLRX
IX1 1
CLR
ADD
INH 2
1
INH 1
2
BD
BSR
Page 2
WAIT
5
1
JSR
REL 2
2 BE
LDX
2
AF
TXA
INH 2
AIX
LDX
DIR 3
3 CF
STX
IMM 2
EXT 3
4 DF
STX
DIR 3
EXT 3
Opcode in
Hexadecimal F0
EOR
ADC
IX2 2
IX
2
STA
IX
3
EOR
IX
3
ADC
IX1 1
3 FA
ORA
IX
3
ORA
IX1 1
3 FB
ADD
JSR
LDX
IX1 1
3 FF
IX
5
JSR
IX1 1
3 FE
IX1 1
IX
3
JMP
IX1 1
5 FD
STX
IX
3
ADD
IX1 1
3 FC
JMP
IX2 2
4 EF
STX
IX
3
LDA
IX1 1
3 F9
IX2 2
4 EE
LDX
BIT
IX1 1
3 F8
IX2 2
6 ED
JSR
EXT 3
4 DE
IX
3
STA
IX2 2
4 EC
JMP
EXT 3
6 DD
JSR
DIR 3
3 CE
LDX
IMM 2
2 BF
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit Offset
Indexed, No Offset with
Post Increment
Indexed, 1-Byte Offset with
Post Increment
JMP
DIR 3
5 CD
AND
IX1 1
3 F7
IX2 2
4 EB
ADD
EXT 3
4 DC
IX
3
LDA
IX2 2
4 EA
ORA
EXT 3
4 DB
ADD
JMP
INH 2
AE
INH
2+ 9F
ORA
CPX
IX1 1
3 F6
IX2 2
4 E9
ADC
EXT 3
4 DA
IX
3
BIT
IX2 2
4 E8
EOR
IX
3
SBC
IX1 1
3 F5
STA
ADC
DIR 3
3 CC
AND
IX2 2
4 E7
EXT 3
4 D9
CMP
IX1 1
3 F4
IX2 2
4 E6
EXT 3
4 D8
EOR
DIR 3
3 CB
ADD
IMM 2
BC
INH
1 AD
NOP
IX 1
IMM 2
2 BB
CPX
LDA
STA
IX
3
IX1 1
3 F3
IX2 2
4 E5
EXT 3
4 D7
DIR 3
3 CA
ORA
RSP
1
2+ 9E
STOP
ADC
SBC
BIT
LDA
DIR 3
3 C9
IMM 2
2 BA
ORA
SEI
INH 1
9D
IX
5 8E
MOV
ADC
INH 2
1 AB
INH 1
1 9C
CLRH
IX 1
3
IMD 2
IX+D 1
5 7F
4 8F
CLR
INH 2
INH 1
2 9B
EOR
AND
3
SUB
IX1 1
3 F2
IX2 2
4 E4
EXT 3
4 D6
DIR 3
3 C8
IMM 2
2 B9
INH 2
1 AA
CLI
TST
IX1 1
4 7E
MOV
SEC
INH 1
3 9A
PSHH
IX 1
4 8C
EOR
CPX
BIT
STA
CMP
IX2 2
4 E3
EXT 3
4 D5
DIR 3
3 C7
IMM 2
2 B8
INH 2
1 A9
PULH
IX 1
6 8B
IX1 2
5 7C
CLC
INH 1
2 99
AND
LDA
AIS
INH 2
1 A8
SBC
F0
IX1 1
3 F1
IX2 2
4 E2
EXT 3
4 D4
DIR 3
3 C6
IMM 2
2 B7
TAX
CPX
BIT
LDA
CMP
EXT 3
4 D3
DIR 3
3 C5
IMM 2
2 B6
EXT 2
1 A7
INH 1
3 98
PSHX
IX 1
4 8A
IX1 1
7 7B
INH 3
2 97
PULX
IX 1
4 89
IX1 1
5 7A
INH 2
4 6B
IX1+
LSL
STHX
PSHA
IX 1
4 88
IX1 1
5 79
INH 2
1 6A
SP1
SP2
IX+
ASR
LSL
INH 2
1 69
PULA
IX 1
4 87
IX1 1
5 78
DD 2
DIX+ 3
1 5F
1 6F
CLRA
ROR
AND
BIT
INH 2
5 A6
SBC
3
SUB
IX2 2
4 E1
EXT 3
4 D2
DIR 3
3 C4
IMM 2
2 B5
TSX
INH 1
3 96
CPX
AND
CMP
E0
SUB
EXT 3
4 D1
DIR 3
3 C3
IMM 2
2 B4
INH 2
2 A5
TPA
DIR 1
4 86
IX1 1
5 77
TSTX
INH 1
5 5E
MOV
EXT 3
5 4F
REL 2
REL
IX
IX1
IX2
IMD
DIX+
TSTA
DIR 1
6 4E
INH 2
1 67
INCX
INH 1
1 5D
CPHX
TXS
INH 1
1 95
SBC
CPX
SUB
DIR 3
3 C2
IMM 2
2 B3
REL 2
2 A4
TAP
IX 1
5 85
IMM 2
5 76
ROR
DBNZX
INH 2
1 5C
INCA
DIR 1
4 4D
CPHX
DIR 3
1 66
DECX
INH 1
4 5B
DBNZA
DIR 2
5 4C
REL 2
3 3D
BIL
DECA
DIR 1
7 4B
DBNZ
BMS
DIR 2
5 2E
Inherent
Immediate
Direct
Extended
DIR to DIR
IX+ to DIR
DEC
LSR
CMP
SBC
BLE
Register/Memory
C0
4 D0
4
DIR 3
3 C1
IMM 2
2 B2
REL 2
3 A3
INH 2
1 94
3
SUB
CMP
BGT
SWI
B0
IMM 2
2 B1
REL 2
3 A2
INH 2
11 93
IX 1
4 84
2
SUB
BLT
INH 2
5+ 92
BGND
COM
A0
REL 2
3 A1
RTS
INH 1
4 83
IX1 1
3 75
ROLX
INH 1
1 5A
DAA
3
BGE
INH 2
6 91
IX+ 1
1 82
LSR
LSLX
INH 1
1 59
CBEQ
IX1 1
5 74
INH 2
4 65
ASRX
INH 1
1 58
ROLA
DIR 1
5 4A
BMC
DIR 2
5 2D
DIR 2
ROL
REL 3
3 3C
INH 1
1 57
LSLA
DIR 1
5 49
REL 2
3 3B
BMI
DIR 2
5 2C
BCLR7
DIR 2
LSL
COM
RTI
IX 1
5 81
INH 1
5 73
INH 2
1 64
RORX
ASRA
DIR 1
5 48
REL 2
3 3A
DIR 2
5 2B
BSET7
DIR 2
5 1F
ASR
BHCS
BPL
RORA
DIR 1
5 47
REL 2
3 39
DIR 2
5 2A
BCLR6
DIR 2
5 1E
ROR
INH 1
1 63
Control
9 90
80
NEG
NSA
LDHX
IMM 2
1 56
4
IX1+ 2
1 72
LSRX
INH 1
3 55
LDHX
DIR 3
5 46
BHCC
DIR 2
5 29
BSET6
DIR 2
5 1D
STHX
CBEQ
COMX
INH 1
1 54
LSRA
DIR 1
4 45
REL 2
3 38
BCLR5
DIR 2
5 1C
LSR
BEQ
INH 1
1 53
70
IX1 1
5 71
IMM 3
6 62
DIV
COMA
DIR 1
5 44
REL 2
3 37
BSET5
DIR 2
5 1B
BRCLR5
3
0C
BNE
DIR 2
5 28
BCLR4
DIR 2
5 1A
COM
REL 2
3 36
DIR 2
5 27
BSET4
DIR 2
5 19
BRCLR4
3
0A
BCS
MUL
5
NEG
INH 2
4 61
CBEQX
IMM 3
5 52
EXT 1
5 43
REL 2
3 35
DIR 2
5 26
CBEQA
LDHX
NEGX
INH 1
4 51
DIR 3
5 42
BCC
BCLR3
DIR 2
5 18
CBEQ
REL 2
3 34
DIR 2
5 25
BSET3
DIR 2
5 17
BRCLR3
3
08
BLS
NEGA
DIR 1
5 41
REL 3
3 33
DIR 2
5 24
BCLR2
DIR 2
5 16
BRSET3
DIR 2
5 23
Read-Modify-Write
1 50
1 60
40
NEG
REL 3
3 32
BHI
BSET2
DIR 2
5 15
BRCLR2
3
06
BRN
DIR 2
5 22
BCLR1
DIR 2
5 14
5
REL 2
3 31
BSET1
DIR 2
5 13
30
BRA
DIR 2
5 21
BCLR0
DIR 2
5 12
BRSET1
3
03
BSET0
DIR 2
5 11
BRCLR0
3
02
Branch
20
3
IX
3
LDX
IX
2
STX
IX
3 HCS08 Cycles
Instruction Mnemonic
IX Addressing Mode
SUB
Number of Bytes 1
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
123
Central Processor Unit (S08CPUV2)
Table 8-3. Opcode Map (Sheet 2 of 2)
Bit-Manipulation
Branch
Read-Modify-Write
9E60
Control
Register/Memory
9ED0 5
6
NEG
CMP
SP1
CMP
4
SP2 3
SP1
9ED2 5 9EE2 4
SBC
9E63
SBC
4
SP2 3
SP1
9ED3 5 9EE3 4 9EF3
6
COM
CPX
3
SP1
9E64
6
CPX
AND
SP1
SP1
AND
4
SP2 3
SP1
9ED5 5 9EE5 4
BIT
BIT
6
4
SP2 3
SP1
9ED6 5 9EE6 4
3
SP1
9E67
6
4
SP2 3
SP1
9ED7 5 9EE7 4
9E66
6
CPHX
4
SP2 3
SP1 3
9ED4 5 9EE4 4
LSR
3
4
SUB
4
SP2 3
SP1
9ED1 5 9EE1 4
CBEQ
4
9EE0
SUB
3
SP1
9E61
6
ROR
LDA
ASR
LDA
STA
3
SP1
9E68
6
STA
4
SP2 3
SP1
9ED8 5 9EE8 4
LSL
EOR
3
SP1
9E69
6
EOR
4
SP2 3
SP1
9ED9 5 9EE9 4
ROL
ADC
3
SP1
9E6A 6
ADC
4
SP2 3
SP1
9EDA 5 9EEA 4
DEC
ORA
3
SP1
9E6B 8
ORA
4
SP2 3
SP1
9EDB 5 9EEB 4
DBNZ
ADD
4
SP1
9E6C 6
4
ADD
SP2 3
SP1
INC
3
SP1
9E6D 5
TST
3
SP1
9EAE
5
9EBE
LDHX
2
9E6F
IX 4
6
9ECE
LDHX
5
9EDE
LDHX
IX2 3
6
CLR
3
INH
IMM
DIR
EXT
DD
IX+D
Inherent
Immediate
Direct
Extended
DIR to DIR
IX+ to DIR
REL
IX
IX1
IX2
IMD
DIX+
Relative
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
IMM to DIR
DIR to IX+
SP1
SP2
IX+
IX1+
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
5
9EEE
LDX
4
9EFE
LDX
5
LDHX
IX1 4
SP2 3
SP1 3
SP1
9EDF 5 9EEF 4 9EFF 5
STX
SP1
4
SP2 3
STX
SP1 3
STHX
SP1
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit Offset
Indexed, No Offset with
Post Increment
Indexed, 1-Byte Offset with
Post Increment
Prebyte (9E) and Opcode in
Hexadecimal 9E60
6
HCS08 Cycles
Instruction Mnemonic
SP1 Addressing Mode
NEG
Number of Bytes 3
MC9S08GT16A/GT8A Data Sheet, Rev. 1
124
Freescale Semiconductor
Chapter 9
Internal Clock Generator (S08ICGV4)
9.1
Introduction
The MC9S08GT16A/GT8A microcontroller provides one internal clock generation (ICG) module to
create the system bus frequency. All functions described in this section are available on the
MC9S08GT16A/GT8A microcontroller. The EXTAL and XTAL pins share port G bits 2 and 1,
respectively. Analog supply lines VDDA and VSSA are internally derived from the MCU’s VDD and VSS
pins. Electrical parametric data for the ICG may be found in Appendix A, “Electrical Characteristics.”
ICGERCLK
SYSTEM
CONTROL
LOGIC
TPM1
TPM2
IIC1
SCI1
SCI2
SPI1
RTI
FFE
÷2
ICG
FIXED FREQ CLOCK (XCLK)
ICGOUT
÷2
BUSCLK
ICGLCLK*
CPU
BDC
COP
ATD1
RAM
ATD has min and max
frequency requirements. See
* ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A. Chapter 14, “Analog-to-Digital Converter (S08ATDV3),” and Appendix A,
“Electrical Characteristics.”
FLASH
FLASH has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics.”
Figure 9-1. System Clock Distribution Diagram
NOTE
Freescale Semiconductor programs a factory trim value for ICGTRM into
the FLASH location $FFBE (NVICGTRM). Leaving this address for the
ICGTRM value also allows debugger and programmer vendors to perform
a manual trim operation and store the resultant ICGTRM value into
NVICGTRM for users to access at a later time. The value in NVICGTRM
is not automatically loaded and therefore must be copied into ICGTTRM by
user code.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
125
VREFL
VREFH
VSSAD
VDDAD
Internal Clock Generator (S08ICGV4)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 9-2. Block Diagram Highlighting ICG Module
MC9S08GT16A/GT8A Data Sheet, Rev. 1
126
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
The ICG provides multiple options for clock sources. This offers a user great flexibility when making
choices between cost, precision, current draw, and performance. The ICG consists of four functional
blocks. Each of these is briefly described here and then in more detail in a later section.
• Oscillator block — The oscillator block provides means for connecting an external crystal or
resonator. Two frequency ranges are software selectable to allow optimal startup and stability.
Alternatively, the oscillator block can be used to route an external square wave to the system clock.
External sources can provide a very precise clock source. The oscillator is capable of being
configured for low power mode or high amplitude mode as selected by HGO.
• Internal reference generator — The internal reference generator consists of two controlled clock
sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the
background debug controller. The other internal reference clock source is typically 243 kHz and
can be trimmed for finer accuracy via software when a precise timed event is input to the MCU.
This provides a highly reliable, low-cost clock source.
• Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or
external clock source and multiplies it to a higher frequency. Status bits provide information when
the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the
external reference clock and signals whether the clock is valid or not.
• Clock select block — The clock select block provides several switch options for connecting
different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out
of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source,
and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency
clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC).
9.1.1
Features
The module is intended to be very user friendly with many of the features occurring automatically without
user intervention. To quickly configure the module, go to Section 9.5, “Initialization/Application
Information” and pick an example that best suits the application needs.
Features of the ICG and clock distribution system:
• Several options for the primary clock source allow a wide range of cost, frequency, and precision
choices:
— 32 kHz–100 kHz crystal or resonator
— 1 MHz–16 MHz crystal or resonator
— External clock
— Internal reference generator
• Defaults to self-clocked mode to minimize startup delays
• Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz)
— Uses external or internal clock as reference frequency
• Automatic lockout of non-running clock sources
• Reset or interrupt on loss of clock or loss of FLL lock
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
127
Internal Clock Generator (S08ICGV4)
•
•
•
•
•
•
•
9.1.2
Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast
frequency lock when recovering from stop3 mode
DCO will maintain operating frequency during a loss or removal of reference clock
Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)
Separate self-clocked source for real-time interrupt
Trimmable internal clock source supports SCI communications without additional external
components
Automatic FLL engagement after lock is acquired
External oscillator selectable for low power or high gain
Modes of Operation
This is a high-level description only. Detailed descriptions of operating modes are contained in
Section 9.4, “Functional Description.”
• Mode 1 — Off
The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is
executed.
• Mode 2 — Self-clocked (SCM)
Default mode of operation that is entered immediately after reset. The ICG’s FLL is open loop and
the digitally controlled oscillator (DCO) is free running at a frequency set by the filter bits.
• Mode 3 — FLL engaged internal (FEI)
In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the
internal reference clock.
— FLL engaged internal unlocked is a transition state that occurs while the FLL is attempting to
lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
— FLL engaged internal locked is a state that occurs when the FLL detects that the DCO is locked
to a multiple of the internal reference.
• Mode 4 — FLL bypassed external (FBE)
In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source.
• Mode 5 — FLL engaged external (FEE)
The ICG’s FLL is used to generate frequencies that are programmable multiples of the external
clock reference.
— FLL engaged external unlocked is a transition state that occurs while the FLL is attempting to
lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
— FLL engaged external locked is a state which occurs when the FLL detects that the DCO is
locked to a multiple of the internal reference.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
128
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.1.3
Block Diagram
Figure 9-3 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module. This section includes a general description and a feature list.
EXTAL
OSCILLATOR (OSC)
WITH EXTERNAL REF
SELECT
ICG
CLOCK
SELECT
ICGERCLK
XTAL
ICGDCLK
REF
SELECT
VDDA
(SEE NOTE 2)
FREQUENCY
LOCKED
LOOP (FLL)
DCO
OUTPUT
CLOCK
SELECT
/R
ICGOUT
LOSS OF LOCK
AND CLOCK DETECTOR
V SSA
(SEE NOTE 2)
FIXED
CLOCK
SELECT
IRG
INTERNAL TYP 243 kHz
REFERENCE
8 MHz
GENERATORS
RG
FFE
ICGIRCLK
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
ICGLCLK
NOTES:
1. See chip level clock routing diagram for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments.
Figure 9-3. ICG Block Diagram
9.2
External Signal Description
The oscillator pins are used to provide an external clock source for the MCU. The oscillator pins are gain
controlled in low-power mode (default). Oscillator amplitudes in low-power mode are limited to
approximately 1 V, peak-to-peak.
9.2.1
EXTAL — External Reference Clock / Oscillator Input
If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as either
the external clock input or the input of the oscillator circuit as determined by REFS. If upon the first write
to ICGC1, either the FEI mode or SCM mode is selected, this pin is not used by the ICG.
9.2.2
XTAL — Oscillator Output
If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the
output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
129
Internal Clock Generator (S08ICGV4)
selected, this pin is not used by the ICG. The oscillator is capable of being configured to provide a higher
amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1.
9.2.3
External Clock Connections
If an external clock is used, then the pins are connected as shown Figure 9-4.
ICG
EXTAL
XTAL
VSS
NOT CONNECTED
CLOCK INPUT
Figure 9-4. External Clock Connections
9.2.4
External Crystal/Resonator Connections
If an external crystal/resonator frequency reference is used, then the pins are connected as shown in
Figure 9-5. Recommended component values are listed in the Electrical Characteristics chapter.
ICG
EXTAL
VSS
XTAL
RS
C1
C2
RF
CRYSTAL OR RESONATOR
Figure 9-5. External Frequency Reference Connection
MC9S08GT16A/GT8A Data Sheet, Rev. 1
130
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.3
Register Definition
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all ICG registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
9.3.1
R
ICG Control Register 1 (ICGC1)
7
6
5
HGO1
RANGE
REFS
0
1
0
4
3
2
1
OSCSTEN
LOCD
1
0
0
0
CLKS
W
Reset
0
0
0
= Unimplemented or Reserved
Figure 9-6. ICG Control Register 1 (ICGC1)
1
This bit can be written only once after reset. Additional writes are ignored.
Table 9-1. ICGC1 Register Field Descriptions
Field
7
HGO
Description
High Gain Oscillator Select — The HGO bit is used to select between low power operation and high gain
operation for improved noise immunity. This bit is write-once after reset.
0 Oscillator configured for low power operation.
1 Oscillator configured for high gain operation.
6
RANGE
Frequency Range Select — The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler
multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is
write-once after a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external
modes.
0 Oscillator configured for low frequency range. FLL loop prescale factor P is 64.
1 Oscillator configured for high frequency range. FLL loop prescale factor P is 1.
5
REFS
External Reference Select — The REFS bit controls the external reference clock source for ICGERCLK. The
REFS bit is write-once after a reset.
0 External clock requested.
1 Oscillator using crystal or resonator requested.
4:3
CLKS
Clock Mode Select — The CLKS bits control the clock mode as described below. If FLL bypassed external is
requested, it will not be selected until ERCS = 1. If the ICG enters off mode, the CLKS bits will remain
unchanged. Writes to the CLKS bits will not take effect if a previous write is not complete.
00 Self-clocked
01 FLL engaged, internal reference
10 FLL bypassed, external reference
11 FLL engaged, external reference
The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits cannot
be written to 1X until after the next reset (because the EXTAL pin was not reserved).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
131
Internal Clock Generator (S08ICGV4)
Table 9-1. ICGC1 Register Field Descriptions (continued)
Field
2
OSCSTEN
1
LOCD
Description
Enable Oscillator in Off Mode — The OSCSTEN bit controls whether or not the oscillator circuit remains
enabled when the ICG enters off mode. This bit has no effect if HGO = 1 and RANGE = 1.
0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1.
1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1.
Loss of Clock Disable
0 Loss of clock detection enabled.
1 Loss of clock detection disabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
132
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.3.2
ICG Control Register 2 (ICGC2)
7
6
5
4
3
2
1
0
R
LOLRE
MFD
LOCRE
RFD
W
Reset
0
0
0
0
0
0
0
0
Figure 9-7. ICG Control Register 2 (ICGC2)
Table 9-2. ICGC2 Register Field Descriptions
Field
Description
7
LOLRE
Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a
loss of lock indication. The LOLRE bit only has an effect when LOLS is set.
0
Generate an interrupt request on loss of lock.
1
Generate a reset request on loss of lock.
6:4
MFD
Multiplication Factor — The MFD bits control the programmable multiplication factor in the FLL loop. The value
specified by the MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to
the MFD bits will not take effect if a previous write is not complete. Select a low enough value for N such that
fICGDCLK does not exceed its maximum specified value.
000 Multiplication factor = 4
001 Multiplication factor = 6
010 Multiplication factor = 8
011 Multiplication factor = 10
100 Multiplication factor = 12
101 Multiplication factor = 14
110 Multiplication factor = 16
111 Multiplication factor = 18
3
LOCRE
Loss of Clock Reset Enable — The LOCRE bit determines how the system manages a loss of clock condition.
0
Generate an interrupt request on loss of clock.
1
Generate a reset request on loss of clock.
2:0
RFD
Reduced Frequency Divider — The RFD bits control the value of the divider following the clock select circuitry.
The value specified by the RFD bits establishes the division factor (R) applied to the selected output clock source.
Writes to the RFD bits will not take effect if a previous write is not complete.
000 Division factor = 1
001 Division factor = 2
010 Division factor = 4
011 Division factor = 8
100 Division factor = 16
101 Division factor = 32
110 Division factor = 64
111 Division factor = 128
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
133
Internal Clock Generator (S08ICGV4)
9.3.3
ICG Status Register 1 (ICGS1)
7
R
6
CLKST
5
4
3
2
1
0
REFST
LOLS
LOCK
LOCS
ERCS
ICGIF
W
Reset
1
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-8. ICG Status Register 1 (ICGS1)
Table 9-3. ICGS1 Register Field Descriptions
Field
Description
7:6
CLKST
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Self-clocked
01 FLL engaged, internal reference
10 FLL bypassed, external reference
11 FLL engaged, external reference
5
REFST
Reference Clock Status — The REFST bit indicates which clock reference is currently selected by the
Reference Select circuit.
0 External Clock selected.
1 Crystal/Resonator selected.
4
LOLS
FLL Loss of Lock Status — The LOLS bit is an indication of FLL lock status.
0 FLL has not unexpectedly lost lock since LOLS was last cleared.
1 FLL has unexpectedly lost lock since LOLS was last cleared, LOLRE determines action taken.
3
LOCK
FLL Lock Status — The LOCK bit indicates whether the FLL has acquired lock. The LOCK bit is cleared in off,
self-clocked, and FLL bypassed modes.
0 FLL is currently unlocked.
1 FLL is currently locked.
2
LOCS
Loss Of Clock Status — The LOCS bit is an indication of ICG loss of clock status.
0 ICG has not lost clock since LOCS was last cleared.
1 ICG has lost clock since LOCS was last cleared, LOCRE determines action taken.
1
ERCS
External Reference Clock Status — The ERCS bit is an indication of whether or not the external reference
clock (ICGERCLK) meets the minimum frequency requirement.
0 External reference clock is not stable, frequency requirement is not met.
1 External reference clock is stable, frequency requirement is met.
0
ICGIF
ICG Interrupt Flag — The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by
a reset or by reading the ICG status register when ICGIF is set and then writing a logic 1 to ICGIF. If another ICG
interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain set after
the clear sequence was completed for the earlier interrupt. Writing a logic 0 to ICGIF has no effect.
0 No ICG interrupt request is pending.
1 An ICG interrupt request is pending.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
134
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.3.4
R
ICG Status Register 2 (ICGS2)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DCOS
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 9-9. ICG Status Register 2 (ICGS2)
Table 9-4. ICGS2 Register Field Descriptions
Field
Description
0
DCOS
DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error
has not changed by more than nunlock for two consecutive samples and the DCO clock is not static. This bit is
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used
in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the
off state.
0 DCO clock is unstable.
1 DCO clock is stable.
9.3.5
R
ICG Filter Registers (ICGFLTU, ICGFLTL)
7
6
5
4
0
0
0
0
3
2
1
0
0
0
FLT
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-10. ICG Upper Filter Register (ICGFLTU)
Table 9-5. ICGFLTU Register Field Descriptions
Field
Description
3:0
FLT
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
135
Internal Clock Generator (S08ICGV4)
7
6
5
4
3
2
1
0
0
0
0
0
R
FLT
W
Reset
1
1
0
0
Figure 9-11. ICG Lower Filter Register (ICGFLTL)
Table 9-6. ICGFLTL Register Field Descriptions
Field
Description
7:0
FLT
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete. The filter registers show the filter value (FLT).
9.3.6
ICG Trim Register (ICGTRM)
7
6
5
4
3
2
1
0
R
TRIM
W
POR
1
0
0
0
0
0
0
0
Reset:
U
U
U
U
U
U
U
U
U = Unaffected by MCU reset
Figure 9-12. ICG Trim Register (ICGTRM)
Table 9-7. ICGTRM Register Field Descriptions
Field
7
TRIM
Description
ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ±25%
adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice
as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value
will decrease the period.
9.4
Functional Description
This section provides a functional description of each of the five operating modes of the ICG. Also
discussed are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG
is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When
using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value
to ensure proper MCU operation.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
136
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.4.1
Off Mode (Off)
Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state.
However there are two cases to consider when clock activity continues while the CPU is in stop mode,
9.4.1.1
BDM Active
When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to
memory and control registers via the BDC controller.
9.4.1.2
OSCSTEN Bit Set
When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled
but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator
startup times if necessary, or to run the RTI from the oscillator during stop3.
9.4.1.3
Stop/Off Mode Recovery
Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
9.4.2
Self-Clocked Mode (SCM)
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
• After any reset.
• Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
• CLKS bits are written from X1 to 00.
• CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by fICGDCLK / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, fICGDCLK will default to fSelf_reset which is nominally 8 MHz. If this
mode is entered from FLL engaged internal, fICGDCLK will maintain the previous frequency.If this mode
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), fICGDCLK will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
If this mode is entered from off mode, fICGDCLK will be equal to the frequency of ICGDCLK before
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
137
Internal Clock Generator (S08ICGV4)
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
CLKST
REFERENCE
DIVIDER (/7)
ICGIRCLK
CLKS
RFD
CLOCK
SELECT
CIRCUIT
REDUCED
FREQUENCY
DIVIDER (R)
RANGE
ICGOUT
ICGDCLK
FLT
MFD
1x
DIGITALLY
CONTROLLED
OSCILLATOR
2x
DIGITAL
LOOP
FILTER
SUBTRACTOR
FLL ANALOG
ICGERCLK
CLKST
FREQUENCYLOCKED
LOOP (FLL)
OVERFLOW
ICG2DCLK
PULSE
COUNTER
COUNTER ENABLE
RANGE
LOCK AND
LOSS OF CLOCK
DETECTOR
DCOS LOCK LOLS
LOCS ERCS
RESET AND
INTERRUPT
CONTROL
LOCD
IRQ
RESET
ICGIF LOLRE LOCRE
Figure 9-13. Detailed Frequency-Locked Loop Block Diagram
9.4.3
FLL Engaged, Internal Clock (FEI) Mode
FLL engaged internal (FEI) is entered when any of the following conditions occur:
• CLKS bits are written to 01
• The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
138
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.4.4
FLL Engaged Internal Unlocked
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (∆n) output from
the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the
lock detector to detect the unlock condition.
The ICG will remain in this state while the count error (∆n) is greater than the maximum nlock or less than
the minimum nlock, as required by the lock detector to detect the lock condition.
In this state the output clock signal ICGOUT frequency is given by fICGDCLK / R.
9.4.5
FLL Engaged Internal Locked
FLL engaged internal locked is entered from FEI unlocked when the count error (∆n), which comes from
the subtractor, is less than nlock (max) and greater than nlock (min) for a given number of samples, as
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by fICGDCLK / R. In FEI locked, the filter value is updated only once every four comparison cycles.
The update made is an average of the error measurements taken in the four previous comparisons.
9.4.6
FLL Bypassed, External Clock (FBE) Mode
FLL bypassed external (FBE) is entered when any of the following conditions occur:
• From SCM when CLKS = 10 and ERCS is high
• When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
• From FLL engaged external mode if a loss of DCO clock occurs and the external reference remains
valid (both LOCS = 1 and ERCS = 1)
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by fICGERCLK / R. If an external clock
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
9.4.7
FLL Engaged, External Clock (FEE) Mode
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
• CLKS = 11 and ERCS and DCOS are both high.
• The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from Table 9-12 is 4. Because 4 X 10 MHz is 40MHz, which is the
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
139
Internal Clock Generator (S08ICGV4)
9.4.7.1
FLL Engaged External Unlocked
FEE unlocked is entered when FEE is entered and the count error (∆n) output from the subtractor is greater
than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the
unlock condition.
The ICG will remain in this state while the count error (∆n) is greater than the maximum nlock or less than
the minimum nlock, as required by the lock detector to detect the lock condition.
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by fICGDCLK / (2×R) This
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. After the FLL has locked, if an unexpected loss of lock
causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by fICGDCLK / R.
9.4.7.2
FLL Engaged External Locked
FEE locked is entered from FEE unlocked when the count error (∆n) is less than nlock (max) and greater
than nlock (min) for a given number of samples, as required by the lock detector to detect the lock
condition. The output clock signal ICGOUT frequency is given by fICGDCLK/R. In FLL engaged external
locked, the filter value is updated only once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
9.4.8
FLL Lock and Loss-of-Lock Detection
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see Table 9-9 for explanation of a comparison cycle) and passes this number to
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, ∆n. To
achieve locked status, ∆n must be between nlock (min) and nlock (max). After the FLL has locked, ∆n must
stay between nunlock (min) and nunlock (max) to remain locked. If ∆n goes outside this range unexpectedly,
the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is
cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset
(LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up
from stop.
Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the
TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the
LOLS will not be set.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
140
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.4.9
FLL Loss-of-Clock Detection
The reference clock and the DCO clock are monitored under different conditions (see Table 9-8). Provided
the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum
frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls
below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.
LOCS will remain set until it is acknowledged or until the MCU is reset. LOCS is cleared by reading
ICGS1 then writing 1 to ICGIF (LOCRE = 0), or by a loss-of-clock induced reset (LOCRE = 1), or by any
MCU reset.
If the ICG is in FEE, a loss of reference clock causes the ICG to enter SCM, and a loss of DCO clock causes
the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to
enter SCM. In each case, the CLKST and CLKS bits will be automatically changed to reflect the new state.
If the ICG is in FEE mode when a loss of clock occurs and the ERCS is still set to 1, then the CLKST bits
are set to 10 and the ICG reverts to FBE mode.
A loss of clock will also cause a loss of lock when in FEE or FEI modes. Because the method of clearing
the LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE = 1 and
LOCRE = 0. In this case, the interrupt would be overridden by the reset for the loss of lock.
Table 9-8. Clock Monitoring (When LOCD = 0)
Mode
CLKS
REFST
ERCS
External Reference
Clock
Monitored?
DCO Clock
Monitored?
Off
0X or 11
X
Forced Low
No
No
10
0
Forced Low
No
No
10
1
Real-Time1
Yes(1)
No
0X
X
Forced Low
No
Yes2
10
0
Forced High
No
Yes(2)
10
1
Real-Time
Yes
Yes(2)
11
X
Real-Time
Yes
Yes(2)
FEI
(CLKST = 01)
0X
X
Forced Low
No
Yes
11
X
Real-Time
Yes
Yes
FBE
(CLKST = 10)
10
0
Forced High
No
No
10
1
Real-Time
Yes
No
FEE
(CLKST = 11)
11
X
Real-Time
Yes
Yes
SCM
(CLKST = 00)
1
2
If ENABLE is high (waiting for external crystal start-up after exiting stop).
DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
141
Internal Clock Generator (S08ICGV4)
9.4.10
Clock Mode Requirements
A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by
CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should
be the same as the requested mode in CLKS1:CLKS0. Table 9-9 shows the relationship between CLKS,
CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
NOTE
If a crystal will be used before the next reset, then be sure to set REFS = 1
and CLKS = 1x on the first write to the ICGC1 register. Failure to do so will
result in “locking” REFS = 0 which will prevent the oscillator amplifier
from being enabled until the next reset occurs.
Table 9-9. ICG State Table
Actual
Mode
(CLKST)
Off
(XX)
SCM
(00)
FEI
(01)
FBE
(10)
FEE
(11)
Desired
Mode
(CLKS)
Range
Reference
Frequency
(fREFERENCE)
Comparison
Cycle Time
ICGOUT
Conditions1 for
CLKS = CLKST
Reason
CLKS1 ≠
CLKST
Off
(XX)
X
0
—
0
—
—
FBE
(10)
X
0
—
0
—
ERCS = 0
SCM
(00)
X
fICGIRCLK/72
8/fICGIRCLK
ICGDCLK/R
Not switching
from FBE to
SCM
—
FEI
(01)
0
fICGIRCLK/7(1)
8/fICGIRCLK
ICGDCLK/R
—
DCOS = 0
FBE
(10)
X
fICGIRCLK/7(1)
8/fICGIRCLK
ICGDCLK/R
—
ERCS = 0
FEE
(11)
X
fICGIRCLK/7(1)
8/fICGIRCLK
ICGDCLK/R
—
DCOS = 0 or
ERCS = 0
FEI
(01)
0
fICGIRCLK/7
8/fICGIRCLK
ICGDCLK/R
DCOS = 1
—
FEE
(11)
X
fICGIRCLK/7
8/fICGIRCLK
ICGDCLK/R
—
ERCS = 0
FBE
(10)
X
0
—
ICGERCLK/R
ERCS = 1
—
FEE
(11)
X
0
—
ICGERCLK/R
—
LOCS = 1 &
ERCS = 1
0
fICGERCLK
2/fICGERCLK
ICGDCLK/R3
ERCS = 1 and
DCOS = 1
—
1
fICGERCLK
128/fICGERCLK
ICGDCLK/R(2)
ERCS = 1 and
DCOS = 1
—
FEE
(11)
1
CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new
value.
2
The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons
that determine the DCOS bit
3 After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are changed.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
142
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.4.11
Fixed Frequency Clock
The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is
equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to
ICGERCLK ÷ 2 when the following conditions are met:
• (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 9-11), N and R are determined by
MFD and RFD respectively (see Table 9-12).
• LOCK = 1.
If the above conditions are not true, then XCLK is equal to BUSCLK.
When the ICG is in either FEI or SCM mode, XCLK is turned off. Any peripherals which can use XCLK
as a clock source must not do so when the ICG is in FEI or SCM mode.
9.4.12
High Gain Oscillator
The oscillator has the option of running in a high gain oscillator (HGO) mode, which improves the
oscillator's resistance to EMC noise when running in FBE or FEE modes. This option is selected by writing
a 1 to the HGO bit in the ICGC1 register. HGO is used with both the high and low range oscillators but is
only valid when REFS = 1 in the ICGC1 register. When HGO = 0, the standard low-power oscillator is
selected. This bit is writable only once after any reset.
9.5
9.5.1
Initialization/Application Information
Introduction
The section is intended to give some basic direction on which configuration a user would want to select
when initializing the ICG. For some applications, the serial communication link may dictate the accuracy
of the clock reference. For other applications, lowest power consumption may be the chief clock
consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in
choosing which is best for any application.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
143
Internal Clock Generator (S08ICGV4)
Table 9-10. ICG Configuration Consideration
Clock Reference Source = Internal
1
Clock Reference Source = External
FLL
Engaged
FEI
4 MHz < fBus < 20 MHz.
Medium power (will be less than FEE if oscillator
range = high)
Good clock accuracy (After IRG is trimmed)
Lowest system cost (no external components
required)
IRG is on. DCO is on. 1
FEE
4 MHz < fBus < 20 MHz
Medium power (will be less than FEI if oscillator
range = low)
High clock accuracy
Medium/High system cost (crystal, resonator or
external clock source required)
IRG is off. DCO is on.
FLL
Bypassed
SCM
This mode is mainly provided for quick and reliable
system startup.
3 MHz < fBus < 5 MHz (default).
3 MHz < fBus < 20 MHz (via filter bits).
Medium power
Poor accuracy.
IRG is off. DCO is on and open loop.
FBE
fBus range ≤ 8 MHz when crystal or resonator is
used.
Lowest power
Highest clock accuracy
Medium/High system cost (Crystal, resonator or
external clock source required)
IRG is off. DCO is off.
The IRG typically consumes 100 µA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency.
For minimum power consumption and minimum jitter, choose N and R to be as small as possible.
The following sections contain initialization examples for various configurations.
NOTE
Hexadecimal values designated by a preceding $, binary values designated
by a preceding %, and decimal values have no preceding character.
Important configuration information is repeated here for reference.
Table 9-11. ICGOUT Frequency Calculation Options
Clock Scheme
SCM — self-clocked mode (FLL bypassed
internal)
FBE — FLL bypassed external
FEI — FLL engaged internal
FEE — FLL engaged external
1
fICGOUT1
P
Note
fICGDCLK / R
NA
Typical fICGOUT = 8 MHz
immediately after reset
fext / R
NA
(fIRG / 7)* 64 * N / R
64
fext * P * N / R
Range = 0 ; P = 64
Range = 1; P = 1
Typical fIRG = 243 kHz
Ensure that fICGDCLK, which is equal to fICGOUT * R, does not exceed fICGDCLKmax.
Table 9-12. MFD and RFD Decode Table
MFD Value
Multiplication Factor (N)
RFD
Division Factor (R)
000
001
010
011
100
4
6
8
10
12
000
001
010
011
100
÷1
÷2
÷4
÷8
÷16
MC9S08GT16A/GT8A Data Sheet, Rev. 1
144
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
Table 9-12. MFD and RFD Decode Table
101
110
111
9.5.2
14
16
18
101
110
111
÷32
÷64
÷128
Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz
In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to
8.38 MHz to achieve 4.19 MHz bus frequency.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (fBus).
The clock scheme will be FLL engaged, external (FEE). So
fICGOUT = fext * P * N / R ; P = 64, fext = 32 kHz
Eqn. 9-1
N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1
Eqn. 9-2
Solving for N / R gives:
The values needed in each register to set up the desired operation are:
ICGC1 = $38 (%00111000)
Bit 7
Bit 6
Bit 5
Bits 4:3
Bit 2
Bit 1
Bit 0
HGO
RANGE
REFS
CLKS
OSCSTEN
LOCD
0
0
1
11
0
0
0
Configures oscillator for low power
Configures oscillator for low-frequency range; FLL prescale factor is 64
Oscillator using crystal or resonator is requested
FLL engaged, external reference clock mode
Oscillator disabled
Loss-of-clock detection enabled
Unimplemented or reserved, always reads zero
ICGC2 = $00 (%00000000)
Bit 7
Bits 6:4
Bit 3
Bits 2:0
LOLRE
MFD
LOCRE
RFD
0
Generates an interrupt request on loss of lock
000 Sets the MFD multiplication factor to 4
0
Generates an interrupt request on loss of clock
000 Sets the RFD division factor to ÷1
ICGS1 = $xx
This is read only except for clearing interrupt flag
ICGS2 = $xx
This is read only; should read DCOS = 1 before performing any time critical tasks
ICGFLTLU/L = $xx
Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock
Bits 15:12 unused
0000
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
145
Internal Clock Generator (S08ICGV4)
Bits 11:0 FLT
No need for user initialization
ICGTRM = $xx
Bits 7:0
TRIM
Only need to write when trimming internal oscillator; not used when external
crystal is clock source
Figure 9-14 shows flow charts for three conditions requiring ICG initialization.
RESET
INITIALIZE ICG
ICGC1 = $38
ICGC2 = $00
CHECK
FLL LOCK STATUS.
LOCK = 1?
QUICK RECOVERY FROM STOP
MINIMUM CURRENT DRAW IN STOP
RECOVERY FROM STOP
OSCSTEN = 1
RECOVERY FROM STOP
OSCSTEN = 0
CHECK
FLL LOCK STATUS.
LOCK = 1?
NO
CHECK
FLL LOCK STATUS.
LOCK = 1?
NO
YES
YES
NO
CONTINUE
CONTINUE
YES
CONTINUE
NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND
STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR
AND EXTERNAL CIRCUITRY.
Figure 9-14. ICG Initialization for FEE in Example #1
MC9S08GT16A/GT8A Data Sheet, Rev. 1
146
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.5.3
Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz
In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to
40-MHz to achieve 20 MHz bus frequency.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
During reset initialization software, the clock scheme will be set to FLL engaged, external (FEE). So
fICGOUT = fext * P * N / R ; P = 1, fext = 4.00 MHz
Eqn. 9-3
N / R = 40 MHz /(4 MHz * 1) = 10 ; We can choose N = 10 and R = 1
Eqn. 9-4
Solving for N / R gives:
The values needed in each register to set up the desired operation are:
ICGC1 = $78
Bit 7
Bit 6
Bit 5
Bits 4:3
Bit 2
Bit 1
Bit 0
HGO
RANGE
REFS
CLKS
OSCSTEN
LOCD
ICGC2 = $30
Bit 7
Bit 6:4
Bit 3
Bit 2:0
(%01111000)
0
1
1
11
0
0
0
Configures oscillator for low power
Configures oscillator for high-frequency range; FLL prescale factor is 1
Requests an oscillator
FLL engaged, external reference clock mode
Disables the oscillator
Loss-of-clock detection enabled
Unimplemented or reserved, always reads zero
(%00110000)
LOLRE
MFD
LOCRE
RFD
0
Generates an interrupt request on loss of lock
011 Sets the MFD multiplication factor to 10
0
Generates an interrupt request on loss of clock
000 Sets the RFD division factor to ÷1
ICGS1 = $xx
This is read only except for clearing interrupt flag
ICGS2 = $xx
This is read only. Should read DCOS before performing any time critical tasks
ICGFLTLU/L = $xx
Not used in this example
ICGTRM
Not used in this example
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
147
Internal Clock Generator (S08ICGV4)
RECOVERY
FROM STOP
RESET
INITIALIZE ICG
ICGC1 = $7A
ICGC2 = $30
CHECK
FLL LOCK STATUS
LOCK = 1?
YES
SERVICE INTERRUPT
SOURCE (fBus = 4 MHz)
NO
CHECK
FLL LOCK STATUS
LOCK = 1?
NO
YES
CONTINUE
CONTINUE
Figure 9-15. ICG Initialization and Stop Recovery for Example #2
MC9S08GT16A/GT8A Data Sheet, Rev. 1
148
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.5.4
Example #3: No External Crystal Connection, 5.4 MHz Bus
Frequency
In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate)
reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim
function to fine tune the frequency based on an external reference signal.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
The clock scheme will be FLL engaged, internal (FEI). So
fICGOUT = (fIRG / 7) * P * N / R ; P = 64, fIRG = 243 kHz
Eqn. 9-5
Solving for N / R gives:
N / R = 10.8 MHz /(243/7 kHz * 64) = 4.86 ; We can choose N = 10 and R = 2.
Eqn. 9-6
A trim procedure will be required to hone the frequency to exactly 5.4 MHz. An example of the trim
procedure is shown in example #4.
The values needed in each register to set up the desired operation are:
ICGC1 = $28 (%00101000)
Bit 7
HGO
0
Bit 6
RANGE
0
Bit 5
REFS
1
Bits 4:3 CLKS
01
Bit 2
OSCSTEN 0
Bit 1
LOCD
0
Bit 0
0
Configures oscillator for low power
Configures oscillator for low-frequency range; FLL prescale factor is 64
Oscillator using crystal or resonator requested (bit is really a don’t care)
FLL engaged, internal reference clock mode
Disables the oscillator
Loss-of-clock enabled
Unimplemented or reserved, always reads zero
ICGC2 = $31 (%00110001)
Bit 7
LOLRE
0
Generates an interrupt request on loss of lock
Bit 6:4 MFD
011 Sets the MFD multiplication factor to 10
Bit 3
LOCRE
0
Generates an interrupt request on loss of clock
Bit 2:0 RFD
001 Sets the RFD division factor to ÷2
ICGS1 = $xx
This is read only except for clearing interrupt flag
ICGS2 = $xx
This is read only; good idea to read this before performing time critical operations
ICGFLTLU/L = $xx
Not used in this example
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
149
Internal Clock Generator (S08ICGV4)
ICGTRM = $xx
Bit 7:0 TRIM
Only need to write when trimming internal oscillator; done in separate
operation (see example #4)
RECOVERY
FROM STOP
RESET
INITIALIZE ICG
ICGC1 = $28
ICGC2 = $31
CHECK
FLL LOCK STATUS.
LOCK = 1?
CHECK
FLL LOCK STATUS.
LOCK = 1?
NO
YES
NO
CONTINUE
YES
CONTINUE
NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND
STABILIZE.
Figure 9-16. ICG Initialization and Stop Recovery for Example #3
MC9S08GT16A/GT8A Data Sheet, Rev. 1
150
Freescale Semiconductor
Internal Clock Generator (S08ICGV4)
9.5.5
Example #4: Internal Clock Generator Trim
The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some
cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a
trimming procedure is provided that will allow a very accurate source. This section outlines one example
of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used.
Initial conditions:
1) Clock supplied from ATE has 500 µsec duty period
2) ICG configured for internal reference with 4 MHz bus
START TRIM PROCEDURE
ICGTRM = $80, n = 1
MEASURE
INCOMING CLOCK WIDTH
(COUNT = # OF BUS CLOCKS / 4)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
.
CASE STATEMENT
COUNT = EXPECTED = 500
COUNT > EXPECTED = 500
(RUNNING TOO FAST)
ICGTRM =
ICGTRM - 128 / (2**n)
(DECREASING ICGTRM
INCREASES THE FREQUENCY)
ICGTRM =
ICGTRM + 128 / (2**n)
(INCREASING ICGTRM
DECREASES THE FREQUENCY)
STORE ICGTRM VALUE
IN NON-VOLATILE
MEMORY
CONTINUE
n = n+1
YES
IS n > 8?
NO
Figure 9-17. Trim Procedure
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in Figure 9-17 while the
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
151
Internal Clock Generator (S08ICGV4)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
152
Freescale Semiconductor
Chapter 10
Timer/PWM (S08TPMV2)
10.1
Introduction
The MC9S08GT16A/GT8A includes two independent timer/PWM (TPM) modules which support
traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on
each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned
PWM functions. In each of these two TPMs, timing functions are based on a separate 16-bit counter with
prescaler and modulo features to control frequency and range (period between overflows) of the time
reference. This timing system is ideally suited for a wide range of control applications, and the
center-aligned PWM capability on the 3-channel TPM extends the field of applications to motor control in
small appliances.
The use of the fixed system clock, XCLK, as the clock source for either of the TPM modules allows the
TPM prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This clock source must be
selected only if the ICG is configured in either FBE or FEE mode. In FBE mode, this selection is redundant
because the BUSCLK frequency is the same as XCLK. In FEE mode, the proper conditions must be met
for XCLK to equal ICGERCLK/2. Selecting XCLK as the clock source with the ICG in either FEI or SCM
mode will result in the TPM being non-functional.
10.1.1
Features
The timer system in the MC9S08GT16A includes a 3-channel TPM1 and a separate 5-channel TPM2; the
timer system in the MC9S08GT8A includes two 2-channel modules, TPM1 and TPM2. Timer system
features include:
• A total of eight channels:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system
clock, or an external pin
• Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus terminal count interrupt
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
153
VREFL
VREFH
VSSAD
VDDAD
Timer/PWM (S08TPMV2)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 10-1. Block Diagram Highlighting the TPM Modules
MC9S08GT16A/GT8A Data Sheet, Rev. 1
154
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
10.1.2
Features
The TPM has the following features:
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock sources independently selectable per TPM (multiple TPMs device)
• Selectable clock sources (device dependent): bus clock, fixed system clock, external pin
• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs
device)
• Channel features:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
10.1.3
Block Diagram
Figure 10-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various
numbers of channels.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
155
Timer/Pulse-Width Modulator (S08TPMV2)
BUSCLK
XCLK
TPMxCLK
SYNC
CLOCK SOURCE
SELECT
OFF, BUS, XCLK, EXT
CLKSB
PRESCALE AND SELECT
DIVIDE BY
1, 2, 4, 8, 16, 32, 64, or 128
PS2
CLKSA
PS1
PS0
CPWMS
MAIN 16-BIT COUNTER
TOF
COUNTER RESET
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TPMxMODH:TPMxMODL
CHANNEL 0
ELS0B
ELS0A
PORT
LOGIC
16-BIT COMPARATOR
TPMxC0VH:TPMxC0VL
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
INTERNAL BUS
CHANNEL 1
MS0B
MS0A
ELS1B
ELS1A
CH0IE
TPMxCH1
PORT
LOGIC
16-BIT COMPARATOR
CH1F
TPMxC1VH:TPMxC1VL
INTERRUPT
LOGIC
16-BIT LATCH
MS1A
ELSnB
ELSnA
...
...
MS1B
CH1IE
...
CHANNEL n
TPMxCH0
TPMxCHn
PORT
LOGIC
16-BIT COMPARATOR
TPMxCnVH:TPMxCnVL
CHnF
16-BIT LATCH
MSnB
MSnA
CHnIE
INTERRUPT
LOGIC
Figure 10-2. TPM Block Diagram
The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a
modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM
counter (when operating in normal up-counting mode) provides the timing reference for the input capture,
output compare, and edge-aligned PWM functions. The timer counter modulo registers,
TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF
effectively make the counter free running.) Software can read the counter value at any time without
affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter
regardless of the data value written.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
156
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
All TPM channels are programmable independently as input capture, output compare, or buffered
edge-aligned PWM channels.
10.2
External Signal Description
When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled.
After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive
pullups disabled.
10.2.1
External TPM Clock Sources
When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and
consequently the 16-bit counter for TPMx are driven by an external clock source, TPMxCLK, connected
to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This
synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half
the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to
be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL)
or frequency-locked loop (FLL) frequency jitter effects.
On some devices the external clock input is shared with one of the TPM channels. When a TPM channel
is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still
be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the
external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not
trying to use the same pin.
10.2.2
TPMxCHn — TPMx Channel n I/O Pins
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled
by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction
registers do not affect the related pin(s). See the Pins and Connections chapter for additional information
about shared pin functions.
10.3
Register Definition
The TPM includes:
• An 8-bit status and control register (TPMxSC)
• A 16-bit counter (TPMxCNTH:TPMxCNTL)
• A 16-bit modulo register (TPMxMODH:TPMxMODL)
Each timer channel has:
• An 8-bit status and control register (TPMxCnSC)
• A 16-bit channel value register (TPMxCnVH:TPMxCnVL)
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
157
Timer/Pulse-Width Modulator (S08TPMV2)
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some MCU systems have more than one TPM, so register names include placeholder characters to identify
which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x,
channel n and TPM1C2SC is the status and control register for timer 1, channel 2.
10.3.1
Timer x Status and Control Register (TPMxSC)
TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
7
R
6
5
4
3
2
1
0
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0
0
0
0
0
0
0
TOF
W
Reset
0
= Unimplemented or Reserved
Figure 10-3. Timer x Status and Control Register (TPMxSC)
Table 10-1. TPMxSC Register Field Descriptions
Field
Description
7
TOF
Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set
after the counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another
TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set
after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
6
TOIE
Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling)
1 TOF interrupts enabled
5
CPWMS
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears
CPWMS.
0 All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register
1 All TPMx channels operate in center-aligned PWM mode
4:3
CLKS[B:A]
Clock Source Select — As shown in Table 10-2, this 2-bit field is used to disable the TPM system or select one
of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the
bus clock by an on-chip synchronization circuit.
2:0
PS[2:0]
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in
Table 10-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects
whatever clock source is selected to drive the TPM system.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
158
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
Table 10-2. TPM Clock Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
0:0
No clock selected (TPMx disabled)
0:1
Bus rate clock (BUSCLK)
1:0
Fixed system clock (XCLK)
1:1
External source (TPMxCLK)1,2
1
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
2
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
Table 10-3. Prescale Divisor Selection
10.3.2
PS2:PS1:PS0
TPM Clock Source Divided-By
0:0:0
1
0:0:1
2
0:1:0
4
0:1:1
8
1:0:0
16
1:0:1
32
1:1:0
64
1:1:1
128
Timer x Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers.
R
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
W
Reset
Any write to TPMxCNTH clears the 16-bit counter.
0
0
0
0
0
0
Figure 10-4. Timer x Counter Register High (TPMxCNTH)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
159
Timer/Pulse-Width Modulator (S08TPMV2)
R
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
W
Reset
Any write to TPMxCNTL clears the 16-bit counter.
0
0
0
0
0
0
Figure 10-5. Timer x Counter Register Low (TPMxCNTL)
When background mode is active, the timer counter and the coherency mechanism are frozen such that the
buffer latches remain in the state they were in when the background mode became active even if one or
both bytes of the counter are read while background mode is active.
10.3.3
Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPMxMODH or TPMxMODL inhibits TOF and overflow interrupts until the other byte is written. Reset
sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo
disabled).
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 10-6. Timer x Counter Modulo Register High (TPMxMODH)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 10-7. Timer x Counter Modulo Register Low (TPMxMODL)
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
160
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
10.3.4
Timer x Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
7
6
5
4
3
2
CHnF
CHnIE
MSnB
MSnA
ELSnB
ELSnA
0
0
0
0
0
0
R
1
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 10-8. Timer x Channel n Status and Control Register (TPMxCnSC)
Table 10-4. TPMxCnSC Register Field Descriptions
Field
Description
7
CHnF
Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs
on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is
seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a
previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
6
CHnIE
Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use software polling)
1 Channel n interrupt requests enabled
5
MSnB
Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for
edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 10-5.
4
MSnA
Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for
input capture mode or output compare mode. Refer to Table 10-5 for a summary of channel mode and setup
controls.
3:2
ELSn[B:A]
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MSnB:MSnA and shown in Table 10-5, these bits select the polarity of the input edge that triggers an
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
161
Timer/Pulse-Width Modulator (S08TPMV2)
Table 10-5. Mode, Edge, and Level Selection
CPWMS
MSnB:MSnA
ELSnB:ELSnA
X
XX
00
0
00
01
01
Input capture
Capture on falling edge only
11
Capture on rising or falling edge
Output
compare
Software compare only
Toggle output on compare
10
Clear output on compare
11
Set output on compare
10
Edge-aligned
PWM
X1
XX
Capture on rising edge only
10
01
1
Configuration
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
00
1X
Mode
10
Center-aligned
PWM
X1
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
10.3.5
Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 10-9. Timer x Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 10-10. Timer Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
162
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value
into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the
timer channel value registers. This latching mechanism may be manually reset by writing to the
TPMxCnSC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various
compiler implementations.
10.4
Functional Description
All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock
source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the
TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function.
The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When
CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the
associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can
independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM
mode.
The following sections describe the main 16-bit counter and each of the timer operating modes (input
capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation
and interrupt activity depend on the operating mode, these topics are covered in the associated mode
sections.
10.4.1
Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section
discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and
manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.
Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source
for each of the TPM can be independently selected to be off, the bus clock (BUSCLK), the fixed system
clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is
one-fourth the bus rate. Refer to Section 10.3.1, “Timer x Status and Control Register (TPMxSC)” and
Table 10-2 for more information about clock source selection.
When the microcontroller is in active background mode, the TPM temporarily suspends all counting until
the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped;
therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to
operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),
the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter.
As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then
continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
163
Timer/Pulse-Width Modulator (S08TPMV2)
When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its
terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the
terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock
period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is
a software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter
changes direction at the transition from the value set in the modulus register and the next lower count value.
This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a
period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter
for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes
are captured into a buffer so when the other byte is read, the value will represent the other byte of the count
at the time the first byte was read. The counter continues to count normally, but no new value can be read
from either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either byte of the timer
count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency
mechanism in case only one byte of the counter was read before resetting the count.
10.4.2
Channel Mode Selection
Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits
in the channel n status and control registers determine the basic mode of operation for the corresponding
channel. Choices include input capture, output compare, and buffered edge-aligned PWM.
10.4.2.1
Input Capture Mode
With the input capture function, the TPM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter
into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may
be chosen as the active edge that triggers an input capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support
coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to
the channel status/control register (TPMxCnSC).
An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
164
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
10.4.2.2
Output Compare Mode
With the output compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an
output compare channel, the TPM can set, clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only
after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset
by writing to the channel status/control register (TPMxCnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
10.4.2.3
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the setting in the modulus register
(TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value
register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the
ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As Figure 10-11 shows, the output compare value in the TPM channel registers determines the pulse width
(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the
pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare
forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TPMxC
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 10-11. PWM Period and Pulse Width (ELSnA = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle
can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,
TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the
corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and
the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect
until the next full period.)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
165
Timer/Pulse-Width Modulator (S08TPMV2)
10.4.3
Center-Aligned PWM Mode
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The
output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM
signal and the period is determined by the value in TPMxMODH:TPMxMODL.
TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPMxCnVH:TPMxCnVL)
Eqn. 10-1
period = 2 x (TPMxMODH:TPMxMODL);
for TPMxMODH:TPMxMODL = 0x0001–0x7FFF
Eqn. 10-2
If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will
be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero)
modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if
generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting
period is much longer than required for normal applications.
TPMxMODH:TPMxMODL = 0x0000 is a special case that should not be used with center-aligned PWM
mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through
0xFFFF, but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other
than at 0x0000 in order to change directions from up-counting to down-counting.
Figure 10-12 shows the output compare value in the TPM channel registers (multiplied by 2), which
determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while
counting up forces the CPWM output signal low and a compare match while counting down forces the
output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then
counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
COUNT = 0
COUNT =
TPMxMODH:TPMx
OUTPUT
COMPARE
(COUNT UP)
OUTPUT
COMPARE
(COUNT DOWN)
COUNT =
TPMxMODH:TPMx
TPM1C
PULSE WIDTH
2x
2x
PERIOD
Figure 10-12. CPWM Period and Pulse Width (ELSnA = 0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,
TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are
MC9S08GT16A/GT8A Data Sheet, Rev. 1
166
Freescale Semiconductor
Timer/Pulse-Width Modulator (S08TPMV2)
transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have
been written and the timer counter overflows (reverses direction from up-counting to down-counting at the
end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to
PWM channels, not output compares.
Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF
interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they
will all update simultaneously at the start of a new period.
Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the
coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.
10.5
TPM Interrupts
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register. See the Resets,
Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local
interrupt mask control bits.
For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer
overflow, channel input capture, or output compare events. This flag may be read (polled) by software to
verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable
hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated
whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a
sequence of steps to clear the interrupt flag before returning from the interrupt service routine.
10.5.1
Clearing Timer Interrupt Flags
TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1)
followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset
and the interrupt flag remains set after the second step to avoid the possibility of missing the new event.
10.5.2
Timer Overflow Interrupt Description
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction
at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
167
Timer/Pulse-Width Modulator (S08TPMV2)
10.5.3
Channel Event Interrupt Description
The meaning of channel interrupts depends on the current mode of the channel (input capture, output
compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
Section 10.5.1, “Clearing Timer Interrupt Flags.”
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
sequence described in Section 10.5.1, “Clearing Timer Interrupt Flags.”
10.5.4
PWM End-of-Duty-Cycle Events
For channels that are configured for PWM operation, there are two possibilities:
• When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
• When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
The flag is cleared by the 2-step sequence described in Section 10.5.1, “Clearing Timer Interrupt Flags.”
MC9S08GT16A/GT8A Data Sheet, Rev. 1
168
Freescale Semiconductor
Chapter 11
Serial Communications Interface (S08SCIV1)
11.1
Introduction
The MC9S08GT16A/GT8A includes two independent serial communications interface (SCI) modules —
sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used
to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, and they can
also be used to communicate with other embedded controllers.
A flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond
115.2 kbaud. Transmit and receive within the same SCI use a common baud rate, and each SCI module
has a separate baud rate generator.
This SCI system offers many advanced features not commonly found on other asynchronous serial I/O
peripherals on other embedded controllers. The receiver employs an advanced data sampling technique
that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double
buffering on transmit and receive are also included.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
169
VREFL
VREFH
VSSAD
VDDAD
Serial Communications Interface (S08SCIV1)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 11-1. Block Diagram Highlighting the SCI Modules
MC9S08GT16A/GT8A Data Sheet, Rev. 1
170
Freescale Semiconductor
Serial Communications Interface (S08SCIV1)
11.1.1
Features
Features of SCI module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
• Programmable baud rates (13-bit modulo divider)
• Interrupt-driven or polled operation:
— Transmit data register empty and transmission complete
— Receive data register full
— Receive overrun, parity error, framing error, and noise error
— Idle receiver detect
• Hardware parity generation and checking
• Programmable 8-bit or 9-bit character length
• Receiver wakeup by idle-line or address-mark
11.1.2
Modes of Operation
See Section 11.3, “Functional Description,” for a detailed description of SCI operation in the different
modes.
• 8- and 9- bit data modes
• Stop modes — SCI is halted during all stop modes
• Loop modes
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
171
Serial Communications Interface (S08SCIV1)
11.1.3
Block Diagram
Figure 11-2 shows the transmitter portion of the SCI. (Figure 11-3 shows the receiver portion of the SCI.)
INTERNAL BUS
(WRITE-ONLY)
LOOPS
SCID – Tx BUFFER
8
7
6
5
4
3
2
1
TE
PREAMBLE (ALL 1s)
PARITY
GENERATION
PT
SHIFT ENABLE
PE
LOAD FROM SCIxD
SHIFT DIRECTION
T8
0
START
TO TxD PIN
L
SCI CONTROLS TxD
ENABLE
TRANSMIT CONTROL
SBK
TO RECEIVE
DATA IN
LSB
H
1 × BAUD
RATE CLOCK
11-BIT TRANSMIT SHIFT REGISTER
LOOP
CONTROL
BREAK (ALL 0s)
STOP
M
RSRC
TxD DIRECTION
TO TxD
PIN LOGIC
TXDIR
TDRE
TIE
TC
Tx INTERRUPT
REQUEST
TCIE
Figure 11-2. SCI Transmitter Block Diagram
MC9S08GT16A/GT8A Data Sheet, Rev. 1
172
Freescale Semiconductor
Serial Communications Interface (S08SCIV1)
Figure 11-3 shows the receiver portion of the SCI.
INTERNAL BUS
(READ-ONLY)
SCID – Rx BUFFER
16 × BAUD
RATE CLOCK
11-BIT RECEIVE SHIFT REGISTER
LOOPS
RSRC
SINGLE-WIRE
LOOP CONTROL
WAKE
ILT
8
MSB
ALL 1s
H
DATA RECOVERY
FROM RxD PIN
7
6
5
4
3
2
1
START
M
LSB
STOP
DIVIDE
BY 16
0
L
SHIFT DIRECTION
WAKEUP
LOGIC
RWU
FROM
TRANSMITTER
RDRF
RIE
IDLE
Rx INTERRUPT
REQUEST
ILIE
OR
ORIE
FE
FEIE
ERROR INTERRUPT
REQUEST
NF
NEIE
PE
PT
PARITY
CHECKING
PF
PEIE
Figure 11-3. SCI Receiver Block Diagram
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
173
Serial Communications Interface (S08SCIV1)
11.2
Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
11.2.1
SCI Baud Rate Registers (SCIxBDH, SCIxBHL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write
to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written.
SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
R
7
6
5
0
0
0
4
3
2
1
0
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
W
Reset
0
0
0
= Unimplemented or Reserved
Figure 11-4. SCI Baud Rate Register (SCIxBDH)
Table 11-1. SCIxBDH Register Field Descriptions
Field
Description
4:0
SBR[12:8]
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 11-2.
7
6
5
4
3
2
1
0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
R
W
Reset
Figure 11-5. SCI Baud Rate Register (SCIxBDL)
Table 11-2. SCIxBDL Register Field Descriptions
Field
Description
7:0
SBR[7:0]
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 11-1.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
174
Freescale Semiconductor
Serial Communications Interface (S08SCIV1)
11.2.2
SCI Control Register 1 (SCIxC1)
This read/write register is used to control various optional features of the SCI system.
7
6
5
4
3
2
1
0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0
0
0
0
0
0
0
0
R
W
Reset
Figure 11-6. SCI Control Register 1 (SCIxC1)
Table 11-3. SCIxC1 Register Field Descriptions
Field
7
LOOPS
6
SCISWAI
5
RSRC
4
M
3
WAKE
Description
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When
LOOPS = 1, the transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
RSRC bit.) RxD pin is not used by SCI.
SCI Stops in Wait Mode
0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When
LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
Receiver Wakeup Method Select — Refer to Section 11.3.3.2, “Receiver Wakeup Operation” for more
information.
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to
Section 11.3.3.2.1, “Idle-Line Wakeup” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant
bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
175
Serial Communications Interface (S08SCIV1)
11.2.3
SCI Control Register 2 (SCIxC2)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
R
W
Reset
Figure 11-7. SCI Control Register 2 (SCIxC2)
Table 11-4. SCIxC2 Register Field Descriptions
Field
7
TIE
6
TCIE
Description
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupt requested when TC flag is 1.
1 Hardware interrupts from TC disabled (use polling).
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. Normally, when TE = 1, the SCI forces the TxD pin to act as an
output for the SCI system. If LOOPS = 1 and RSRC = 0, the TxD pin reverts to being a port B general-purpose
I/O pin even if TE = 1.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
Refer to Section 11.3.2.1, “Send Break and Queued Idle,” for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
2
RE
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin.
0 Receiver off.
1 Receiver on.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
176
Freescale Semiconductor
Serial Communications Interface (S08SCIV1)
Table 11-4. SCIxC2 Register Field Descriptions (continued)
Field
Description
1
RWU
Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to Section 11.3.3.2, “Receiver Wakeup Operation,” for more details.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
0
SBK
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the
set and clear of SBK relative to the information currently being transmitted, a second break character may be
queued before software clears SBK. Refer to Section 11.3.2.1, “Send Break and Queued Idle,” for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
11.2.4
SCI Status Register 1 (SCIxS1)
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.
R
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 11-8. SCI Status Register 1 (SCIxS1)
Table 11-5. SCIxS1 Register Field Descriptions
Field
Description
7
TDRE
Transmit Data Register Empty Flag — TDRE is set immediately after reset and when a transmit data value
transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To
clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD).
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
6
TC
Transmission Complete Flag — TC is set immediately after reset and when TDRE = 1 and no data, preamble,
or break character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCIxS1 with TC = 1 and then doing one of the following three things:
• Write to the SCI data register (SCIxD) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCIxC2
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
177
Serial Communications Interface (S08SCIV1)
Table 11-5. SCIxS1 Register Field Descriptions (continued)
Field
Description
5
RDRF
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into
the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data
register (SCIxD).
0 Receive data register empty.
1 Receive data register full.
4
IDLE
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of
activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCIxS1 with IDLE = 1 and then read the SCI data register (SCIxD). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3
OR
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data
register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCIxD. To clear
OR, read SCIxS1 with OR = 1 and then read the SCI data register (SCIxD).
0 No overrun.
1 Receive overrun (new SCI data lost).
2
NF
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit
and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the
character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD).
0 No noise detected.
1 Noise detected in the received character in SCIxD.
1
FE
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCIxS1 with FE = 1 and then read the SCI data register (SCIxD).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0
PF
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read
the SCI data register (SCIxD).
0 No parity error.
1 Parity error.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
178
Freescale Semiconductor
Serial Communications Interface (S08SCIV1)
11.2.5
SCI Status Register 2 (SCIxS2)
This register has one read-only status flag. Writes have no effect.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RAF
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 11-9. SCI Status Register 2 (SCIxS2)
Table 11-6. SCIxS2 Register Field Descriptions
Field
Description
0
RAF
Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
0 SCI receiver idle waiting for a start bit.
1 SCI receiver active (RxD input not idle).
11.2.6
SCI Control Register 3 (SCIxC3)
7
R
6
5
T8
TXDIR
0
0
R8
4
3
2
1
0
ORIE
NEIE
FEIE
PEIE
0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 11-10. SCI Control Register 3 (SCIxC3)
Table 11-7. SCIxC3 Register Field Descriptions
Field
Description
7
R8
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a
ninth receive data bit to the left of the MSB of the buffered data in the SCIxD register. When reading 9-bit data,
read R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which
could allow R8 and SCIxD to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a
ninth transmit data bit to the left of the MSB of the data in the SCIxD register. When writing 9-bit data, the entire
9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to
change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such
as when it is used to generate mark or space parity), it need not be written each time SCIxD is written.
5
TXDIR
TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
179
Serial Communications Interface (S08SCIV1)
Table 11-7. SCIxC3 Register Field Descriptions (continued)
Field
Description
3
ORIE
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
2
NEIE
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
1
FEIE
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
0
PEIE
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
11.2.7
SCI Data Register (SCIxD)
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
0
0
0
0
0
0
0
0
Reset
Figure 11-11. SCI Data Register (SCIxD)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
180
Freescale Semiconductor
Serial Communications Interface (S08SCIV1)
11.3
Functional Description
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.
11.3.1
Baud Rate Generation
As shown in Figure 11-12, the clock source for the SCI baud rate generator is the bus-rate clock.
MODULO DIVIDE BY
(1 THROUGH 8191)
BUSCLK
SBR12:SBR0
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
DIVIDE BY
16
Tx BAUD RATE
Rx SAMPLING CLOCK
(16 × BAUD RATE)
BAUD RATE =
BUSCLK
[SBR12:SBR0] × 16
Figure 11-12. SCI Baud Rate Generation
SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are
no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is
accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus
frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format
and about ±4 percent for 9-bit data format. Although baud rate modulo divider settings do not always
produce baud rates that exactly match standard rates, it is normally possible to get within a few percent,
which is acceptable for reliable communications.
11.3.2
Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter (Figure 11-2), as well as
specialized functions for sending break and idle characters.
The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one
full character frame of the idle state. The transmitter then remains idle until data is available in the transmit
data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCIxD).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0,
selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits,
and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in
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Serial Communications Interface (S08SCIV1)
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCIxD.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD1 high, waiting for more
characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
11.3.2.1
Send Break and Queued Idle
The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). Normally, a program would wait for TDRE to become set to indicate the
last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit.
This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the
queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is
queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be
received as 0s in all eight data bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD1 pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a
normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
11.3.3
Receiver Functional Description
In this section, the data sampling technique used to reconstruct receiver data is described in more detail;
two variations of the receiver wakeup function are explained. (The receiver block diagram is shown in
Figure 11-3.)
The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0,
eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer
to Section 11.3.5.1, “8- and 9-Bit Data Modes.” For the remainder of this discussion, we assume the SCI
is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status
flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun
(OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program
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Serial Communications Interface (S08SCIV1)
has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid
a receiver overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is
normally satisfied in the course of the user’s program that handles receive data. Refer to Section 11.3.4,
“Interrupts and Status Flags,” for more details about flag clearing.
11.3.3.1
Data Sampling Technique
The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples
at 16 times the baud rate to search for a falling edge on the RxD1 serial data input pin. A falling edge is
defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to
divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more
samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at
least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to
determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples
taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples
at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any
sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic
level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive
data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample
clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise
or mismatched baud rates. It does not improve worst case analysis because some characters do not have
any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic
that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected
almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
11.3.3.2
Receiver Wakeup Operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first
character(s) of each message, and as soon as they determine the message is intended for a different
receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU = 1, it
inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for
handling the unimportant message characters. At the end of a message, or at the beginning of the next
message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first
character(s) of the next message.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
183
Serial Communications Interface (S08SCIV1)
11.3.3.2.1
Idle-Line Wakeup
When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When the RWU bit is set, the idle character that wakes a receiver does not set the receiver idle bit, IDLE,
or the receive data register full flag, RDRF. It therefore will not generate an interrupt when this idle
character occurs. The receiver will wake up and wait for the next data transmission which will set RDRF
and generate an interrupt if enabled.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
11.3.3.2.2
Address-Mark Wakeup
When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames. The logic 1 MSB of an address frame clears the receivers RWU bit before the
stop bit is received and sets the RDRF flag.
11.3.4
Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is
used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately
masked by local interrupt enable masks. The flags can still be polled by software when the local masks are
cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be
requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished
transmitting all data, preamble, and break characters and is idle with TxD1 high. This flag is often used in
systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt
enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware
interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE
or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then
reading SCIxD.
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Serial Communications Interface (S08SCIV1)
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains
idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE = 1 and then reading
SCIxD. After IDLE has been cleared, it cannot become set again until the receiver has received at least one
new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags —
noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF. These
flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag gets set instead and the data and any associated NF, FE, or PF
condition is lost.
11.3.5
Additional SCI Functions
The following sections describe additional SCI functions.
11.3.5.1
8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is
held in R8 in SCIxC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the
ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.
11.3.5.2
Stop Mode Operation
During all stop modes, clocks to the SCI module are halted.
In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these
two stop modes.
No SCI module registers are affected in stop3 mode.
Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3
mode). Software should ensure stop mode is not entered while there is a character being transmitted out of
or received into the SCI module.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
185
Serial Communications Interface (S08SCIV1)
11.3.5.3
Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a
general-purpose port I/O pin.
11.3.5.4
Single-Wire Operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection.
The receiver is internally connected to the transmitter output and to the TxD1 pin. The RxD1 pin is not
used and reverts to a general-purpose port I/O pin.
In single-wire mode, the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD1 pin. When
TXDIR = 0, the TxD1 pin is an input to the SCI receiver and the transmitter is temporarily disconnected
from the TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1
pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the
transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
186
Freescale Semiconductor
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.1
Introduction
The MC9S08GT16A/GT8A provides one serial peripheral interface (SPI) module. The four pins
associated with SPI functionality are shared with port E pins 2–5. See the Appendix A, “Electrical
Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the
direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as
general-purpose I/O.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
187
VREFL
VREFH
VSSAD
VDDAD
Serial Peripheral Interface (S08SPIV3)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 12-1. Block Diagram Highlighting the SPI Module
MC9S08GT16A/GT8A Data Sheet, Rev. 1
188
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
Module Initialization (Slave):
Write:
SPIC1
to configure
interrupts, set primary SPI options, slave mode select, and
system enable.
Write:
SPIC2
to configure
optional SPI features
Module Initialization (Master):
Write:
SPIC1
to configure
interrupts, set primary SPI options, master mode select,
and system enable.
Write:
SPIC2
to configure
optional SPI features
Write:
SPIBR
to set
baud rate
Module Use:
After SPI master initiates transfer by checking that SPTEF = 1 and then writing data to SPID:
Wait for SPTEF, then write to SPID
Wait for SPRF, then read from SPID
Mode fault detection can be enabled for master mode in cases where more than one SPI device might become a master
at the same time.
SPIC1
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
Module/interrupt enables and configuration
SPIC2
MODFEN
BIDIROE
SPISWAI
SPC0
SPR2
SPR1
SPR0
Bit 2
Bit 1
Bit 0
Additional configuration options.
SPIBR
SPPR2
SPPR1
SPPR0
Baud rate = (BUSCLK/SPPR[2:0])/SPR2[2:0]
SPID
Bit 7
SPIS
SPRF
Bit 6
Bit 5
Bit 4
SPTEF
MODF
Bit 3
Figure 12-2. SPI Module Quick Start
12.1.1
Features
Features of the SPI module include:
• Master or slave mode operation
• Full-duplex or single-wire bidirectional option
• Programmable transmit bit rate
• Double-buffered transmit and receive
• Serial clock phase and polarity options
• Slave select output
• Selectable MSB-first or LSB-first shifting
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
189
Serial Peripheral Interface (S08SPIV3)
12.1.2
Block Diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
12.1.2.1
SPI System Block Diagram
Figure 12-3 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
SLAVE
MASTER
MOSI
MOSI
SPI SHIFTER
7
6
5
4
3
2
SPI SHIFTER
1
0
MISO
SPSCK
CLOCK
GENERATOR
SS
MISO
7
6
5
4
3
2
1
0
SPSCK
SS
Figure 12-3. SPI System Connections
The most common uses of the SPI system include connecting simple shift registers for adding input or
output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although
Figure 12-3 shows a system where data is exchanged between two MCUs, many practical systems involve
simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a
slave to the master MCU.
12.1.2.2
SPI Module Block Diagram
Figure 12-4 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift
register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the
double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls
connections between MCU pins and the SPI module.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
190
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
PIN CONTROL
M
SPE
MOSI
(MOMI)
S
Tx BUFFER (WRITE SPID)
ENABLE
SPI SYSTEM
M
SHIFT
OUT
SPI SHIFT REGISTER
SHIFT
IN
MISO
(SISO)
S
SPC0
Rx BUFFER (READ SPID)
BIDIROE
SHIFT
DIRECTION
LSBFE
SHIFT
CLOCK
Rx BUFFER
FULL
Tx BUFFER
EMPTY
MASTER CLOCK
BUS RATE
CLOCK
SPIBR
CLOCK GENERATOR
MSTR
CLOCK
LOGIC
SLAVE CLOCK
MASTER/SLAVE
M
SPSCK
S
MASTER/
SLAVE
MODE SELECT
MODFEN
SSOE
MODE FAULT
DETECTION
SS
SPRF
SPTEF
SPTIE
MODF
SPIE
SPI
INTERRUPT
REQUEST
Figure 12-4. SPI Module Block Diagram
12.1.3
SPI Baud Rate Generation
As shown in Figure 12-5, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
191
Serial Peripheral Interface (S08SPIV3)
BUS CLOCK
PRESCALER
CLOCK RATE DIVIDER
DIVIDE BY
1, 2, 3, 4, 5, 6, 7, or 8
DIVIDE BY
2, 4, 8, 16, 32, 64, 128, or 256
SPPR2:SPPR1:SPPR0
SPR2:SPR1:SPR0
MASTER
SPI
BIT RATE
Figure 12-5. SPI Baud Rate Generation
12.2
External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
12.2.1
SPSCK — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
12.2.2
MOSI — Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes
the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether
the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is
selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
12.2.3
MISO — Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes
the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the
pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,
this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
12.2.4
SS — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being
a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select
output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select
output (SSOE = 1).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
192
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
12.3
Modes of Operation
12.3.1
SPI in Stop Modes
The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1
or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are
halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If
stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered.
12.4
Register Definition
The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
12.4.1
SPI Control Register 1 (SPIC1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
7
6
5
4
3
2
1
0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
0
0
1
0
0
R
W
Reset
Figure 12-6. SPI Control Register 1 (SPIC1)
Table 12-1. SPIC1 Field Descriptions
Field
Description
7
SPIE
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
6
SPE
SPI System Enable — Disabling the SPI halts any transfer that is in progress and initializes internal state
machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled
5
SPTIE
SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
193
Serial Peripheral Interface (S08SPIV3)
Table 12-1. SPIC1 Field Descriptions (continued)
Field
Description
4
MSTR
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
CPOL
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
2
CPHA
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
1
SSOE
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 12-2.
0
LSBFE
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
Table 12-2. SS Pin Function
12.4.2
MODFEN
SSOE
Master Mode
Slave Mode
0
0
General-purpose I/O (not SPI)
Slave select input
0
1
General-purpose I/O (not SPI)
Slave select input
1
0
SS input for mode fault
Slave select input
1
1
Automatic SS output
Slave select input
SPI Control Register 2 (SPIC2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
R
7
6
5
0
0
0
4
3
MODFEN
BIDIROE
0
0
2
1
0
SPISWAI
SPC0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 12-7. SPI Control Register 2 (SPIC2)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
194
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
Table 12-3. SPIC2 Register Field Descriptions
Field
Description
4
MODFEN
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer
to Table 12-2 for more details).
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3
BIDIROE
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
1
SPISWAI
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
0
SPC0
12.4.3
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Register (SPIBR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
7
R
6
5
4
3
SPPR2
SPPR1
SPPR0
0
0
0
0
2
1
0
SPR2
SPR1
SPR0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 12-8. SPI Baud Rate Register (SPIBR)
Table 12-4. SPIBR Register Field Descriptions
Field
Description
6:4
SPPR[2:0]
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in Table 12-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 12-5).
2:0
SPR[2:0]
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table 12-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 12-5). The output of this
divider is the SPI bit rate clock for master mode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
195
Serial Peripheral Interface (S08SPIV3)
Table 12-5. SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0
Prescaler Divisor
0:0:0
1
0:0:1
2
0:1:0
3
0:1:1
4
1:0:0
5
1:0:1
6
1:1:0
7
1:1:1
8
Table 12-6. SPI Baud Rate Divisor
12.4.4
SPR2:SPR1:SPR0
Rate Divisor
0:0:0
2
0:0:1
4
0:1:0
8
0:1:1
16
1:0:0
32
1:0:1
64
1:1:0
128
1:1:1
256
SPI Status Register (SPIS)
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Writes have no meaning or effect.
R
7
6
5
4
3
2
1
0
SPRF
0
SPTEF
MODF
0
0
0
0
0
0
1
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 12-9. SPI Status Register (SPIS)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
196
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
Table 12-7. SPIS Register Field Descriptions
Field
Description
7
SPRF
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI
data register.
0 No data available in the receive data buffer
1 Data available in the receive data buffer
5
SPTEF
SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by
reading SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read
with SPTEF = 1 before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU
interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte transfers
from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift
register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so
SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After
completion of the transfer of the value in the shift register, the queued value from the transmit buffer will
automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit
buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the
buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
4
MODF
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes
low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input
only when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1, then writing to SPI control register 1 (SPIC1).
0 No mode fault error
1 Mode fault error detected
12.4.5
SPI Data Register (SPID)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 12-10. SPI Data Register (SPID)
Reads of this register return the data read from the receive data buffer. Writes to this register write data to
the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer
initiates an SPI transfer.
Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF)
is set, indicating there is room in the transmit buffer to queue a new transmit byte.
Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure to
read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition
and the data from the new transfer is lost.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
197
Serial Peripheral Interface (S08SPIV3)
12.5
Functional Description
An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then
writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register
is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate
there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing
the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in
the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were
shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data byte is
moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by
reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved
into the shifter, SPTEF is set, and a new transfer is started.
Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable
(LSBFE) bit is set, SPI data is shifted LSB first.
When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must
stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a
logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See
Section 12.5.1, “SPI Clock Formats” for more details.
Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently
being shifted out, can be queued into the transmit data buffer, and a previously received character can be
in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the
transmit buffer has room for a new character. The SPRF flag indicates when a received character is
available in the receive data buffer. The received character must be read out of the receive buffer (read
SPID) before the next transfer is finished or a receive overrun error results.
In the case of a receive overrun, the new data is lost because the receive buffer still held the previous
character and was not ready to accept the new data. There is no indication for such an overrun condition
so the application system designer must ensure that previous data has been read from the receive buffer
before a new transfer is initiated.
12.5.1
SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 12-11 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are
shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after
the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending
on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms
applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the
MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output
MC9S08GT16A/GT8A Data Sheet, Rev. 1
198
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master
SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.
BIT TIME #
(REFERENCE)
1
2
...
6
7
8
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 12-11. SPI Clock Formats (CPHA = 1)
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not
defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the
master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 12-12 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are
shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
199
Serial Peripheral Interface (S08SPIV3)
in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a
specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input
of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a
master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes
to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.
BIT TIME #
(REFERENCE)
1
2
BIT 7
BIT 0
BIT 6
BIT 1
...
6
7
8
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
...
...
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 12-12. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between
transfers.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
200
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
12.5.2
SPI Interrupts
There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit
is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can
poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should
check the flag bits to determine what event caused the interrupt. The service routine should also clear the
flag bit(s) before returning from the ISR (usually near the beginning of the ISR).
12.5.3
Mode Fault Detection
A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an
error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is
configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1),
and slave select output enable is clear (SSOE = 0).
The mode fault detection feature can be used in a system where more than one SPI device might become
a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other
SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver
conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.
When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back
to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are
disabled.
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User
software should verify the error condition has been corrected before changing the SPI back to master
mode.
12.6
Initialization/Application Information
12.6.1
12.6.1.1
SPI Module Initialization Example
Initialization Sequence
Before the SPI module can be used for communication, an initialization procedure must be carried out, as
follows:
1. Update control register 1 (SPIC1) to enable the SPI and to control interrupt enables. This register
also sets the SPI as master or slave, determines clock phase and polarity, and configures the main
SPI options.
2. Update control register 2 (SPIC2) to enable additional SPI functions such as the master mode-fault
function and bidirectional mode output. Other optional SPI functions are configured here as well.
3. Update the baud rate register (SPIBR) to set the prescaler and bit rate divisor for an SPI master.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
201
Serial Peripheral Interface (S08SPIV3)
12.6.1.2
Pseudo—Code Example
In this example, the SPI module will be set up for master mode with only transmit interrupts enabled to
run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an
active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
SPIC1 = 0x74(%01110100)
Bit 7
SPIE
= 0
Disables receive and mode fault interrupts
Bit 6
SPE
= 1
Enables the SPI system
Bit 5
SPTIE
= 1
Enables SPI transmit interrupts
Bit 4
MSTR
= 1
Sets the SPI module as a master SPI device
Bit 3
CPOL
= 0
Configures SPI clock as active-high
Bit 2
CPHA
= 1
First edge on SPSCK at start of first data transfer cycle
Bit 1
SSOE
= 0
Determines SS pin function when mode fault enabled
Bit 0
LSBFE
= 0
SPI serial data transfers start with most significant bit
SPIC2 = 0x00(%00000000)
Bit 7:5
= 000
Unimplemented
Bit 4
MODFEN
= 0
Disables mode fault function
Bit 3
BIDIROE
= 0
SPI data I/O pin acts as input
= 0
Unimplemented
Bit 2
Bit 1
SPISWAI
= 0
SPI clocks operate in wait mode
Bit 0
SPC0
= 0
SPI uses separate pins for data input and output
SPIBR = 0x00(%00000000)
Bit 7
= 0
Unimplemented
Bit 6:4
= 000
Sets prescale divisor to 1
Bit 3
= 0
Unimplemented
Bit 2:0
= 000
Sets baud rate divisor to 2
SPRF
= 0
Flag is set when receive data buffer is full
= 0
Unimplemented
Bit 5
SPTEF
= 0
Flag is set when transmit data buffer is empty
Bit 4
MODF
= 0
Mode fault flag for master mode
= 0
Unimplemented
SPIS = 0x00(%00000000)
Bit 7
Bit 6
Bit 3:0
SPID = 0xxx
Holds data to be transmitted by transmit buffer and data received by receive buffer.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
202
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
RESET
INITIALIZE SPI
SPIC1 = 0x74
SPIC2 = 0x00
SPIBR = 0x00
SPTEF = 1
?
NO
YES
READ SPIS WITH SPTEF
SET TO CLEAR FLAG,
THEN WRITE DATA TO
SPID
CONTINUE
Figure 12-13. Initialization Flowchart Example for SPI Master Device
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
203
Serial Peripheral Interface (S08SPIV3)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
204
Freescale Semiconductor
Chapter 13
Inter-Integrated Circuit (S08IICV1)
13.1
Introduction
The MC9S08GT16A/GT8A series of microcontrollers provides one inter-integrated circuit (IIC) module
for communication with other integrated circuits. The two pins associated with this module, SDA and SCL
share port C pins 2 and 3, respectively. All functionality as described in this section is available on
MC9S08GT16A/GT8A. When the IIC is enabled, the direction of pins is controlled by module
configuration. If the IIC is disabled, both pins can be used as general-purpose I/O.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
205
VREFL
VREFH
VSSAD
VDDAD
Inter-Integrated Circuit (S08IICV1)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 13-1. Block Diagram Highlighting the IIC Module
MC9S08GT16A/GT8A Data Sheet, Rev. 1
206
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
13.1.1
Features
The IIC includes these distinctive features:
• Compatible with IIC bus standard
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus busy detection
13.1.2
Modes of Operation
The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various
MCU modes is given here.
• Run mode — This is the basic mode of operation. To conserve power in this mode, disable the
module.
• Wait mode — The module will continue to operate while the MCU is in wait mode and can provide
a wake-up interrupt.
• Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP
instruction does not affect IIC register states. Stop1 and stop2 will reset the register contents.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
207
Inter-Integrated Circuit (S08IICV1)
13.1.3
Block Diagram
Figure 13-2 is a block diagram of the IIC.
ADDRESS
DATA BUS
INTERRUPT
ADDR_DECODE
CTRL_REG
DATA_MUX
FREQ_REG
ADDR_REG
STATUS_REG
DATA_REG
INPUT
SYNC
START
STOP
ARBITRATION
CONTROL
CLOCK
CONTROL
IN/OUT
DATA
SHIFT
REGISTER
ADDRESS
COMPARE
SCL
SDA
Figure 13-2. IIC Functional Block Diagram
13.2
External Signal Description
This section describes each user-accessible pin signal.
13.2.1
SCL — Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
13.2.2
SDA — Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
13.3
Register Definition
This section consists of the IIC register descriptions in address order.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
208
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
13.3.1
IIC Address Register (IICA)
7
6
5
4
3
2
1
0
0
R
ADDR
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-3. IIC Address Register (IICA)
Table 13-1. IICA Register Field Descriptions
Field
Description
7:1
ADDR[7:1]
IIC Address Register — The ADDR contains the specific slave address to be used by the IIC module. This is
the address the module will respond to when addressed as a slave.
13.3.2
IIC Frequency Divider Register (IICF)
7
6
5
4
3
2
1
0
0
0
0
R
MULT
ICR
W
Reset
0
0
0
0
0
Figure 13-4. IIC Frequency Divider Register (IICF)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
209
Inter-Integrated Circuit (S08IICV1)
Table 13-2. IICA Register Field Descriptions
Field
Description
7:6
MULT
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0
ICR
IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to
define the SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT
register (multiplier factor mul) is used to generate IIC baud rate.
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC data). The
ICR is used to determine the SDA hold value.
SDA hold time = bus period (s) * SDA hold value
Table 13-3 provides the SCL divider and SDA hold values for corresponding values of the ICR. These values can
be used to set IIC baud rate and SDA hold time. For example:
Bus speed = 8 MHz
MULT is set to 01 (mul = 2)
Desired IIC baud rate = 100 kbps
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
100000 = 8000000/(2*SCL divider)
SCL divider = 40
Table 13-3 shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result in an SDA
hold value of 9.
SDA hold time = bus period (s) * SDA hold value * mul
SDA hold time = 1/8000000 * 9 * mul = 1.125 µs * mul
If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This will result
in a different SDA hold value.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
210
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
Table 13-3. IIC Divider and Hold Values
ICR
(hex)
SCL Divider
SDA Hold
Value
ICR
(hex)
SCL Divider
SDA Hold
Value
00
20
7
20
160
17
01
22
7
21
192
17
02
24
8
22
224
33
03
26
8
23
256
33
04
28
9
24
288
49
05
30
9
25
320
49
06
34
10
26
384
65
07
40
10
27
480
65
08
28
7
28
320
33
09
32
7
29
384
33
0A
36
9
2A
448
65
0B
40
9
2B
512
65
0C
44
11
2C
576
97
0D
48
11
2D
640
97
0E
56
13
2E
768
129
0F
68
13
2F
960
129
10
48
9
30
640
65
11
56
9
31
768
65
12
64
13
32
896
129
13
72
13
33
1024
129
14
80
17
34
1152
193
15
88
17
35
1280
193
16
104
21
36
1536
257
17
128
21
37
1920
257
18
80
9
38
1280
129
19
96
9
39
1536
129
1A
112
17
3A
1792
257
1B
128
17
3B
2048
257
1C
144
25
3C
2304
385
1D
160
25
3D
2560
385
1E
192
33
3E
3072
513
1F
240
33
3F
3840
513
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
211
Inter-Integrated Circuit (S08IICV1)
13.3.3
IIC Control Register (IICC)
7
6
5
4
3
IICEN
IICIE
MST
TX
TXAK
R
W
Reset
2
1
0
0
0
0
0
0
RSTA
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-5. IIC Control Register (IICC)
Table 13-4. IICC Register Field Descriptions
Field
Description
7
IICEN
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
6
IICIE
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
5
MST
Master Mode Select — The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave Mode.
1 Master Mode.
4
TX
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
3
TXAK
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
0 An acknowledge signal will be sent out to the bus after receiving one data byte.
1 No acknowledge signal response is sent.
2
RSTA
Repeat START — Writing a one to this bit will generate a repeated START condition provided it is the current
master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
212
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
13.3.4
IIC Status Register (IICS)
7
R
6
TCF
5
4
BUSY
IAAS
3
2
0
SRW
ARBL
1
0
RXAK
IICIF
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-6. IIC Status Register (IICS)
Table 13-5. IICS Register Field Descriptions
Field
Description
7
TCF
Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid
during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by
reading the IICD register in receive mode or writing to the IICD in transmit mode.
0 Transfer in progress.
1 Transfer complete.
6
IAAS
Addressed as a Slave — The IAAS bit is set when the calling address matches the programmed slave address.
Writing the IICC register clears this bit.
0 Not addressed.
1 Addressed as a slave.
5
BUSY
Bus Busy — The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is
set when a START signal is detected and cleared when a STOP signal is detected.
0 Bus is idle.
1 Bus is busy.
4
ARBL
Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be
cleared by software, by writing a one to it.
0 Standard bus operation.
1 Loss of arbitration.
2
SRW
Slave Read/Write — When addressed as a slave the SRW bit indicates the value of the R/W command bit of
the calling address sent to the master.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
1
IICIF
IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a one to it in the interrupt routine. One of the following events can set the IICIF bit:
• One byte transfer completes
• Match of slave address to calling address
• Arbitration lost
0 No interrupt pending.
1 Interrupt pending.
0
RXAK
Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received.
1 No acknowledge received.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
213
Inter-Integrated Circuit (S08IICV1)
13.3.5
IIC Data I/O Register (IICD)
7
6
5
4
3
2
1
0
0
0
0
0
R
DATA
W
Reset
0
0
0
0
Figure 13-7. IIC Data I/O Register (IICD)
Table 13-6. IICD Register Field Descriptions
Field
Description
7:0
DATA
Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
NOTE
When transmitting out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IICD will not initiate the receive.
Reading the IICD will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7–bit 1) concatenated with the required
R/W bit (in position bit 0).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
214
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
13.4
Functional Description
This section provides a complete functional description of the IIC module.
13.4.1
IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
• START signal
• Slave address transmission
• Data transfer
• STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and illustrated in Figure 13-8.
MSB
SCL
SDA
1
LSB
2
3
4
5
6
7
CALLING ADDRESS
START
SIGNAL
1
XXX
3
4
5
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
6
7
8
9
READ/ ACK
WRITE BIT
1
XX
9
NO STOP
ACK SIGNAL
BIT
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
CALLING ADDRESS
1
DATA BYTE
LSB
2
LSB
READ/ ACK
WRITE BIT
MSB
SDA
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
SIGNAL
SCL
8
MSB
LSB
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
REPEATED
START
SIGNAL
NEW CALLING ADDRESS
READ/ NO STOP
SIGNAL
WRITE ACK
BIT
Figure 13-8. IIC Bus Transmission Signals
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
215
Inter-Integrated Circuit (S08IICV1)
13.4.1.1
START Signal
When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in Figure 13-8, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
13.4.1.2
Slave Address Transmission
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 13-8).
No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit
an address that is equal to its own slave address. The IIC cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
13.4.1.3
Data Transfer
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 13-8. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the
receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one
complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high
by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave
interprets this as an end of data transfer and releases the SDA line.
In either case, the data transfer is aborted and the master does one of two things:
• Relinquishes the bus by generating a STOP signal.
• Commences a new calling by generating a repeated START signal.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
216
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
13.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logical 1 (see Figure 13-8).
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
13.4.1.5
Repeated START Signal
As shown in Figure 13-8, a repeated START signal is a START signal generated without first generating a
STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
13.4.1.6
Arbitration Procedure
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is
set by hardware to indicate loss of arbitration.
13.4.1.7
Clock Synchronization
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see Figure 13-9). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
217
Inter-Integrated Circuit (S08IICV1)
DELAY
START COUNTING HIGH PERIOD
SCL1
SCL2
SCL
INTERNAL COUNTER RESET
Figure 13-9. IIC Clock Synchronization
13.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
13.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
13.5
Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
13.6
Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in Table 13-7 occur provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.
The user can determine the interrupt type by reading the status register.
Table 13-7. Interrupt Summary
Interrupt Source
Status
Flag
Local Enable
Complete 1-byte transfer
TCF
IICIF
IICIE
Match of received calling address
IAAS
IICIF
IICIE
Arbitration Lost
ARBL
IICIF
IICIE
MC9S08GT16A/GT8A Data Sheet, Rev. 1
218
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV1)
13.6.1
Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of
byte transfer.
13.6.2
Address Detect Interrupt
When the calling address matches the programmed slave address (IIC address register), the IAAS bit in
the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW
bit and set its Tx mode accordingly.
13.6.3
Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
• SDA sampled as a low when the master drives a high during an address or data transmit cycle.
• SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
• A START cycle is attempted when the bus is busy.
• A repeated START cycle is requested in slave mode.
• A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a one to it.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
219
Inter-Integrated Circuit (S08IICV1)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
220
Freescale Semiconductor
Chapter 14
Analog-to-Digital Converter (S08ATDV3)
The MC9S08GT16A/GT8A provides one 8-channel analog-to-digital (ATD) module. The eight ATD
channels share port B. Each channel individually can be configured for general-purpose I/O or for ATD
functionality. All features of the ATD module as described in this section are available on the
MC9S08GT16A/GT8A. Electrical parametric information for the ATD may be found in Appendix A,
“Electrical Characteristics.”
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
221
VREFL
VREFH
VSSAD
VDDAD
Analog-to-Digital Converter (S08ATDV3)
BKGD
8
4
4
COP
IRQ
LVD
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
2-CHANNEL TIMER/PWM
(TPM2)
SCL
SDA
RXD2
TXD2
CH1
CH0
3-CHANNEL TIMER/PWM
(TPM1)
CH0
CH1
CH2
SERIAL PERIPHERAL
INTERFACE (SPI)
SPSCK
MOSI
MISO
SS
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
RXD1
TXD1
VDD
VSS
VSS
VOLTAGE
REGULATOR
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
NOTE 5
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PORT G
LOW-POWER OSCILLATOR
NOTE 6
PTA3/KBIP3–
PTA0/KBIP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
INTERNAL CLOCK
GENERATOR (ICG)
EXTAL
XTAL
BKGD
PTA7/KBIP7–
PTA4/KBIP4
PTC1/RxD2
PTC0/TxD2
PORT D
RTI
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT E
IRQ
NOTES 2, 3
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
4
BDC
HCS08 SYSTEM CONTROL
RESET
NOTE 4
8
PORT B
CPU
8-BIT KEYBOARD
INTERRUPT (KBI)
PORT A
4
HCS08 CORE
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive.
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 14-1. MC9S08GT16A Block Diagram Highlighting ATD Block and Pins
MC9S08GT16A/GT8A Data Sheet, Rev. 1
222
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
14.1
Introduction
The ATD module is an analog-to-digital converter with a successive approximation register (SAR)
architecture with sample and hold.
14.1.1
•
•
•
•
•
•
•
Features
8-/10-bit resolution
14.0 µsec, 10-bit single conversion time at a conversion frequency of 2 MHz
Left-/right-justified result data
Left-justified signed data mode
Conversion complete flag or conversion complete interrupt generation
Analog input multiplexer for up to eight analog input channels
Single or continuous conversion mode
14.1.2
Modes of Operation
The ATD has two modes for low power
• Stop mode
• Power-down mode
14.1.2.1 Stop Mode
When the MCU goes into stop mode, the MCU stops the clocks and the ATD analog circuitry is turned off,
placing the module into a low-power state. Once in stop mode, the ATD module aborts any single or
continuous conversion in progress. Upon exiting stop mode, no conversions occur and the registers have
their previous values. As long as the ATDPU bit is set prior to entering stop mode, the module is reactivated
coming out of stop.
14.1.2.2 Power Down Mode
Clearing the ATDPU bit in register ATDC also places the ATD module in a low-power state. The ATD
conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down
mode. (This mode does not remove power to the ATD module.) Once in power-down mode, the ATD
module aborts any conversion in progress. Upon setting the ATDPU bit, the module is reactivated. During
power-down mode, the ATD registers are still accessible.
Note that the reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state.
14.1.3
Block Diagram
Figure 14-2 illustrates the functional structure of the ATD module.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
223
Analog-to-Digital Converter (S08ATDV3)
CONTROL
INTERRUPT
DATA
JUSTIFICATION
CONTROL AND
STATUS
REGISTERS
ADDRESS
R/W DATA
RESULT REGISTERS
SAR_REG
<9:0>
CTL
VDD
STATUS
PRESCALER
VSS
CTL
BUSCLK
CONVERSION MODE
CLOCK
PRESCALER
CONTROL BLOCK
STATE
MACHINE
CONVERSION CLOCK
DIGITAL
ANALOG
CTL
POWERDOWN
VREFH
VREFL
VSSAD
SUCCESSIVE APPROXIMATION REGISTER
ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK
ADP0
ADP1
ADP2
ADP3
ADP4
CONVERSION REGISTER
VDDAD
INPUT
MUX
ADP5
ADP6
ADP7
= INTERNAL PINS
= CHIP PADS
Figure 14-2. ATD Block Diagram
14.2
External Signal Description
The ATD supports eight input channels and requires four supply/reference/ground pins. These pins are
listed in Table 14-1.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
224
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
Table 14-1. Signal Properties
14.2.1
Name
Function
AD7–AD0
Channel input pins
VREFH
High reference voltage for ATD converter
VREFL
Low reference voltage for ATD converter
VDDAD
ATD power supply voltage
VSSAD
ATD ground supply voltage
ADP7–ADP0 — Channel Input Pins
The channel pins are used as the analog input pins of the ATD. Each pin is connected to an analog switch
which serves as the signal gate into the sample submodule.
14.2.2
VREFH, VREFL — ATD Reference Pins
These pins serve as the source for the high and low reference potentials for the converter. Separation from
the power supply pins accommodates the filtering necessary to achieve the accuracy of which the system
is capable.
14.2.3
VDDAD, VSSAD — ATD Supply Pins
These two pins are used to supply power and ground to the analog section of the ATD. Dedicated power
is required to isolate the sensitive analog circuitry from the normal levels of noise present on digital power
supplies.
NOTE
VDDAD1 and VDD must be at the same potential. Likewise, VSSAD1 and VSS
must be at the same potential.
14.3
Register Definition
The ATD has seven registers that control ATD functions.
Refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address
assignments for all ATD registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.3.1
ATD Control (ATDC)
Writes to the ATD control register will abort the current conversion, but will not start a new conversion.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
225
Analog-to-Digital Converter (S08ATDV3)
R
W
Reset
7
6
5
4
ATDPU
DJM
RES8
SGN
0
0
0
0
3
2
1
0
0
0
PRS
0
0
Figure 14-3. ATD Control Register (ATDC)
Table 14-2. ATDC Field Descriptions
Field
Description
7
ATDPU
ATD Power Up — This bit provides program on/off control over the ATD, reducing power consumption when the
ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress.
0 Disable the ATD and enter a low-power state.
1 ATD functionality.
6
DJM
Data Justification Mode — This bit determines how the 10-bit conversion result data maps onto the ATD result
register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATDRH.
For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map onto ATDRL
bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB).
For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7–0 map onto
ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB).
The effect of the DJM bit on the result is shown in Table 14-3.
0 Result register data is left justified. See Figure 14-4.
1 Result register data is right justified. See Figure 14-5.
5
RES8
ATD Resolution Select — This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD
converter has the accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit
resolution will map result data bits 9-2 onto ATDRH bits 7-0.
The effect of the RES8 bit on the result is shown in Table 14-3.
0 10-bit resolution selected.
1 8-bit resolution selected.
4
SGN
Signed Result Select — This bit determines whether the result will be signed or unsigned data. Signed data is
represented as 2’s complement data and is achieved by complementing the MSB of the result. Signed data mode
can be used only when the result is left justified (DJM = 0) and is not available for right-justified mode (DJM = 1).
When a signed result is selected, the range for conversions becomes –512 ($200) to 511 ($1FF) for 10-bit
resolution and –128 ($80) to 127 ($7F) for 8-bit resolution.
The effect of the SGN bit on the result is shown in Table 14-3.
0 Left justified result data is unsigned.
1 Left justified result data is signed.
3:0
PRS
Prescaler Rate Select — This field of bits determines the prescaled factor for the ATD conversion clock.
Table 14-4 illustrates the divide-by operation and the appropriate range of bus clock frequencies.
7
6
9
ATDRH
5
4
3
2
1
0
7
RESULT
6
0
5
4
3
2
1
0
5
4
3
2
1
0
0
ATDRL
Figure 14-4. Left-Justified Mode
7
ATDRH
6
5
4
3
2
1
9
0
7
6
RESULT
ATDRL
Figure 14-5. Right-Justified Mode
MC9S08GT16A/GT8A Data Sheet, Rev. 1
226
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
Table 14-3. Available Result Data Formats
RES8
DJM
SGN
Data Formats of Result
Analog Input
VREFH = VDDA, VREFL = VSSA
ATDRH:ATDRL
VDDA
VSSA
$00:$00
$80:$00
1
1
0
0
0
1
8-bit : left justified : unsigned
8-bit : left justified : signed
$FF:$00
$7F:$00
1
1
$00:$00
0
0
8-bit : left justified2 : unsigned
10-bit : left justified : unsigned
10-bit : left justified : signed
$FF:$00
0
0
X1
0
1
$FF:$C0
$7F:$C0
$00:$00
$80:$00
0
1
X1
10-bit : right justified : unsigned
$03:$FF
$00:$00
1
2
The SGN bit is only effective when DJM = 0. When DJM = 1, SGN is ignored.
8-bit results are always in ATDRH.
Table 14-4. Clock Prescaler Values
PRS
Factor = (PRS +1) × 2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Min Bus Clock3
Max Bus Clock
Max Bus Clock
MHz
MHz
MHz
(2 MHz max ATD Clock)1 (1 MHz max ATD Clock)2 (500 kHz min ATD Clock)
4
8
12
16
20
20
20
20
20
20
20
20
20
20
20
20
2
4
6
8
10
12
14
16
18
20
20
20
20
20
20
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Maximum ATD conversion clock frequency is 2 MHz. The max bus clock frequency is computed from the max ATD conversion
clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD conversion clock
frequency) × 2 (Factor) = 4 MHz.
2 Use these settings if the maximum desired ATD conversion clock frequency is 1 MHz. The max bus clock frequency is
computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus
clock = 1 (max ATD conversion clock frequency) × 2 (Factor) = 2 MHz.
3 Minimum ATD conversion clock frequency is 500 kHz. The min bus clock frequency is computed from the min ATD conversion
clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD conversion clock
frequency) × 2 (Factor) = 1 MHz.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
227
Analog-to-Digital Converter (S08ATDV3)
14.3.2
ATD Status and Control (ATDSC)
Writes to the ATD status and control register clears the CCF flag, cancels any pending interrupts, and
initiates a new conversion.
7
R
CCF
6
5
ATDIE
ATDCO
0
0
4
3
2
1
0
0
1
ATDCH
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 14-6. ATD Status and Control Register (ATDSC)
Table 14-5. ATDSC Register Field Descriptions
Field
Description
7
CCF
Conversion Complete Flag — The CCF is a read-only bit which is set each time a conversion is complete. The
CCF bit is cleared whenever the ATDSC register is written. It is also cleared whenever the result registers,
ATDRH or ATDRL, are read.
0 Current conversion is not complete.
1 Current conversion is complete.
ATD Interrupt Enabled — When this bit is set, an interrupt is generated upon completion of an ATD conversion.
At this time, the result registers contain the result data generated by the conversion. The interrupt will remain
pending as long as the conversion complete flag CCF is set. If the ATDIE bit is cleared, then the CCF bit must
be polled to determine when the conversion is complete. Note that system reset clears pending interrupts.
0 ATD interrupt disabled.
1 ATD interrupt enabled.
ATD Continuous Conversion — When this bit is set, the ATD will convert samples continuously and update the
result registers at the end of each conversion. When this bit is cleared, only one conversion is completed between
writes to the ATDSC register.
0 Single conversion mode.
1 Continuous conversion mode.
Analog Input Channel Select — This field of bits selects the analog input channel whose signal is sampled and
converted to digital codes. Table 14-6 lists the coding used to select the various analog input channels.
6
ATDIE
5
ATDCO
4:0
ATDCH
Table 14-6. Analog Input Channel Select Coding
ATDCH
Analog Input Channel
00
AD0
01
AD1
02
AD2
03
AD3
04
AD4
05
AD5
06
AD6
07
AD7
08–1D
Reserved (default to VREFL)
1E
VREFH
1F
VREFL
MC9S08GT16A/GT8A Data Sheet, Rev. 1
228
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
14.3.3
ATD Result Data (ATDRH, ATDRL)
For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map onto
ATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB).
7
6
5
4
3
9
2
1
0
7
6
5
4
3
2
1
0
0
RESULT
ATD1RH
ATD1RL
Figure 14-7. Left-Justified Mode
For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7–0 map
onto ATDRL bits 7–0, where bit 1 of ATDRH is the most significant bit (MSB).
7
6
5
4
3
2
1
0
7
6
9
5
4
3
2
0
0
RESULT
ATD1RH
1
ATD1RL
Figure 14-8. Right-Justified Mode
The ATD 10-bit conversion results are stored in two 8-bit result registers, ATDRH and ATDRL. The result
data is formatted either left or right justified where the format is selected using the DJM control bit in the
ATDC register. The 10-bit result data is mapped either between ATDRH bits 7–0 and ATDRL bits 7–6 (left
justified), or ATDRH bits 1–0 and ATDRL bits 7–0 (right justified).
For 8-bit conversions, the 8-bit result is always located in ATDRH bits 7–0, and the ATDRL bits read 0.
For 10-bit conversions, the six unused bits always read 0.
The ATDRH and ATDRL registers are read-only.
14.3.4
ATD Pin Enable (ATDPE)
7
6
5
4
3
2
1
0
ATDPE7
ATDPE6
ATDPE5
ATDPE4
ATDPE3
ATDPE2
ATDPE1
ATDPE0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-9. ATD Pin Enable Register (ATDPE)
Table 14-7. ATDSC Register Field Descriptions
Field
Description
7:0
ATD Pin 7–0 Enables — The ATD pin enable register allows the pins dedicated to the ATD module to be
ATDPE[7:0] configured for ATD usage. A write to this register will abort the current conversion but will not initiate a new
conversion. If the ATDPEx bit is 0 (disabled for ATD usage) but the corresponding analog input channel is
selected via the ATDCH bits, the ATD will not convert the analog input but will instead convert VREFL placing
zeroes in the ATD result registers.
0 Pin disabled for ATD usage.
1 Pin enabled for ATD usage.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
229
Analog-to-Digital Converter (S08ATDV3)
14.4
Functional Description
The ATD uses a successive approximation register (SAR) architecture. The ATD contains all the necessary
elements to perform a single analog-to-digital conversion.
A write to the ATDSC register initiates a new conversion. A write to the ATDC register will interrupt the
current conversion but it will not initiate a new conversion. A write to the ATDPE register will also abort
the current conversion but will not initiate a new conversion. If a conversion is already running when a
write to the ATDSC register is made, it will be aborted and a new one will be started.
14.4.1
Mode Control
The ATD has a mode control unit to communicate with the sample and hold (S/H) machine and the SAR
machine when necessary to collect samples and perform conversions. The mode control unit signals the
S/H machine to begin collecting a sample and for the SAR machine to begin receiving a sample. At the
end of the sample period, the S/H machine signals the SAR machine to begin the analog-to-digital
conversion process. The conversion process is terminated when the SAR machine signals the end of
conversion to the mode control unit. For VREFL and VREFH, the SAR machine uses the reference potentials
to set the sampled signal level within itself without relying on the S/H machine to deliver them.
The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital
output data from the SAR register to the result register. The result register consists of a dual-port register.
The SAR register writes data into the register through one port while the module data bus reads data out
of the register through the other port.
14.4.2
Sample and Hold
The S/H machine accepts analog signals and stores them as capacitor charge on a storage node located in
the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can
not run concurrently even though they are independent machines. Figure 14-10 shows the placement of the
various resistors and capacitors.
INPUT PIN
RAS
ATD SAR
ENGINE
RAIN1
VAIN
+
–
CAS
INPUT PIN
CHANNEL
SELECT 0
RAIN2
CHANNEL
SELECT 1
INPUT PIN
RAIN3
.
.
.
INPUT PIN
CHANNEL
SELECT 2
RAINn
CHANNEL
SELECT n
CAIN
Figure 14-10. Resistor and Capacitor Placement
MC9S08GT16A/GT8A Data Sheet, Rev. 1
230
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are
unipolar. The signals must fall within the potential range of VSSAD to VDDAD. The S/H machine is not
required to perform special conversions (i.e., convert VREFL and VREFH).
Proper sampling is dependent on the following factors:
• Analog source impedance (the real portion, RAS – see the electricals characteristics at the end of
this data sheet) — This is the resistive (or real, in the case of high frequencies) portion of the
network driving the analog input voltage VAIN.
• Analog source capacitance (CAS) — This is the filtering capacitance on the analog input, which (if
large enough) may help the analog source network charge the ATD input in the case of high RAS.
• ATD input resistance (RAIN – maximum value 7 kΩ) — This is the internal resistance of the ATD
circuit in the path between the external ATD input and the ATD sample and hold circuit. This
resistance varies with temperature, voltage, and process variation but a worst case number is
necessary to compute worst case sample error.
• ATD input capacitance (CAIN – maximum value 25 pF) — This is the internal capacitance of the
ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process
variation but a worst case number is necessary to compute worst case sample error.
• ATD conversion clock frequency (fATDCLK – maximum value 2 MHz) — This is the frequency of
the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler.
This frequency determines the width of the sample window, which is 14 ATDCLK cycles.
• Input sample frequency (fSAMP – see the electrical characteristics at the end of this data sheet) —
This is the frequency that a given input is sampled.
• Delta-input sample voltage (∆VSAMP) — This is the difference between the current input voltage
(intended for conversion) and the previously sampled voltage (which may be from a different
channel). In non-continuous convert mode, this is assumed to be the greater of (VREFH – VAIN) and
(VAIN – VREFL). In continuous convert mode, 5 LSB should be added to the known difference to
account for leakage and other losses.
• Delta-analog input voltage (∆VAIN) — This is the difference between the current input voltage and
the input voltage during the last conversion on a given channel. This is based on the slew rate of
the input.
In cases where there is no external filtering capacitance, the sampling error is determined by the number
of time constants of charging and the change in input voltage relative to the resolution of the ATD:
# of time constants (τ) = (14 / fATDCLK) / ((RAS + RAIN) * CAIN)
Eqn. 14-1
sampling error in LSB (ES) = 2N * (∆VSAMP / (VREFH - VREFL)) * e−τ
The maximum sampling error (assuming maximum change on the input voltage) will be:
ES = (3.6/3.6) * e–(14/((7 k + 10 k) * 50 p * 2 M)) * 1024 = 0.271 LSB
Eqn. 14-2
In the case where an external filtering capacitance is applied, the sampling error can be reduced based on
the size of the source capacitor (CAS) relative to the analog input capacitance (CAIN). Ignoring the analog
source impedance (RAS), CAS will charge CAIN to a value of:
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
231
Analog-to-Digital Converter (S08ATDV3)
ES = 2N * (∆VSAMP / (VREFH – VREFL)) * (CAIN / (CAIN + CAS))
Eqn. 14-3
In the case of a 0.1 µF CAS, a worst case sampling error of 0.5 LSB is achieved regardless of RAS.
However, in the case of repeated conversions at a rate of fSAMP, RAS must re-charge CAS. This recharge is
continuous and controlled only by RAS (not RAIN), and reduces the overall sampling error to:
ES = 2N * {(∆VAIN / (VREFH – VREFL)) * e−(1 / (fSAMP * RAS * CAS )
+ (∆VSAMP / (VREFH - VREFL)) * Min[(CAIN / (CAIN + CAS)), e−(1 / (fATDCLK * (RAS + RAIN) * CAIN )]}
Eqn. 14-4
This is a worst case sampling error which does not account for RAS recharging the combination of CAS
and CAIN during the sample window. It does illustrate that high values of RAS (>10 kΩ) are possible if a
large CAS is used and sufficient time to recharge CAS is provided between samples. In order to achieve
accuracy specified under the worst case conditions of maximum ∆VSAMP and minimum CAS, RAS must
be less than the maximum value of 10 kΩ. The maximum value of 10 kΩ for RAS is to ensure low sampling
error in the worst case condition of maximum ∆VSAMP and minimum CAS.
14.4.3
Analog Input Multiplexer
The analog input multiplexer selects one of the eight external analog input channels to generate an analog
sample. The analog input multiplexer includes negative stress protection circuitry which prevents
cross-talk between channels when the applied input potentials are within specification. Only analog input
signals within the potential range of VREFL to VREFH (ATD reference potentials) will result in valid ATD
conversions.
14.4.4
ATD Module Accuracy Definitions
Figure 14-11 illustrates an ideal ATD transfer function. The horizontal axis represents the ATD input
voltage in millivolts. The vertical axis the conversion result code. The ATD is specified with the following
figures of merit:
• Number of bits (N) — The number of bits in the digitized output
• Resolution (LSB) — The resolution of the ATD is the step size of the ideal transfer function. This
is also referred to as the ideal code width, or the difference between the transition voltages to a
given code and to the next code. This unit, known as 1LSB, is equal to
1LSB = (VREFH – VREFL) / 2N
•
•
•
Eqn. 14-5
Inherent quantization error (EQ) — This is the error caused by the division of the perfect ideal
straight-line transfer function into the quantized ideal transfer function with 2N steps. This error is
± 1/2 LSB.
Differential non-linearity (DNL) — This is the difference between the current code width and the
ideal code width (1LSB). The current code width is the difference in the transition voltages to the
current code and to the next code. A negative DNL means the transfer function spends less time at
the current code than ideal; a positive DNL, more. The DNL cannot be less than –1.0; a DNL of
greater than 1.0 reduces the effective number of bits by 1.
Integral non-linearity (INL) — This is the difference between the transition voltage to the current
code and the transition to the corresponding code on the adjusted transfer curve. INL is a measure
MC9S08GT16A/GT8A Data Sheet, Rev. 1
232
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
of how straight the line is (how far it deviates from a straight line). The adjusted ideal transition
voltage is:
Eqn. 14-6
Adjusted Ideal Trans. V = (Current Code - 1/2) * ((VREFH + EFS) - (VREFL + EZS))
2N
•
Zero scale error (EZS) — This is the difference between the transition voltage to the first valid code
and the ideal transition to that code. Normally, it is defined as the difference between the actual and
ideal transition to code $001, but in some cases the first transition may be to a higher code. The
ideal transition to any code is:
Eqn. 14-7
Ideal Transition V =
•
(Current Code - 1/2)
2N
*(VREFH – VREFL)
Full scale error (EFS) — This is the difference between the transition voltage to the last valid code
and the ideal transition to that code. Normally, it is defined as the difference between the actual and
ideal transition to code $3FF, but in some cases the last transition may be to a lower code. The ideal
transition to any code is:
Eqn. 14-8
Ideal Transition V =
•
•
(Current Code - 1/2)
2N
*(VREFH – VREFL)
Total unadjusted error (ETU) — This is the difference between the transition voltage to a given code
and the ideal straight-line transfer function. An alternate definition (with the same result) is the
difference between the actual transfer function and the ideal straight-line transfer function. This
measure of error includes inherent quantization error and all forms of circuit error (INL, DNL,
zero-scale, and full-scale) except input leakage error, which is not due to the ATD.
Input leakage error (EIL) — This is the error between the transition voltage to the current code and
the ideal transition to that code that is the result of input leakage across the real portion of the
impedance of the network that drives the analog input. This error is a system-observable error
which is not inherent to the ATD, so it is not added to total error. This error is:
EIL (in V) = input leakage * RAS
Eqn. 14-9
There are two other forms of error which are not specified which can also affect ATD accuracy. These are:
• Sampling error (ES) — The error due to inadequate time to charge the ATD circuitry
• Noise error (EN) — The error due to noise on VAIN, VREFH, or VREFL due to either direct coupling
(noise source capacitively coupled directly on the signal) or power supply (VDDAD, VSSAD, VDD,
and VSS) noise interfering with the ATD’s ability to resolve the input accurately. The error due to
internal sources can be reduced (and specified operation achieved) by operating the ATD
conversion in wait mode and ceasing all IO activity. Reducing the error due to external sources is
dependent on system activity and board layout.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
233
Analog-to-Digital Converter (S08ATDV3)
CODE
D
C
TOTAL UNADJUSTED
ERROR BOUNDARY
B
A
IDEAL TRANSFER
FUNCTION
9
NEGATIVE DNL
(CODE WIDTH <1LSB)
8
IDEAL STRAIGHT-LINE
7
TRANSFER FUNCTION
QUANTIZATION
ERROR
6
INL
(ASSUMES EZS = EFS = 0)
5
1 LSB
4
TOTAL UNADJUSTED
3
ERROR AT THIS CODE
2
POSITIVE DNL
1
(CODE WIDTH >1LSB)
0
1
2
3
4
8
12
LSB
NOTES: Graph is for example only and may not represent actual performance
Figure 14-11. ATD Accuracy Definitions
MC9S08GT16A/GT8A Data Sheet, Rev. 1
234
Freescale Semiconductor
Analog-to-Digital Converter (S08ATDV3)
14.5
Resets
The ATD module is reset on system reset. If the system reset signal is activated, the ATD registers are
initialized back to their reset state and the ATD module is powered down. This occurs as a function of the
register file initialization; the reset definition of the ATDPU bit (power down bit) is zero or disabled.
The MCU places the module back into an initialized state. If the module is performing a conversion, the
current conversion is terminated, the conversion complete flag is cleared, and the SAR register bits are
cleared. Any pending interrupts are also cancelled. Note that the control, test, and status registers are
initialized on reset; the initialized register state is defined in the register description section of this
specification.
Enabling the module (using the ATDPU bit) does not cause the module to reset since the register file is not
initialized. Finally, writing to control register ATDC does not cause the module to reset; the current
conversion will be terminated.
14.6
Interrupts
The ATD module originates interrupt requests and the MCU handles or services these requests. Details on
how the ATD interrupt requests are handled can be found in the resets and interrupts chapter of this data
sheet.
The ATD interrupt function is enabled by setting the ATDIE bit in the ATDSC register. When the ATDIE
bit is set, an interrupt is generated at the end of an ATD conversion and the ATD result registers (ATDRH
and ATDRL) contain the result data generated by the conversion. If the interrupt function is disabled
(ATDIE = 0), then the CCF flag must be polled to determine when a conversion is complete.
The interrupt will remain pending as long as the CCF flag is set. The CCF bit is cleared whenever the ATD
status and control (ATDSC) register is written. The CCF bit is also cleared whenever the ATD result
registers (ATDRH or ATDRL) are read.
Table 14-8. Interrupt Summary
Interrupt
Local
Enable
Description
CCF
ATDIE
Conversion complete
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
235
Analog-to-Digital Converter (S08ATDV3)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
236
Freescale Semiconductor
Chapter 15
Development Support
15.1
Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.
The alternate BDC clock source for MC9S08GT16A/GT8A is the ICGLCLK. See the Chapter 9, “Internal
Clock Generator (S08ICGV4),” for more information about ICGCLK and how to select clock sources.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
237
Development Support
15.1.1
Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• Active background mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from stop or wait modes
• One hardware address breakpoint built into BDC
• Oscillator runs in stop mode, if BDC enabled
• COP watchdog disabled while in active background mode
Features of the ICE system include:
• Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W
• Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
• Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
• Nine trigger modes:
— Basic: A-only, A OR B
— Sequence: A then B
— Full: A AND B data, A AND NOT B data
— Event (store data): Event-only B, A then event-only B
— Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B)
15.2
Background Debug Controller (BDC)
All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit
programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike
debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources.
It does not use any user memory or locations in the memory map and does not share any on-chip
peripherals.
BDC commands are divided into two groups:
• Active background mode commands require that the target MCU is in active background mode (the
user program is not running). Active background mode commands allow the CPU registers to be
read or written, and allow the user to trace one user instruction at a time, or GO to the user program
from active background mode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
238
Freescale Semiconductor
Development Support
•
Non-intrusive commands can be executed at any time even while the user’s program is running.
Non-intrusive commands allow a user to read or write MCU memory locations or access status and
control registers within the background debug controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into
commands for the custom serial interface to the single-wire background debug system. Depending on the
development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port,
or some other type of communications such as a universal serial bus (USB) to communicate between the
host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET,
and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the
on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use
power from the target system to avoid the need for a separate power supply. However, if the pod is powered
separately, it can be connected to a running target system without forcing a target system reset or otherwise
disturbing the running application program.
BKGD 1
2 GND
NO CONNECT 3
4 RESET
NO CONNECT 5
6 VDD
Figure 15-1. BDM Tool Connector
15.2.1
BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for
bidirectional serial communication of active background mode commands and data. During reset, this pin
is used to select between starting in active background mode or starting the user’s application program.
This pin is also used to request a timed sync response pulse to allow a host development tool to determine
the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of
microcontrollers. This protocol assumes the host knows the communication clock rate that is determined
by the target BDC clock rate. All communication is initiated and controlled by the host that drives a
high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit
first (MSB first). For a detailed description of the communications protocol, refer to Section 15.2.2,
“Communication Details.”
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed sync response signal from which the host can
determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
Refer to Section 15.2.2, “Communication Details,” for more detail.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
239
Development Support
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a development system is connected, it can pull both BKGD and
RESET low, release RESET to select active background mode rather than normal operating mode, then
release BKGD. It is not necessary to reset the target MCU to communicate with it through the background
debug interface.
15.2.2
Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data
is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if
512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress
when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU
system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
240
Freescale Semiconductor
Development Support
Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD
pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
EARLIEST START
OF NEXT BIT
TARGET SENSES BIT LEVEL
PERCEIVED START
OF BIT TIME
Figure 15-2. BDC Host-to-Target Serial Bit Timing
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Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
HIGH-IMPEDANCE
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 15-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
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Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
HIGH-IMPEDANCE
SPEEDUP
PULSE
TARGET MCU
DRIVE AND
SPEED-UP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 15-4. BDM Target-to-Host Serial Bit Timing (Logic 0)
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15.2.3
BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 15-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 15-1 to describe the coding structure of the BDC commands.
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDC clock cycles
AAAA = a 16-bit address in the host-to-target direction
RD = 8 bits of read data in the target-to-host direction
WD = 8 bits of write data in the host-to-target direction
RD16 = 16 bits of read data in the target-to-host direction
WD16 = 16 bits of write data in the host-to-target direction
SS = the contents of BDCSCR in the target-to-host direction (STATUS)
CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
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Table 15-1. BDC Command Summary
Command
Mnemonic
1
Active BDM/
Non-intrusive
Coding
Structure
Description
SYNC
Non-intrusive
n/a1
Request a timed reference pulse to determine
target BDC communication speed
ACK_ENABLE
Non-intrusive
D5/d
Enable acknowledge protocol. Refer to
Freescale document order no. HCS08RMv1/D.
ACK_DISABLE
Non-intrusive
D6/d
Disable acknowledge protocol. Refer to
Freescale document order no. HCS08RMv1/D.
BACKGROUND
Non-intrusive
90/d
Enter active background mode if enabled
(ignore if ENBDM bit equals 0)
READ_STATUS
Non-intrusive
E4/SS
Read BDC status from BDCSCR
WRITE_CONTROL
Non-intrusive
C4/CC
Write BDC controls in BDCSCR
READ_BYTE
Non-intrusive
E0/AAAA/d/RD
Read a byte from target memory
READ_BYTE_WS
Non-intrusive
E1/AAAA/d/SS/RD
Read a byte and report status
READ_LAST
Non-intrusive
E8/SS/RD
Re-read byte from address just read and
report status
WRITE_BYTE
Non-intrusive
C0/AAAA/WD/d
Write a byte to target memory
WRITE_BYTE_WS
Non-intrusive
C1/AAAA/WD/d/SS
Write a byte and report status
READ_BKPT
Non-intrusive
E2/RBKP
Read BDCBKPT breakpoint register
WRITE_BKPT
Non-intrusive
C2/WBKP
Write BDCBKPT breakpoint register
GO
Active BDM
08/d
Go to execute the user application program
starting at the address currently in the PC
TRACE1
Active BDM
10/d
Trace 1 user instruction at the address in the
PC, then return to active background mode
TAGGO
Active BDM
18/d
Same as GO but enable external tagging
(HCS08 devices have no external tagging pin)
READ_A
Active BDM
68/d/RD
Read accumulator (A)
READ_CCR
Active BDM
69/d/RD
Read condition code register (CCR)
READ_PC
Active BDM
6B/d/RD16
Read program counter (PC)
READ_HX
Active BDM
6C/d/RD16
Read H and X register pair (H:X)
READ_SP
Active BDM
6F/d/RD16
Read stack pointer (SP)
READ_NEXT
Active BDM
70/d/RD
Increment H:X by one then read memory byte
located at H:X
READ_NEXT_WS
Active BDM
71/d/SS/RD
Increment H:X by one then read memory byte
located at H:X. Report status and data.
WRITE_A
Active BDM
48/WD/d
Write accumulator (A)
WRITE_CCR
Active BDM
49/WD/d
Write condition code register (CCR)
WRITE_PC
Active BDM
4B/WD16/d
Write program counter (PC)
WRITE_HX
Active BDM
4C/WD16/d
Write H and X register pair (H:X)
WRITE_SP
Active BDM
4F/WD16/d
Write stack pointer (SP)
WRITE_NEXT
Active BDM
50/WD/d
Increment H:X by one, then write memory byte
located at H:X
WRITE_NEXT_WS
Active BDM
51/WD/d/SS
Increment H:X by one, then write memory byte
located at H:X. Also report status.
The SYNC command is a special operation that does not have a command code.
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The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct communications speed to use for BDC communications until after it has analyzed the response to
the SYNC command.
To issue a SYNC command, the host:
• Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest
clock is normally the reference oscillator/64 or the self-clocked rate/64.)
• Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically
one cycle of the fastest clock in the system.)
• Removes all drive to the BKGD pin so it reverts to high impedance
• Monitors the BKGD pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would
ever occur during normal BDC communications):
• Waits for BKGD to return to a logic high
• Delays 16 cycles to allow the host to stop driving the high speedup pulse
• Drives BKGD low for 128 BDC clock cycles
• Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
• Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
15.2.4
BDC Hardware Breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a
16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged
breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction
boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction
opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather
than executing that instruction if and when it reaches the end of the instruction queue. This implies that
tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can
be set at any address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to
enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the
breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC
breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select
forced (FTS = 1) or tagged (FTS = 0) type breakpoints.
The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more
flexible than the simple breakpoint in the BDC module.
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15.3
On-Chip Debug System (DBG)
Because HCS08 devices do not have external address and data buses, the most important functions of an
in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage
FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture
bus information and what information to capture. The system relies on the single-wire background debug
system to access debug control registers and to read results out of the eight stage FIFO.
The debug module includes control and status registers that are accessible in the user’s memory map.
These registers are located in the high register space to avoid using valuable direct page memory space.
Most of the debug module’s functions are used during development, and user programs rarely access any
of the control and status registers for the debug module. The one exception is that the debug system can
provide the means to implement a form of ROM patching. This topic is discussed in greater detail in
Section 15.3.6, “Hardware Breakpoints.”
15.3.1
Comparators A and B
Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking
circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry
optionally allows you to specify that a trigger will occur only if the opcode at the specified address is
actually executed as opposed to only being read from memory into the instruction queue. The comparators
are also capable of magnitude comparisons to support the inside range and outside range trigger modes.
Comparators are disabled temporarily during all BDC accesses.
The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the
CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data
bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an
additional purpose, in full address plus data comparisons they are used to decide which of these buses to
use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s
write data bus is used. Otherwise, the CPU’s read data bus is used.
The currently selected trigger mode determines what the debugger logic does when a comparator detects
a qualified match condition. A match can cause:
• Generation of a breakpoint to the CPU
• Storage of data bus values into the FIFO
• Starting to store change-of-flow addresses into the FIFO (begin type trace)
• Stopping the storage of change-of-flow addresses into the FIFO (end type trace)
15.3.2
Bus Capture Information and FIFO Operation
The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the
debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would
read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of
words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by
writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and
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the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry
in the FIFO.
In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In
these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading
DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information
is available at the FIFO data port. In the event-only trigger modes (see Section 15.3.5, “Trigger Modes”),
8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is
not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO
is shifted so the next data value is available through the FIFO data port at DBGFL.
In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU
addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow
address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the
FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-flow,
it will be saved as the last change-of-flow entry for that debug run.
The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not
armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be
saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by
reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded
because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic
reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger
can develop a profile of executed instruction addresses.
15.3.3
Change-of-Flow Information
To minimize the amount of information stored in the FIFO, only information related to instructions that
cause a change to the normal sequential execution of instructions is stored. With knowledge of the source
and object code program stored in the target system, an external debugger system can reconstruct the path
of execution through many instructions from the change-of-flow information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was true), the source
address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are
not conditional, these events do not cause change-of-flow information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the
destination address, so the debug system stores the run-time destination address for any indirect JMP or
JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow
information.
15.3.4
Tag vs. Force Breakpoints and Triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue,
but not taking any other action until and unless that instruction is actually executed by the CPU. This
distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt
causes some instructions that have been fetched into the instruction queue to be thrown away without being
executed.
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A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint
request. The usual action in response to a breakpoint is to go to active background mode rather than
continuing to the next instruction in the user application program.
The tag vs. force terminology is used in two contexts within the debug module. The first context refers to
breakpoint requests from the debug module to the CPU. The second refers to match signals from the
comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is
entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU
will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background
mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is
set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the
debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare
address is actually executed. There is separate opcode tracking logic for each comparator so more than one
compare event can be tracked through the instruction queue at a time.
15.3.5
Trigger Modes
The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register
selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator
must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in
DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace),
or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected
(end trigger).
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and
clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets
full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually
by writing a 0 to ARM or DBGEN in DBGC.
In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only
trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type
traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons
because opcode tags would only apply to opcode fetches that are always read cycles. It would also be
unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally
known at a particular address.
The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger.
Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the
corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with
optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines
whether the CPU request will be a tag request or a force request.
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A-Only — Trigger when the address matches the value in comparator A
A OR B — Trigger when the address matches either the value in comparator A or the value in
comparator B
A Then B — Trigger when the address matches the value in comparator B but only after the address for
another cycle matched the value in comparator A. There can be any number of cycles after the A match
and before the B match.
A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally)
must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte
of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of
comparator B is not used.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low
half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within
the same bus cycle to cause a trigger.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
Event-Only B (Store Data) — Trigger events occur each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the
FIFO becomes full.
A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger
event occurs each time the address matches the value in comparator B. Trigger events cause the data to be
captured into the FIFO. The debug run ends when the FIFO becomes full.
Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value
in comparator A and less than or equal to the value in comparator B at the same time.
Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than
the value in comparator A or greater than the value in comparator B.
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15.3.6
Hardware Breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions
described in Section 15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a
force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction
queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to
finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command
through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background
mode.
15.4
Register Definition
This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute
address assignments for all DBG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
15.4.1
BDC Registers and Control Bits
The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
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15.4.1.1
BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
7
R
6
5
4
3
BKPTEN
FTS
CLKSW
BDMACT
ENBDM
2
1
0
WS
WSF
DVF
W
Normal
Reset
0
0
0
0
0
0
0
0
Reset in
Active BDM:
1
1
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 15-5. BDC Status and Control Register (BDCSCR)
Table 15-2. BDCSCR Register Field Descriptions
Field
Description
7
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
6
BDMACT
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
4
FTS
3
CLKSW
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
clock source.
0 Alternate BDC clock source
1 MCU bus clock
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Table 15-2. BDCSCR Register Field Descriptions (continued)
Field
Description
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active
background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active)
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
0 Memory access did not conflict with a wait or stop instruction
1 Memory access command failed because the CPU entered wait or stop mode
0
DVF
Data Valid Failure Status — This status bit is not used in the MC9S08GT16A/GT8A because it does not have
any slow access memory.
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access
15.4.1.2
BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is
not accessible to user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. For additional information about setup and use of the hardware breakpoint logic in
the BDC, refer to Section 15.2.4, “BDC Hardware Breakpoint.”
15.4.2
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background mode command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
253
Development Support
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BDFR1
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1
BDFR is writable only through serial background mode debug commands, not from user programs.
Figure 15-6. System Background Debug Force Reset Register (SBDFR)
Table 15-3. SBDFR Register Field Description
Field
Description
0
BDFR
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
15.4.3
DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
15.4.3.1
Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
15.4.3.2
Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
15.4.3.3
Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
15.4.3.4
Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
254
Freescale Semiconductor
Development Support
15.4.3.5
Debug FIFO High Register (DBGFH)
This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have
no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of
each FIFO word, so this register is not used and will read 0x00.
Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the
FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the
next word of information.
15.4.3.6
Debug FIFO Low Register (DBGFL)
This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have
no meaning or effect.
Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug
module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each
FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get
successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case.
Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled
or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can
interfere with normal sequencing of reads from the FIFO.
Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode
to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host
software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will
return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO
eight times without using the data to prime the sequence and then begin using the data to get a delayed
picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL
(while the FIFO is not armed) is the address of the most-recently fetched opcode.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
255
Development Support
15.4.3.7
Debug Control Register (DBGC)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
0
0
0
0
0
0
0
0
R
W
Reset
Figure 15-7. Debug Control Register (DBGC)
Table 15-4. DBGC Register Field Descriptions
Field
Description
7
DBGEN
Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
0 DBG disabled
1 DBG enabled
6
ARM
Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used
to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually
stopped by writing 0 to ARM or to DBGEN.
0 Debugger not armed
1 Debugger armed
5
TAG
Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
BRKEN = 0, this bit has no meaning or effect.
0 CPU breaks requested as force type requests
1 CPU breaks requested as tag type requests
4
BRKEN
Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU
break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a
begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of
CPU break requests.
0 CPU break requests not enabled
1 Triggers cause a break request to the CPU
3
RWA
R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0 Comparator A can only match on a write cycle
1 Comparator A can only match on a read cycle
2
RWAEN
Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
0 R/W is not used in comparison A
1 R/W is used in comparison A
1
RWB
R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0 Comparator B can match only on a write cycle
1 Comparator B can match only on a read cycle
0
RWBEN
Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
0 R/W is not used in comparison B
1 R/W is used in comparison B
MC9S08GT16A/GT8A Data Sheet, Rev. 1
256
Freescale Semiconductor
Development Support
15.4.3.8
Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
7
6
TRGSEL
BEGIN
0
0
R
5
4
0
0
3
2
1
0
TRG3
TRG2
TRG1
TRG0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 15-8. Debug Trigger Register (DBGT)
Table 15-5. DBGT Register Field Descriptions
Field
Description
7
TRGSEL
Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode
tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match
address is actually executed.
0 Trigger on access to compare address (force)
1 Trigger if opcode at compare address is executed (tag)
6
BEGIN
Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until
a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are
assumed to be begin traces.
0 Data stored in FIFO until trigger (end trace)
1 Trigger initiates data storage (begin trace)
3:0
TRG[3:0]
Select Trigger Mode — Selects one of nine triggering modes, as described below.
0000 A-only
0001 A OR B
0010 A Then B
0011 Event-only B (store data)
0100 A then event-only B (store data)
0101 A AND B data (full mode)
0110 A AND NOT B data (full mode)
0111 Inside range: A ≤ address ≤ B
1000 Outside range: address < A or address > B
1001 – 1111 (No trigger)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
257
Development Support
15.4.3.9
Debug Status Register (DBGS)
This is a read-only status register.
R
7
6
5
4
3
2
1
0
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 15-9. Debug Status Register (DBGS)
Table 15-6. DBGS Register Field Descriptions
Field
Description
7
AF
Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A
condition was met since arming.
0 Comparator A has not matched
1 Comparator A match
6
BF
Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B
condition was met since arming.
0 Comparator B has not matched
1 Comparator B match
5
ARMF
Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1
to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A
debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A
debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC.
0 Debugger not armed
1 Debugger armed
3:0
CNT[3:0]
FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid
data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the FIFO.
0000 Number of valid words in FIFO = No valid data
0001 Number of valid words in FIFO = 1
0010 Number of valid words in FIFO = 2
0011 Number of valid words in FIFO = 3
0100 Number of valid words in FIFO = 4
0101 Number of valid words in FIFO = 5
0110 Number of valid words in FIFO = 6
0111 Number of valid words in FIFO = 7
1000 Number of valid words in FIFO = 8
MC9S08GT16A/GT8A Data Sheet, Rev. 1
258
Freescale Semiconductor
Appendix A
Electrical Characteristics
A.1
Introduction
This section contains electrical and timing specifications.
A.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table A-1. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
A.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table A-2 may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
259
Electrical Characteristics
Table A-2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
Tstg
–55 to 150
°C
TJ
150
°C
Storage temperature range
Maximum junction temperature
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
A.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the
MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
260
Freescale Semiconductor
Electrical Characteristics
Table A-3. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Symbol
Value
Unit
TA
TL to TH
–40 to 125
°C
Thermal resistance
1s board type
48-pin QFN
84
θJA1, 2
44-pin QFP
72
42-pin SDIP
62
32-pin QFN
99
°C/W
Thermal resistance
2s2p board type
48-pin QFN
26
θJA1,2
44-pin QFP
54
42-pin SDIP
51
32-pin QFN
33
°C/W
1
Junction temperature is a function of die size, on-chip power dissipation, package
thermal resistance, mounting site (board) temperature, ambient temperature, airflow,
power dissipation of other components on the board, and board thermal resistance.
2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Single layer board is designed per JEDEC JESD51-3.
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. A-1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. A-2
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations 1 and 2 iteratively for any value of TA.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
261
Electrical Characteristics
A.5
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification
Table A-4. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Charge Device
Model
Latch-Up
A.6
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
—
3
Series Resistance
R1
0
Ω
Storage Capacitance
C
200
pF
Number of Pulse per pin
—
3
Series Resistance
R1
Ω
Storage Capacitance
C
pF
Number of Pulse per pin
—
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table A-5. MCU Operating Conditions
Characteristic
Supply Voltage
Min
Typ
Max
Unit
1.8
—
3.6
V
–40
–40
—
—
125
85
°C
Temperature
M
C
MC9S08GT16A/GT8A Data Sheet, Rev. 1
262
Freescale Semiconductor
Electrical Characteristics
Table A-6. DC Characteristics (Sheet 1 of 2)
(Temperature Range = –40 to 125°C Ambient)
C
P
P
P
P
P
Parameter
Symbol
Min
Minimum RAM retention supply voltage applied to
VDD
VRAM
1.02
Low-voltage detection threshold — high range
(VDD falling)
(VDD rising)
VLVDH
Low-voltage detection threshold — low range
(VDD falling)
(VDD rising)
VLVDL
Low-voltage warning threshold — high range
(VDD falling)
(VDD rising)
VLVWH
Typical1
Max
Unit
—
V
V
2.08
2.16
2.1
2.19
2.2
2.27
1.80
1.88
1.82
1.90
1.91
1.99
2.35
2.35
2.40
2.40
2.5
2.5
V
V
V
Low-voltage warning threshold — low range
(VDD falling)
(VDD rising)
VLVWL
2.08
2.16
2.1
2.19
2.2
2.27
Power on reset (POR) re-arm voltage(2)
Mode = stop
Mode = run and Wait
VRearm
0.20
0.50
0.30
0.80
0.40
1.2
V
P
Input high voltage (VDD > 2.3 V) (all digital inputs)
VIH
0.70 × VDD
—
P
Input high voltage (1.8 V ≤ VDD ≤ 2.3 V)
(all digital inputs)
VIH
0.85 × VDD
—
P
Input low voltage (VDD > 2.3 V) (all digital inputs)
VIL
—
0.35 × VDD
V
P
Input low voltage (1.8 V ≤ VDD ≤ 2.3 V)
(all digital inputs)
VIL
—
0.30 × VDD
V
Y
Input hysteresis (all digital inputs)
Vhys
0.06 × VDD
—
V
P
Input leakage current (per pin)
VIn = VDD or VSS, all input only pins
|IIn|
—
0.025
1.0
µA
P
High impedance (off-state) leakage current (per pin)
VIn = VDD or VSS, all input/output
|IOZ|
—
0.025
1.0
µA
P
Internal pullup and pulldown resistors3
(all port pins and IRQ)
RPU
17.5
52.5
p
Internal pulldown resistors (Port A4–A7 and IRQ)
RPD
17.5
52.5
kΩ
P
Output high voltage (VDD ≥ 1.8 V)
IOH = –2 mA (ports A, B, D, E, and G)
VDD – 0.5
—
V
P
D
Output high voltage (port C)
IOH = –10 mA (VDD ≥ 2.7 V)
IOH = –6 mA (VDD ≥ 2.3 V)
IOH = –3 mA (VDD ≥ 1.8 V)
Maximum total IOH for all port pins
V
V
kΩ
VOH
VDD – 0.5
|IOHT|
—
—
—
—
60
mA
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
263
Electrical Characteristics
Table A-6. DC Characteristics (Sheet 2 of 2)
(Temperature Range = –40 to 125°C Ambient)
C
D
D
D
C
2
3
4
5
6
7
Symbol
Typical1
Max
Unit
—
0.5
V
—
—
—
0.5
0.5
0.5
60
mA
Min
Output low voltage (VDD ≥ 1.8 V)
IOL = 2.0 mA (ports A, B, D, E, and G)
Output low voltage (port C)
IOL = 10.0 mA (VDD ≥ 2.7 V)
IOL = 6 mA (VDD ≥ 2.3 V)
IOL = 3 mA (VDD ≥ 1.8 V)
VOL
Maximum total IOL for all port pins
IOLT
—
dc injection current 4, 5, 6, 7
DC Injection Current A, B, C, D
Single pin limit
VIN > VDD
VIN < VSS
Total MCU limit, includes sum of all stressed pins
VIN > VDD
VIN < VSS
|IIC|
0
0
-
2
–0.2
mA
mA
0
0
-
25
–5
mA
mA
Input capacitance (all non-supply pins)(2)
CIn
7
pF
—
Typicals are measured at 25°C.
This parameter is characterized and not tested on each device.
Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if clock rate is very low which (would reduce overall power consumption).
All functional non-supply pins are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
IRQ does not have a clamp diode to VDD. Do not drive IRQ above VDD.
PULLUP RESISTOR TYPICALS
PULL-UP RESISTOR (kΩ)
40
85°C
25°C
–40°C
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
3.6
PULLDOWN RESISTANCE (kΩ)
1
Parameter
PULLDOWN RESISTOR TYPICALS
40
85°C
25°C
–40°C
35
30
25
20
1.8
2.3
2.8
VDD (V)
3.3
3.6
Figure A-1. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
264
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
85°C
25°C
–40°C
0.8
85°C
25°C
–40°C
0.3
VOL (V)
VOL (V)
0.6
0.4
0.2
IOL = 10 mA
IOL = 6 mA
0.1
0.2
IOL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure A-2. Typical Low-Side Driver (Sink) Characteristics (Port C)
TYPICAL VOL VS IOL AT VDD = 3.0 V
1.2
85°C
25°C
–40°C
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
0.6
0.4
0.1
85°C, IOL = 2 mA
25°C, IOL = 2 mA
–40°C, IOL = 2 mA
0.05
0.2
0
0
0
5
10
IOL (mA)
15
1
20
2
3
4
VDD (V)
Figure A-3. Typical Low-Side Driver (Sink) Characteristics (Ports A, B, D, E, and G)
TYPICAL VDD – VOH VS VDD AT SPEC IOH
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
0.8
85°C
25°C
–40°C
0.6
0.4
0.2
0
0
85°C
25°C
–40°C
0.3
VDD – VOH (V)
VDD – VOH (V)
0.4
–5
–10
–15
–20
IOH (mA)
–25
–30
0.2
IOH = –10 mA
IOH = –6 mA
0.1
IOH = –3 mA
0
1
2
3
4
VDD (V)
Figure A-4. Typical High-Side Driver (Source) Characteristics (Port C)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
265
Electrical Characteristics
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
1.2
85°C
25°C
–40°C
85°C, IOH = 2 mA
25°C, IOH = 2 mA
–40°C, IOH = 2 mA
0.2
VDD – VOH (V)
1
VDD – VOH (V)
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.25
0.8
0.6
0.4
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA)
–15
–20
1
2
VDD (V)
3
4
Figure A-5. Typical High-Side (Source) Characteristics (Ports A, B, D, E, and G)
A.7
Supply Current Characteristics
Table A-7. Supply Current Characteristics
Parameter
Symbol
3
Run supply current measured at
(CPU clock = 2 MHz, fBus = 1 MHz)
RIDD
Run supply current (3) measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
RIDD
VDD (V)
Typical1
Max2
Temp. (°C)
3
0.8 mA
1.3 mA4
125
2
0.66 mA
1.0 mA(4)
125
3
4.3 mA
7.0 mA5
125
2
3.3 mA
4.5 mA(4)
125
25 nA
0.6 µA(4)
1.8 µA(4)
4.0 µA(5)
13 µA(5)
55
70
85
125
20 nA
500 nA(4)
1.5 µA(4)
3.3 µA(4)
10 µA(4)
55
70
85
125
550 nA
3.0 µA(4)
5.5 µA(4)
11 µA(5)
20 µA(5)
55
70
85
125
400 nA
2.4 µA(4)
5.0 µA(4)
9.5 µA(4)
17 µA(4)
55
70
85
125
3
Stop1 mode supply current
S1IDD
2
3
Stop2 mode supply current
S2IDD
2
MC9S08GT16A/GT8A Data Sheet, Rev. 1
266
Freescale Semiconductor
Electrical Characteristics
Table A-7. Supply Current Characteristics (continued)
Typical1
Max2
Temp. (°C)
675 nA
4.3 µA(4)
7.2 µA(4)
17.0 µA(5)
45 µA(5)
55
70
85
125
2
500 nA
3.5 µA(4)
6.2 µA(4)
15.0 µA(4)
40 µA(4)
55
70
85
125
3
300 nA
2
300 nA
LVI adder to stop3
(LVDSE = LVDE = 1)
3
70 µA
2
60 µA
Adder to stop3 for oscillator enabled7
(OSCSTEN =1)
3
5 µA
2
5 µA
Adder for loss-of-clock enabled
(LOCD=0)
3
9 µA
2
9 µA
Adder for high gain oscillator enabled
(HGO=1)
3
28 µA
2
2 µA
Parameter
Symbol
VDD (V)
3
Stop3 mode supply current
RTI adder to stop2 or stop36
1
2
3
4
5
6
7
S3IDD
Typicals are measured at 25°C. See Table A-6 through Table A-9 for typical curves across voltage/temperature.
Values given here are preliminary estimates prior to completing characterization.
All modules except ATD active, ICG configured for FBE, and does not include any dc loads on port pins
Values are characterized but not tested on every part.
Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode.
Wait mode typical is 560 µA at 3 V and 422 µA at 2V with fBus = 1 MHz.
Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0), clock monitor
disabled (LOCD = 1).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
267
Electrical Characteristics
14
= FEI mode, ATD off, 20 MHz
12
= FBE mode, ATD off, 20 MHz
= FEI mode, ATD off, 16 MHz
10
8
IDD (mA)
= FBE mode, all modules enabled, 8 MHz
= FEI mode, ATD off, 8 MHz
6
4
2
= FEI mode, ATD off, 1 MHz
= FBE mode, ATD off, 1 MHz
0
0
3.6
0
3.5
0
3.4
0
3.3
0
3.2
0
3.1
0
3.0
0
2.9
0
2.8
0
2.7
0
2.6
0
2.5
0
2.4
0
2.3
0
2.2
0
2.1
0
2.0
0
1.9
0
1.8
VDD (Vdc)
Figure A-6. Typical Run IDD for FBE and FEE Modes, IDD vs VDD
MC9S08GT16A/GT8A Data Sheet, Rev. 1
268
Freescale Semiconductor
Electrical Characteristics
1.4
1.2
1
IDD (µA)
0.8
25°C
75°C
85°C
105°C
125°C
0.6
0.4
0.2
0
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (Vdc)
Figure A-7. Typical Stop1 IDD
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
269
Electrical Characteristics
Figure A-8. Typical Stop 2 IDD
MC9S08GT16A/GT8A Data Sheet, Rev. 1
270
Freescale Semiconductor
Electrical Characteristics
Figure A-9. Typical Stop3 IDD
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
271
Electrical Characteristics
A.8
ATD Characteristics
Table A-8. ATD Electrical Characteristics (Operating)
No.
Characteristic
1
ATD supply1
2
ATD supply current
Condition
Symbol
Min
Typ
Max
Unit
VDDAD
1.80
—
3.6
V
Enabled
IDDADrun
—
0.7
1.2
mA
Disabled
(ATDPU = 0
or STOP)
IDDADstop
—
0.02
0.6
µA
3
Differential supply voltage
VDD–VDDAD
|VDDLT|
—
—
100
mV
4
Differential ground voltage
VSS–VSSAD
|VSDLT|
—
—
100
mV
5
Reference potential, low
|VREFL|
—
—
VSSAD
V
VREFH
2.08
—
VDDAD
V
VDDAD
—
VDDAD
Reference potential, high
2.08V < VDDAD < 3.6V
1.80V < VDDAD < 2.08V
6
7
1
2
Reference supply current
(VREFH to VREFL)
µA
Enabled
IREF
—
200
300
Disabled
(ATDPU = 0
or STOP)
IREF
—
<0.01
0.02
VINDC
VSSAD – 0.3
—
VDDAD + 0.3
V
Analog input voltage2
VDDAD must be at same potential as VDD.
Maximum electrical operating range, not valid conversion range.
Table A-9. ATD Timing/Performance Characteristics1
No.
1
Characteristic
ATD conversion clock
frequency
2
Conversion cycles
(continuous convert)2
3
Conversion time
(Including sample time)
Condition
Symbol
Min
Typ
Max
Unit
2.08V < VDDAD < 3.6V
fATDCLK
0.5
—
2.0
MHz
0.5
—
1.0
CC
28
28
<30
ATDCLK
cycles
Tconv
14.0
—
60.0
µs
28.0
—
60.0
tADS
—
14
—
ATDCLK
cycles
—
10
kΩ
VREFH
V
1.80V < VDDAD < 2.08V
2.08V < VDDAD < 3.6V
1.80V < VDDAD < 2.08V
4
ATD sample time
tADS
5
Source impedance at input3
RAS
—
6
Analog Input Voltage4
VAIN
VREFL
MC9S08GT16A/GT8A Data Sheet, Rev. 1
272
Freescale Semiconductor
Electrical Characteristics
Table A-9. ATD Timing/Performance Characteristics1 (continued)
No.
Characteristic
Ideal resolution (1 LSB)5
7
Condition
Symbol
Min
Typ
Max
Unit
2.08V < VDDAD < 3.6V
RES
2.031
—
3.516
mV
1.758
—
2.031
1.80V < VDDAD < 2.08V
8
Differential non-linearity6
1.80V < VDDAD < 3.6V
DNL
—
+0.5
+1.0
LSB
9
Integral non-linearity7
1.80 V < VDDAD < 3.6V
INL
—
+0.5
+1.0
LSB
10
Zero-scale error8
1.80V < VDDAD < 3.6V
EZS
—
+0.4
+1.0
LSB
11
Full-scale error9
1.80V < VDDAD < 3.6V
EFS
—
+0.4
+1.0
LSB
12
Input leakage error 10
1.80V < VDDAD < 3.6V
EIL
—
+0.05
+5
LSB
13
Total unadjusted
error11
1.80V < VDDAD < 3.6V
ETU
—
+1.1
+2.5
LSB
14
Input resistance
RAIN
—
5
7
kΩ
15
Input capacitance
CAIN
—
—
25
pF
1
All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching) and that
adequate low-pass filtering is present on analog input pins (filter with 0.01 µF to 0.1 µF capacitor between analog input and VREFL).
Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which will vary based
on board layout and the type and magnitude of the activity.
2 This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single conversions
or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting the conversion and
setting the CCF flag. The total conversion time in Bus Cycles for a conversion is:
SC Bus Cycles = ((PRS+1)*2) * (28+1) + 2
CC Bus Cycles = ((PRS+1)*2) * (28)
3 R
is
the
real
portion
of
the
impedance
of
the
network
driving
the
analog input pin. Values greater than this amount may not fully
AS
charge the input circuitry of the ATD resulting in accuracy error.
4 Analog input must be between V
REFL and VREFH for valid conversion. Values greater than VREFH will convert to $3FF less the full
scale error (EFS).
5 The resolution is the ideal step size or 1LSB = (V
REFH–VREFL)/1024
6 Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current code width
is the difference in the transition voltages to and from the current code.
7 Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition voltage
for the current code. The adjusted ideal transition voltage is (Current Code–1/2)*(1/((VREFH+EFS)–(VREFL+EZS))).
8 Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal
transition voltage to a given code is (Code–1/2)*(1/(VREFH–VREFL)).
9 Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal
transition voltage to a given code is (Code–1/2)*(1/(VREFH–VREFL)).
10 Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin.
Reducing the impedance of the network reduces this error.
11 Total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfer
function. This measure of error includes inherent quantization error (1/2LSB) and circuit error (differential, integral, zero-scale, and
full-scale) error. The specified value of ET assumes zero EIL (no leakage or zero real source impedance).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
273
Electrical Characteristics
A.9
Internal Clock Generation Module Characteristics
ICG
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator (See Note)
C2
NOTE:
Use fundamental mode crystal or ceramic resonator only.
Table A-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient)
Characteristic
Load capacitors
Feedback resistor
Low range (32k to 100 kHz)
High range (1M – 16 MHz)
Series resistor
Low range
Low Gain (HGO = 0)
High Gain (HGO = 1)
High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
1
2
Symbol
Min
Typ1
Max
C1
C2
See Note 2
RF
10
1
RS
Unit
MΩ
MΩ
—
—
0
100
—
—
—
0
—
—
—
—
0
10
20
—
—
—
kΩ
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
See crystal or resonator manufacturer’s recommendation.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
274
Freescale Semiconductor
Electrical Characteristics
A.9.1
ICG Frequency Specifications
Table A-11. ICG Frequency Specifications
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient)
Characteristic
Symbol
Min
Typical
Max
Unit
flo
32
—
100
kHz
fhi_byp
fhi_eng
flp_byp
flp_eng
1
2
1
2
—
—
—
—
16
10
8
8
MHz
MHz
MHz
MHz
flo
fhi_eng
32
2
—
—
100
10
kHz
MHz
fExtal
0
—
40
MHz
fICGIRCLK
182.25
243
303.75
kHz
tdc
40
—
60
%
fICGOUT
fExtal (min)
flo (min)
fExtal (max)
fICGDCLKmax
(max)
MHz
Minimum DCO clock (ICGDCLK) frequency
fICGDCLKmin
8
Maximum DCO clock (ICGDCLK) frequency
fICGDCLKmax
Oscillator crystal or resonator (REFS = 1)
(Fundamental mode crystal or ceramic resonator)
Low range
High range
High Gain, FBE (HGO=1,CLKS = 10)
High Gain, FEE (HGO=1,CLKS = 11)
Low Power, FBE (HGO=0, CLKS=10)
Low Power, FEE (HGO=0, CLKS=11)
Input clock frequency (CLKS = 11, REFS = 0)
Low range
High range
Input clock frequency (CLKS = 10, REFS = 0)
Internal reference frequency (untrimmed)
Duty cycle of input clock
4
(REFS = 0)
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
—
40
MHz
fICGDCLKmax
MHz
10.5
MHz
5
50
25
500
kHz
fLOD
0.5
1.5
MHz
t
CSTL
t
CSTH
—
—
—
—
ms
FLL lock time 4, 6
Low range
High range
tLockl
tLockh
—
—
5
5
ms
FLL frequency unlock range
nUnlock
–4*N
4*N
counts
nLock
–2*N
2*N
counts
CJitter
—
0.2
% fICG
ACCint
—
—
± 0.5
±0.5
±2
±2
%
—
—
1
VDD
—
—
Self-clock mode (ICGOUT) frequency 1
—
MHz
fSelf
fICGDCLKmin
fSelf_reset
5.5
Loss of reference frequency 2
Low range
High range
fLOR
Loss of DCO frequency 3
Self-clock mode reset (ICGOUT) frequency
Crystal start-up time
Low range
High range
8
4, 5
FLL frequency lock range
4, 7 measured
at fICGOUT Max
ICGOUT period jitter,
Long term jitter (averaged over 2 ms interval)
Internal oscillator deviation from trimmed frequency8
VDD = 1.8 – 3.6 V, (constant temperature)
VDD = 3.0 V ±10%, –40° C to 125° C
Oscillator Amplitude (peak-to-peak)
HGO = 0
HGO = 1
Voscamp
430
4
V
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
275
Electrical Characteristics
1
2
3
4
5
6
7
8
Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked
mode if it is not in the desired range.
Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external
mode (if an external reference exists) if it is not in the desired range.
This parameter is characterized before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external
modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter
percentage for a given interval.
See Figure A-10
0.1
80
–60
–40
–20
0
20
40
100
120
60
PERCENT (%)
–0.1
–0.2
–0.3
–0.4
2V
–0.5
3V
–0.6
TEMPERATURE (°C)
Figure A-10. Internal Oscillator Deviation from Trimmed Frequency
A.10
AC Characteristics
This section describes ac timing characteristics for each peripheral system. For detailed information about
how clocks for the bus are generated, see Chapter 9, “Internal Clock Generator (S08ICGV4).”
MC9S08GT16A/GT8A Data Sheet, Rev. 1
276
Freescale Semiconductor
Electrical Characteristics
A.10.1
Control Timing
Table A-12. Control Timing
Parameter
Symbol
Min
Typical
Max
Unit
fBus
0
0
—
20
8
MHz
tRTI
750
1150
1550
µs
External reset pulse width1
textrst
1.5 x
fSelf_reset
—
ns
Reset low drive2
trstdrv
34 x
fSelf_reset
—
ns
Active background debug mode latch setup time
tMSSU
25
—
ns
Active background debug mode latch hold time
tMSH
25
—
ns
IRQ pulse width3
tILIH
1.5 x tcyc
—
ns
tRise, tFall
—
—
Bus frequency (tcyc = 1/fBus)
VDD ≥ 2.1 V
VDD < 2.1 V
Real-time interrupt internal oscillator period
Port rise and fall time (load = 50 pF)4
Slew rate control disabled
Slew rate control enabled
3
30
ns
1
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
2
When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of fSelf_reset and then samples the level
on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 125°C.
1600
1400
1200
1000
= +3 Sigma
= Mean
= –3 Sigma
Period (µs)
800
600
400
200
0
–40
–20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure A-11. Typical RTI Clock Period vs. Temperature
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
277
Electrical Characteristics
textrst
RESET PIN
Figure A-12. Reset Timing
BKGD/MS
RESET
tMSH
tMSSU
Figure A-13. Active Background Debug Mode Latch Timing
tILIH
IRQ
Figure A-14. IRQ Timing
A.10.2
Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table A-13. TPM Input Timing
Function
Symbol
Min
Max
Unit
External clock frequency
fTPMext
dc
fBus/4
MHz
External clock period
tTPMext
4
—
tcyc
External clock high time
tclkh
1.5
—
tcyc
External clock low time
tclkl
1.5
—
tcyc
tICPW
1.5
—
tcyc
Input capture pulse width
MC9S08GT16A/GT8A Data Sheet, Rev. 1
278
Freescale Semiconductor
Electrical Characteristics
tText
tclkh
TPMxCHn
tclkl
Figure A-15. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure A-16. Timer Input Capture Pulse
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
279
Electrical Characteristics
A.10.3
SPI Timing
Table A-14 and Figure A-17 through Figure A-20 describe the timing requirements for the SPI system.
Table A-14. SPI Timing
No.
Function
Operating frequency
Master
Slave
Symbol
Min
Max
Unit
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
1
SCK period
Master
Slave
tSCK
2
4
2048
—
tcyc
tcyc
2
Enable lead time
Master
Slave
tLead
1/2
1
—
—
tSCK
tcyc
3
Enable lag time
Master
Slave
tLag
1/2
1
—
—
tSCK
tcyc
4
Clock (SCK) high or low time
Master
Slave
tWSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
5
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
6
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
Slave access time
ta
—
1
tcyc
8
Slave MISO disable time
tdis
—
1
tcyc
9
Data valid (after SCK edge)
Master
Slave
tv
—
—
25
25
ns
ns
tHO
0
0
—
—
ns
ns
tRI
tRO
—
—
tcyc – 25
25
ns
ns
tFI
tFO
—
—
tcyc – 25
25
ns
ns
10
Data hold time (outputs)
Master
Slave
11
Rise time
Input
Output
12
Fall time
Input
Output
MC9S08GT16A/GT8A Data Sheet, Rev. 1
280
Freescale Semiconductor
Electrical Characteristics
SS1
(OUTPUT)
1
2
SCK
(CPOL = 0)
(OUTPUT)
11
3
4
4
12
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
9
LSB IN
9
MOSI
(OUTPUT)
MSB OUT2
10
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-17. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
LSB IN
10
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-18. SPI Master Timing (CPHA = 1)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
281
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SCK
(CPOL = 0)
(INPUT)
2
4
4
SCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
9
SLAVE
MSB OUT
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
6
5
MOSI
(INPUT)
10
10
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure A-19. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
12
11
11
12
SCK
(CPOL = 0)
(INPUT)
4
4
SCK
(CPOL = 1)
(INPUT)
9
MISO
(OUTPUT)
SEE
NOTE
7
MOSI
(INPUT)
10
SLAVE
MSB OUT
5
BIT 6 . . . 1
8
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure A-20. SPI Slave Timing (CPHA = 1)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
282
Freescale Semiconductor
Electrical Characteristics
A.11
FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see Chapter 4, “Memory.”
Table A-15. FLASH Characteristics
Characteristic
Symbol
Min
Supply voltage for program/erase
T ≤ 85°C
T > 85°C
Vprog/erase
Supply voltage for read operation
0 < fBus < 8 MHz
0 < fBus < 20 MHz
Typical
Max
Unit
1.8
2.1
3.6
3.6
V
V
VRead
1.8
2.08
3.6
3.6
V
Internal FCLK frequency1
fFCLK
150
200
kHz
Internal FCLK period (1/FCLK)
tFcyc
5
6.67
µs
Byte program time (random location)(2)
tprog
9
tFcyc
Byte program time (burst mode)(2)
tBurst
4
tFcyc
Page erase time2
tPage
4000
tFcyc
Mass erase time(2)
tMass
20,000
tFcyc
Byte program current3
RIDDBP
—
4
—
mA
Page erase current3
RIDDPE
—
6
—
mA
—
—
cycles
100,000
100
—
years
Program/erase endurance4
TL to TH = –40°C to +125°C
T = 25°C
Data retention5
10,000
tD_ret
15
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
3 The program and erase currents are additional to the standard run I . These values were measured at room
DD
temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional
information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin
EB619/D, Typical Endurance for Nonvolatile Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature
and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor
defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for
Nonvolatile Memory.
2
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
283
Electrical Characteristics
MC9S08GT16A/GT8A Data Sheet, Rev. 1
284
Freescale Semiconductor
Appendix B
Ordering Information and Mechanical Drawings
B.1
Ordering Information
This section contains ordering information for MC9S08GT16A and MC9S08GT8A devices.
Table 15-7. Devices in the MC9S08GT16A/GT8A Series
1
B.1.1
Device
FLASH
RAM
Packages1
MC9S08GT16A
16K
2K
MC9S08GT8A
8K
1K
48 QFN
44 QFP
42 SDIP
32 QFN
See Table B-1 for package information.
Device Numbering Scheme
MC 9 S08 GT16A C XX E
RoHS compliance indicator (E = yes)
Package designator (see Table B-1)
Status
(MC = Fully Qualified)
Memory
(9 = FLASH-based)
Core
Temperature range (C = –40°C to +85°C)
(M = –40°C to +125°C)
Family/memory size
B.2
Mechanical Drawings
The following pages are mechanical specifications for MC9S08GT16A/GT8A package options. See
Table B-1 for the document number for each package type.
Table B-1. Package Information
Pin Count
Type
Designator
Document No.
48
QFN
Quad flat no-lead
FD
98ARH99048A
44
QFP
Quad flat package
FB
98ASB42839B
42
PSDIP
32
QFN
Plastic shrink dual inline package
Quad flat no-lead
B
98ASB42767B
FC
98ARH99035A
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
285
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