Dallas DS1643P-70 Nonvolatile timekeeping ram Datasheet

DS1643/DS1643P
Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identically to the
static RAM. These registers are resident in the
eight top RAM locations.
Totally nonvolatile with over 10 years of
operation in the absence of power
Access times of 70 ns and 100 ns
BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
Power-fail write protection allows for ±10%
VCC power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
DS1643 only (DIP Module)
– Standard JEDEC byte-wide 8K x 8 RAM
pinout
DS1643P only (PowerCap Module Board)
– Surface mountable package for direct
connection to PowerCap containing
battery and crystal
– Replaceable battery (PowerCap)
– Power-fail output
– Pin-for-pin compatible with other
densities of DS164XP Timekeeping RAM
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ1
1
2
3
4
5
6
7
8
9
10
11
12
DQ2
13
16
DQ4
GND
14
15
DQ3
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ5
28-PIN Encapsulated Package
(700-mil Extended)
NC
NC
NC
PFO
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
NC
NC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-PIN PowerCap Module Board
(USES DS9034PCX PowerCap)
ORDERING INFORMATION
DS1643-XXX
28-pin DIP module
-70
70 ns access
-100
100 ns access
*DS1643P-XXX
34-pin PowerCap Module Board
-70
70 ns access
-100
100 ns access
*DS9034PCX
PowerCap
(Required; must be ordered
separately)
1 of 14
022101
DS1643/DS1643P
PIN DESCRIPTION
A0-A12
CE
CE2
OE
WE
VCC
- Address Input
- Chip Enable
- Chip Enable 2 (DIP Module
only)
- Output Enable
- Write Enable
- +5 Volts
GND
DQ0-DQ7
NC
RST
X1, X2
VBAT
- Ground
- Data Input/Output
- No Connect
- Power-on Reset Output
(PowerCap Module board only)
- Crystal Connection
- Battery Connection
DESCRIPTION
The DS1643 is a 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) which are
both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to
any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid
access of incorrect data that can occur during clock update cycles. The double-buffered system also
prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1643 also contains its own power-fail circuitry which deselects the device when the VCC supply is in
an out of tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1643 is available in two packages: 28-pin DIP module and 34-pin PowerCap module. The 28-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1643P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, the seventh most significant bit in the control
register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was issued.
However, the internal clock registers of the double-buffered system continue to update so that the clock
accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously
after the clock status is reset. Updating is within a second after the read bit is written to 0.
2 of 14
DS1643/DS1643P
BLOCK DIAGRAM DS1643 Figure 1
DS1643 TRUTH TABLE Table 1
VCC
5 VOLTS
± 10%
<4.5 VOLTS
>VBAT
<VBAT
OE
WE
VIH
X
VIL
VIL
VIL
X
CE2
X
VIL
VIH
VIH
VIH
X
X
X
X
VIL
VIH
X
X
X
X
CE
X
X
VIL
VIH
VIH
X
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DQ
HIGH Z
HIGH Z
DATA IN
DATA OUT
HIGH Z
HIGH Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
X
DESELECT
HIGH Z
DATA RETENTION
MODE
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, CE2 high, and address for seconds register remain valid and stable).
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
3 of 14
DS1643/DS1643P
DS1643 REGISTER MAP - BANK1 Table 2
ADDRES
S
B7
1FFF
1FFE
X
1FFD
X
1FFC
X
1FFB
X
1FFA
X
1FF9
OSC
1FF8
W
OSC = STOP BIT
W
= WRITE BIT
B6
X
X
FT
X
R
B5
X
X
X
DATA
B4
B3
B2
X
X
X
X
X
R = READ BIT
X = UNUSED
B1
X
FUNCTION
B0
YEAR
00-99
MONTH
01-12
DATE
01-31
DAY
01-07
HOUR
00-23
MINUTES
00-59
SECONDS
00-59
X
CONTROL
A
FT = FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA , the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1643 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-on reset output signal ( RST ) will
be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
4 of 14
DS1643/DS1643P
level. The RST signal is an open drain output and requires a pull up. Except for the RST , all control, data,
and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1643 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1643 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
Ds1643 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
5 of 14
DS1643/DS1643P
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C
-40°C to +85°C
J-STD-020A Specification (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Logic 1 Voltage All Inputs
Logic 0 Voltage All Inputs
SYMBOL
VIH
VIL
MIN
2.2
-0.3
SYMBOL
ICC
ICC1
MIN
ICC2
IIL
IOL
VOH
TYP
6 of 14
UNITS
V
V
NOTES
TYP
15
1
MAX
50
3
UNITS
mA
mA
NOTES
2, 3
2, 3
1
3
mA
2, 3
+1
+1
µA
µA
-1
-1
2.4
1
VOL
VPF
MAX
VCC+0.3
0.8
(0°C to=70°C; VCC = 5.0V ±=10%)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Active Supply Current
TTL Standby Current
( CE =VIH, CE2=VIL)
CMOS Standby Current
( CE =VCC-0.2V,
CE2=GND+0.2V)
Input Leakage Current (any input)
Output Leakage Current (any output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
(0°C to 70°C)
0.4
4.25
4.37
4.50
1
V
1
DS1643/DS1643P
READ CYCLE, AC CHARACTERISTICS
PARAMETER
Read Cycle Time
Address Access Time
CE and CE2 to DQ Low-Z
CE Access Time
CE2 Access Time
CE and CE2 Data Off Time
OE to DQ Low-Z
OE Access Time
OE Data Off Time
Output Hold from Address
SYMBOL
tRC
tAA
tCEL
tCEA
tCE2A
tCEZ
tOEL
tOEA
tOEZ
tOH
(0°C to 70°C; VCC = 5.0V ±=10%)
70 ns access
MIN MAX
70
70
5
70
80
25
5
35
25
5
100 ns access
MIN MAX
100
100
5
100
105
35
5
55
35
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
4
4
4
4
4
4
4
4
4
READ CYCLE TIMING DIAGRAM
WRITE CYCLE, AC CHARACTERISTICS
PARAMETER
Write Cycle Time
Address Setup Time
WE Pulse Width
CE Pulse Width
CE2 Pulse Width
Data Setup Time
Data Hold Time
Address Hold Time
WE Data Off Time
Write Recovery Time
SYMBOL
tWC
tAS
tWEW
tCEW
tCE2W
tDS
tDH
tAH
tWEZ
tWR
(0°C to 70°C; VCC = 5.0V ±=10%)
70 ns access
MIN MAX
70
0
50
60
65
30
0
5
25
5
7 of 14
100 ns access
MIN MAX
100
0
70
75
85
40
0
5
35
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
4
4
4
4
4
4
4
4
4
DS1643/DS1643P
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CE , CE2 CONTROLLED
8 of 14
DS1643/DS1643P
POWER-UP/DOWN AC CHARACTERISTICS
PARAMETER
CE or WE at VIH, CE2 at VIL, Before
Power-down
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Fall Time: VPF(MIN) to VBAT
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-up Recover Time
Expected Data Retention Time
(Oscillator On)
SYMBOL
tPD
MIN
0
tF
tFB
tR
tREC
tDR
300
10
0
(0°C to 70°C; VCC = 5.0V ±=10%)
TYP
MAX
35
10
UNITS
µs
µs
µs
µs
ms
years
NOTES
5, 6
POWER-UP/POWER-DOWN TIMING
CAPACITANCE
PARAMETER
Capacitance on all pins
Capacitance on all output pins
(tA = 25°C)
SYMBOL
CIN
CO
9 of 14
MIN
TYP
MAX
7
10
UNITS
pF
pF
NOTES
DS1643/DS1643P
AC TEST CONDITIONS
Output Load:
100 pF + 1TTL Gate
Input Pulse Levels:
0.0 to 3.0 Volts
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1. Voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. The CE2 control signal functions exactly the same as the CE signal except that the logic levels for
active and inactive levels are opposite.
5. Data retention time is at 25°C.
6. Each DS1643 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting
from the time power is first applied by the user.
7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the
part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove
solder.
10 of 14
DS1643/DS1643P
DS1643 28-PIN PACKAGE
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
11 of 14
28-PIN
MIN
MAX
1.470
1.490
37.34
37.85
0.675
0.740
17.75
18.80
0.315
0.335
8.51
9.02
0.075
0.105
1.91
2.67
0.015
0.030
0.38
0.76
0.140
0.180
3.56
4.57
0.090
0.110
2.29
2.79
0.590
0.630
14.99
16.00
0.010
0.018
0.25
0.45
0.015
0.025
0.43
0.58
DS1643/DS1643P
DS1643P
PKG
DIM
A
B
C
D
E
F
G
MIN
0.920
0.980
0.052
0.048
0.015
0.025
INCHES
NOM
0.925
0.985
0.055
0.050
0.020
0.027
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
NOTE:
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up (“live-bug”).
Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds.
To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux,
heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
12 of 14
DS1643/DS1643P
DS1643P WITH DS9034PCX ATTACHED
PKG
DIM
A
B
C
D
E
F
G
13 of 14
MIN
0.920
0.955
0.240
0.052
0.048
0.015
0.020
INCHES
NOM
0.925
0.960
0.245
0.055
0.050
0.020
0.025
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
DS1643/DS1643P
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
A
B
C
D
E
14 of 14
MIN
-
INCHES
NOM
1.050
0.826
0.050
0.030
0.112
MAX
-