TI1 HPA01085DBVR Low-noise, high psrr, rf, 200-ma low-dropout linear regulators in nanostar wafer chip scale and sot-23 Datasheet

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TPS793
SLVS348L – JULY 2001 – REVISED MAY 2015
TPS793 Low-Noise, High PSRR, RF, 200-mA Low-Dropout Linear Regulators in
NanoStar™ Wafer Chip Scale and SOT-23
1 Features
3 Description
•
The TPS793 family of low-dropout (LDO) low-power
linear voltage regulators features high power-supply
rejection ratio (PSRR), ultralow-noise, fast start-up,
and excellent line and load transient responses in
NanoStar™ wafer chip scale and SOT23 packages.
NanoStar packaging gives an ultrasmall footprint as
well as an ultralow profile and package weight,
making these devices ideal for portable applications
such as handsets and PDAs. Each device in the
family is stable, with a small, 2.2-μF ceramic
capacitor on the output. The TPS793 family uses an
advanced, proprietary BiCMOS fabrication process to
yield extremely low dropout voltages (for example,
112 mV at 200 mA, TPS79330). Each device
achieves fast start-up times (approximately 50 μs with
a 0.001-μF bypass capacitor) while consuming very
low quiescent current (170 μA typical). Moreover,
when the device is placed in standby mode, the
supply current is reduced to less than 1 μA. The
TPS79328 exhibits approximately 32 μVRMS of output
voltage noise at 2.8-V output with a 0.1-μF bypass
capacitor. Applications with analog components that
are noise-sensitive, such as portable RF electronics,
benefit from the high PSRR and low-noise features
as well as the fast response time.
1
•
•
•
•
•
•
•
•
200-mA RF Low-Dropout Regulator
With Enable
Available in Fixed-Voltage Versions from 1.8 V to
4.75 V and Adjustable (1.22 V to 5.5 V)
High PSRR (70 dB at 10 kHz)
Low Noise (32 μVRMS, TPS79328)
Fast Start-Up Time (50 μs)
Stable With a 2.2-μF Ceramic Capacitor
Excellent Load and Line Transient Response
Very Low Dropout Voltage (112 mV at 200 mA,
TPS79330)
5- and 6-Pin SOT23 (DBV) and NanoStar Wafer
Chip Scale (YZQ) Packages
2 Applications
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Cellular and Cordless Telephones
Bluetooth®, Wireless LAN
Handheld Organizers, PDAs
Device Information(1)
PART NUMBER
TPS793
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
SOT-23 (5)
2.90 mm × 1.60 mm
DSBGA (5)
1.35 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
VIN
VIN
IN
OUT
Ripple Rejection vs Frequency
VOUT
100
VOUT
VIN = 3.8 V
COUT = 2.2 mF
CNR = 0.1 mF
90
TPS79328
EN
GND
NR
10 mF
0.01 mF
Ripple Rejection (dB)
80
0.1 mF
IOUT = 200 mA
70
60
50
IOUT = 10 mA
40
30
20
10
0
10
100
1k
10 k
100 k
1M
10 M
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS793
SLVS348L – JULY 2001 – REVISED MAY 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
8.3 Do's and Don'ts ....................................................... 17
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Power Dissipation ................................................. 18
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision K (October 2007) to Revision L
Page
•
Changed title of data sheet ................................................................................................................................................... 1
•
Deleted references to YEQ package throughout document (package is obsolete) .............................................................. 1
•
Changed fourth bullet of Features list to low noise ................................................................................................................ 1
•
Changed front-page figure ..................................................................................................................................................... 1
•
Changed Absolute Maximum Ratings condition statement ................................................................................................... 4
•
Added Pin Configurations and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 4
•
Deleted Dissipation Ratings table; added Thermal Information table ................................................................................... 5
•
Deleted TJ = 25°C test condition from PSRR specification measurements because of redundancy .................................... 6
•
Added condition statement to Typical Characteristics ........................................................................................................... 7
•
Changed Figure 23; changed capacitor notation to CFF in figure and related table ............................................................ 14
•
Changed Figure 24; changed capacitor notation to CFF in figure, changed 2.2µF capacitor value to 10µF, and
changed device name .......................................................................................................................................................... 15
2
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23 Fixed Voltage Version
Top View
IN
1
GND
2
EN
3
5
DBV Package
6-Pin SOT-23 Adjustable Voltage Version
Top View
OUT
IN
1
6
OUT
GND
2
5
FB
EN
3
4
NR
NR
4
YZQ Package
5-Pin DSBGA
Top View
IN
C3
A3
EN
C1
B2
A1
OUT
NR
GND
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DBV
YZQ
EN
3
A3
I
Enable pin. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts
the regulator into shutdown mode. EN can be connected to IN if not used.
FB
5
—
I
Feedback pin. This terminal is the feedback input pin for the adjustable device. Fixed voltage
versions in the DBV package do not have this pin.
GND
2
A1
—
Regulator ground.
IN
1
C3
I
Input to the device.
NR
4
B2
—
Noise Reduction pin. Connecting an external capacitor to this pin filters noise generated by
the internal bandgap. This configuration improves power-supply rejection and reduces output
noise.
OUT
6
C1
O
Output of the regulator.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted). All voltages are with respect to GND. (1)
Voltage
Current
MIN
MAX
UNIT
Input, VIN
–0.3
6
V
Enable, VEN
–0.3
6
V
Output, VOUT
–0.3
6
V
Peak output, IOUT(max)
Internally limited
Output short-circuit duration
Total power dissipation
Indefinite
Continuous, PD(tot)
Junction, TJ
Temperature
See Thermal Information
DBV package
–40
150
°C
YZQ package
–40
125
°C
–65
150
°C
Storage, Tstg
(1)
A
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
VIN
Input supply voltage range
VEN
Enable supply voltage range
VOUT
Output voltage range
IOUT
Output current
TJ
Operating junction temperature
CIN
Input capacitor
0.1
1
µF
COUT
Output capacitor
2.2 (1)
10
µF
CNR
Noise reduction capacitor
0
10
nF
CFF
Feed-forward capacitor
R2
Lower feedback resistor
(1)
4
2.7
5.5
V
0
VIN
V
VFB
5
V
0
200
–40
125
mA
°C
15
pF
30.1
kΩ
If CFF is not used or VOUT(nom) < 1.8 V, the minimum recommended COUT = 4.7 µF.
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6.4 Thermal Information
TPS79301
THERMAL METRIC (1)
DBV (SOT-23)
YZQ (DSBGA)
6 PINS
5 PINS
UNIT
178.5
°C/W
RθJA
Junction-to-ambient thermal resistance
225.1
RθJC(top)
Junction-to-case (top) thermal resistance
78.4
1.4
°C/W
RθJB
Junction-to-board thermal resistance
54.7
62.1
°C/W
ψJT
Junction-to-top characterization parameter
3.3
0.9
°C/W
ψJB
Junction-to-board characterization parameter
53.8
62.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
VIN
Input voltage range (1)
IOUT
Continuous output current
VFB
Internal reference (TPS79301)
1.201
TPS79301
VFB
Output voltage
range
VOUT
0
TPS79318
0 µA < IOUT < 200 mA, 2.8 V < VIN < 5.5 V
TPS79325
TPS79328
1.225
MAX
V
200
mA
1.250
0 µA < IOUT < 200 mA, 3.5 V < VIN < 5.5 V
2.45
2.5
2.55
0 µA < IOUT < 200 mA, 3.8 V < VIN < 5.5 V
2.744
2.8
2.856
TPS793285
0 µA < IOUT < 200 mA, 3.85 V < VIN < 5.5 V
2.793
2.85
2.907
TPS79330
0 µA < IOUT < 200 mA, 4 V < VIN < 5.5 V
2.94
3
3.06
TPS79333
0 µA < IOUT < 200 mA, 4.3 V < VIN < 5.5 V
3.234
3.3
3.366
TPS793475
0 µA < IOUT < 200 mA, 5.25 V < VIN < 5.5 V
4.655
4.75
4.845
0.05
0.12
Line regulation
VOUT + 1 V < VIN ≤ 5.5 V
Load regulation
0 µA < IOUT < 200 mA, TJ = 25°C
TPS79328
V
5.5 – VDO
1.8
ΔVOUT(ΔIOUT)
UNIT
5.5
1.764
ΔVOUT(ΔVIN)
VDO
TYP
2.7
1.836
5
%/V
mV
IOUT = 200 mA
120
200
Dropout
TPS793285
voltage (2)
TPS79330
(VIN = VOUT(nom) –
TPS79333
0.1 V)
IOUT = 200 mA
120
200
IOUT = 200 mA
112
200
IOUT = 200 mA
12
180
TPS793475
IOUT = 200 mA
77
125
mV
ICL
Output current limit
VOUT = 0 V
600
mA
IGND
Ground pin current
0 µA < IOUT < 200 mA
170
220
µA
ISHUTDOWN
Shutdown current (3)
VEN = 0 V, 2.7 V < VIN < 5.5 V
0.07
1
µA
IFB
FB pin current
VFB = 1.8 V
1
µA
Power-supply
rejection ratio
PSRR
Output noise
voltage
Vn
tSTR
Startup time
TPS79328
TPS79328
TPS79328
285
V
f = 100 Hz, IOUT = 10 mA
70
f = 100 Hz, IOUT = 200 mA
68
f = 10 kHz, IOUT = 200 mA
70
f = 100 kHz, IOUT = 200 mA
43
BW = 200 Hz to
100 kHz,
IOUT = 200 mA
RL = 14 Ω,
COUT = 1 µF
CNR = 0.001 μF
55
CNR = 0.0047 μF
36
CNR = 0.01 μF
33
CNR = 0.1 μF
32
CNR = 0.001 μF
50
CNR = 0.0047 μF
dB
µVRMS
70
CNR = 0.01 μF
µs
100
VEN(high)
High-level enable input voltage
2.7 V < VIN < 5.5 V
1.7
VIN
V
VEN(low)
Low-level enable input voltage
2.7 V < VIN < 5.5 V
0
0.7
V
IEN
EN pin current
VEN = 0 V
–1
1
µA
2.25
2.65
UVLO
(1)
(2)
(3)
6
Threshold, VCC rising
Hysteresis
100
V
mV
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
Dropout is not measured for the TPS79318 and TPS79325 because minimum VIN = 2.7 V.
For adjustable versions, this parameter applies only after VIN is applied; then VEN transitions high to low.
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6.6 Typical Characteristics
Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
2.805
2.805
VIN = 3.8 V
COUT = 10 mF
TJ = 25°C
2.804
2.803
2.800
IOUT = 1 mA
2.802
VOUT (V)
VOUT (V)
2.795
2.801
2.800
2.799
2.790
IOUT = 200 mA
2.785
2.798
2.797
2.780
VIN = 3.8 V
COUT = 10 mF
2.796
2.795
2.775
0
50
100
150
−40 −25 −10 5
200
20 35 50 65 80 95 110 125
IOUT (mA)
TJ (°C)
Figure 1. TPS79328 Output Voltage vs Output Current
Figure 2. TPS79328 Output Voltage vs Junction
Temperature
0.30
VIN = 3.8 V
COUT = 10 mF
Output Spectral Noise Density (mV/√Hz)
250
IOUT = 1 mA
IGND (mA)
200
IOUT = 200 mA
150
100
50
0
−40 −25 −10 5
VIN = 3.8 V
COUT = 2.2 mF
CNR = 0.1 mF
0.25
0.20
0.15
IOUT = 1 mA
0.10
IOUT = 200 mA
0.05
0
TJ (°C)
100
1k
10 k
Frequency (Hz)
Figure 3. TPS79328 Ground Current vs Junction
Temperature
Figure 4. TPS79328 Output Spectral Noise Density vs
Frequency
20 35 50 65 80 95 110 125
1.6
Output Spectral Noise Density (mV/√Hz)
Output Spectral Noise Density (mV/√Hz)
0.30
VIN = 3.8 V
COUT = 10 mF
CNR = 0.1 mF
0.25
0.20
IOUT = 1 mA
0.15
0.10
IOUT = 200 mA
0.05
0
100
100 k
1k
10 k
1.2
CNR = 0.001 mF
1.0
CNR = 0.0047 mF
0.8
CNR = 0.01 mF
0.6
CNR = 0.1 mF
0.4
0.2
0
100
100 k
VIN = 3.8 V
IOUT = 200 mA
COUT = 10 mF
1.4
1k
10 k
100 k
Frequency (Hz)
Frequency (Hz)
Figure 5. TPS79328 Output Spectral Noise Density vs
Frequency
Figure 6. TPS79328 Output Spectral Noise Density vs
Frequency
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Typical Characteristics (continued)
Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
2.5
60
50
2.0
40
1.5
ZO (W)
RMS, Output Noise (VRMS)
VIN = 3.8 V
COUT = 10 mF
TJ = 25°C
VOUT = 2.8 V
IOUT = 200 mA
COUT = 10 mF
30
1.0
IOUT = 100 mA
20
0.5
10
BW = 100 Hz to 100 kHz
0
0.001
0.01
CNR (mF)
0
10
0.1
100
180
90
10 M
IOUT = 200 mA
80
Ripple Rejection (dB)
140
120
IOUT = 200 mA
100
80
60
40
70
60
50
40
IOUT = 10 mA
30
20
VIN = 3.8 V
COUT = 10 mF
CNR = 0.01 mF
IOUT = 10 mA
20
10
0
−40 −25 −10 5
0
20 35 50 65 80 95 110 125
10
100
TJ (°C)
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Figure 9. TPS79328 Dropout Voltage vs Junction
Temperature
Figure 10. TPS79328 Ripple Rejection vs Frequency
100
100
VIN = 3.8 V
COUT = 2.2 mF
CNR = 0.01 mF
90
80
VIN = 3.8 V
COUT = 2.2 mF
CNR = 0.1 mF
90
80
IOUT = 200 mA
Ripple Rejection (dB)
Ripple Rejection (dB)
1M
100
VIN = 2.7 V
COUT = 10 mF
160
70
60
50
IOUT = 10 mA
40
30
IOUT = 200 mA
70
60
50
IOUT = 10 mA
40
30
20
20
10
10
0
0
10
100
1k
10 k
100 k
1M
10 M
10
Frequency (Hz)
100
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Figure 11. TPS79328 Ripple Rejection vs Frequency
8
1k
10 k 100 k
Frequency (Hz)
Figure 8. Output Impedance vs Frequency
Figure 7. Root Mean Square Output Noise vs CNR
VDO (mV)
IOUT = 1 mA
Figure 12. TPS79328 Ripple Rejection vs Frequency
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Typical Characteristics (continued)
Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
VIN = 3.8 V
VOUT = 2.8 V
IOUT = 200 mA
COUT = 2.2 mF
TJ = 25°C
2
0
CNR = 0.001 mF
4.8
VOUT (mV)
VEN (V)
4
3.8
20
VIN (mV)
3
VOUT (V)
IOUT = 200 mA
COUT = 2.2 mF
CNR = 0.01 mF
2
CNR = 0.0047 mF
1
dv
0.4 V
= ms
dt
0
-20
CNR = 0.01 mF
0
0
20 40
60 80 100 120 140 160 180 200
0
10
20
30 40
Time (ms)
Figure 13. TPS79328 Output Voltage, Enable Voltage vs
Time (Start-Up)
0
−20
500 mV/div
DVOUT (mV)
90 100
VOUT = 3 V
RL = 15 W
−40
di
0.02A
= ms
dt
300
IOUT (mA)
70 80
Figure 14. TPS79328 Line Transient Response
VIN = 3.8 V
COUT = 10 mF
20
50 60
Time (ms)
VIN
VOUT
200
1mA
100
0
0
50 100 150 200 250 300 350 400 450 500
1s/div
Time (ms)
Figure 15. TPS79328 Load Transient Response
Figure 16. Power-Up and Power-Down
250
200
TJ = 125°C
200
150
VDO (mV)
VDO (mV)
TJ = 125°C
150
TJ = 25°C
100
TJ = −55°C
50
TJ = 25°C
100
50
TJ = −40°C
IOUT = 200 mA
0
0
0
20 40 60 80 100 120 140 160 180 200
2.5
3.0
3.5
4.0
4.5
5.0
IOUT (mA)
VIN (V)
Figure 17. Dropout Voltage vs Output Current
Figure 18. TPS79301 Dropout Voltage vs Input Voltage
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Typical Characteristics (continued)
Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
100
COUT = 2.2 mF
VIN = 5.5 V, VOUT ≥ 1.5 V
TJ = −40°C to 125°C
ESR, Equivalent Series Resistance (W)
ESR, Equivalent Series Resistance (W)
100
10
Region of Instability
1
0.1
Region of Stability
10
Region of Instability
1
0.1
Region of Stability
0.01
0.01
0
10
COUT = 10 mF
VIN = 5.5 V
TJ = −40°C to 125°C
0.02
0.04
0.06
0.08
0
0.20
0.02
0.04
0.06
0.08
0.20
IOUT (A)
IOUT (A)
Figure 19. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
Figure 20. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
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7 Detailed Description
7.1 Overview
The TPS793 family of LDO regulators has been optimized for use in noise-sensitive battery-operated equipment.
The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current
(170 μA typically), and enable-input to reduce supply currents to less than 1 μA when the regulator is turned off.
7.2 Functional Block Diagrams
IN
OUT
UVLO
2.45 V
59 k
Current
Sense
ILIM
GND
R1
SHUTDOWN
_
+
FB
EN
R2
UVLO
Thermal
Shutdown
IN
External to
the Device
QuickStart
Bandgap
Reference
1.22 V
250 kW
Vref
NR
Figure 21. TPS79301 Block Diagram (Adjustable Version)
IN
OUT
UVLO
2.45 V
Current
Sense
GND
SHUTDOWN
ILIM
_
EN
R1
+
UVLO
R2
Thermal
Shutdown
R2 = 40 kW
QuickStart
IN
Bandgap
Reference
1.22 V
250 kW
Vref
NR
Figure 22. TPS793 Block Diagram (Fixed Version)
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS793 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage. This circuit ensures that the device does not exhibit any unpredictable
behavior when the supply voltage is lower than the operational range of the internal circuitry, VIN(min).
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (1.7 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.7 V. If shutdown capability is not required, connect EN
to IN.
7.3.3 Foldback Current Limit
The TPS793 features internal current limiting and thermal protection. During normal operation, the TPS793 limits
output current to approximately 400 mA. When current limiting engages, the output voltage scales back linearly
until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care
should be taken not to exceed the power dissipation ratings of the package or the absolute maximum voltage
ratings of the device.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, protecting the device from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin
of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions.
The TPS793 internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heatsinking. Continuously running the TPS793 into thermal shutdown degrades
device reliability.
7.3.5 Reverse Current Operation
The TPS793 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting to
5% of the rated output current is recommended.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage is greater than VEN(min).
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
• The input voltage is less than UVLOfalling.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN(high)
IOUT < ILIM
TJ < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
VIN < UVLOfalling
VEN < VEN(low)
—
TJ > 165°C (1)
Disabled mode
(any true condition disables the
device)
(1)
Approximate value for thermal shutdown.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS793 family of LDO regulators has been optimized for use in noise-sensitive battery-operated equipment.
The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current
(170 μA typically), and enable-input to reduce supply currents to less than 1 μA when the regulator is turned off.
8.1.1 Adjustable Operation
The output voltage of the TPS79301 adjustable regulator is programmed using an external resistor divider as
shown in Figure 23. The output voltage is calculated using Equation 1:
æ
R ö
VOUT = VREF ´ ç 1 + 1 ÷
è R2 ø
where:
•
VREF = 1.2246 V typ (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 50-μA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistors values can cause
accuracy issues and other problems. The recommended design procedure is to choose R2 = 30.1 kΩ to set the
divider current at 50 μA, CFF = 15 pF for stability, and then calculate R1 using Equation 2:
æV
ö
R1 = ç OUT - 1÷ ´ R2
è VREF
ø
(2)
To improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed
between OUT and FB. For output voltages less than 1.8 V, the value of this capacitor should be 100 pF. For
output voltages greater than 1.8 V, the approximate value of this capacitor can be calculated as shown in
Equation 3:
-7
CFF =
(3 ´ 10 ) ´ (R1 + R2)
(R1 ´ R2)
(3)
The suggested value of this capacitor for several resistor ratios is shown in the table in Figure 23. If this
capacitor is not used (such as in a unity-gain configuration) or if an output voltage less than 1.8 V is chosen, then
the minimum recommended output capacitor is 4.7 μF instead of 2.2 μF.
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
IN
1m F
OUT
TPS79301
EN
NR
GND
0.01mF
VOUT
R1
CFF
2.2mF
FB
OUTPUT
VOLTAGE
R1
R2
short
open
0pF
2.5V
31.6kW
30.1kW
22pF
3.3V
51kW
30.1kW
15pF
3.6V
59kW
30.1kW
15pF
1.22V
R2
CFF
Figure 23. TPS79301 Adjustable LDO Regulator Programming
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8.2 Typical Application
A typical application circuit is shown in Figure 24.
VIN
VIN
IN
OUT
VOUT
VOUT
TPS79328
EN
0.1 mF
GND
NR
10 mF
0.01 mF
Figure 24. Typical Application Circuit
8.2.1 Design Requirements
Table 2 lists the design requirements.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.2 V to 3 V (Lithium Ion battery)
Output voltage
1.8 V, ±1%
DC output current
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
8.2.2 Detailed Design Procedure
Pick the desired output voltage option. An input capacitor of 0.1 µF is used as the battery is connected to the
input through a via and a short 10-mil (0.01-in) trace. An output capacitor of 10 µF is used to provide optimal
response time for the load transient. Verify that the maximum junction temperature is not exceed by referring to
Figure 30.
8.2.2.1 Capacitor Recommendations
Low equivalent series resistance (ESR) capacitors should be used for the input, output, noise reduction, and
bypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more
stable characteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5R
capacitors are more cost-effective and are available in higher values.
8.2.2.2 Input and Output Capacitor Requirements
A 0.1-μF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS793, is required for stability and improves transient response, noise rejection, and ripple rejection. A highervalue input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the device is
located several inches from the power source.
Like most low-dropout regulators, the TPS793 requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance is 2.2 μF. Any 2.2-μF or larger
ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load
current is not expected to exceed 100 mA, a 1.0-μF ceramic capacitor can be used. If a feed-forward capacitor is
not used (such as in a unity-gain configuration) or if an output voltage less than 1.8 V is chosen, then the
minimum recommended output capacitor is 4.7 μF instead of 2.2 μF. Table 3 lists the recommended output
capacitor sizes for several common configurations.
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Table 3. Output Capacitor Sizing
Condition
COUT (µF)
VOUT < 1.8 V or CFF = 0 nF
4.7
VOUT > 1.8 V, IOUT > 100 mA
2.2
VOUT > 1.8 V, IOUT < 100 mA
1
8.2.2.3 Noise Reduction and Feed-Forward Capacitor Requirements
The internal voltage reference is a key source of noise in an LDO regulator. The TPS793 has an NR pin which is
connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the
voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR
drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor should be no more than 0.1 μF to ensure that it is fully charged
during the quickstart time provided by the internal switch shown in the Functional Block Diagrams.
As an example, the TPS79328 exhibits only 32 μVRMS of output voltage noise using a 0.1-μF ceramic bypass
capacitor and a 2.2-μF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance
increases due to the RC time constant at the NR pin that is created by the internal 250-kΩ resistor and external
capacitor. This RC time constant is affected by the quick-start circuit, especially for values near or below 10 nF.
See Figure 13 for a comparisons of CNR capacitors and startup times.
A feed-forward capacitor is recommended to improve the stability of the device. If R2 = 30.1 kΩ, set C1 to 15 pF
for optimal performance. For voltages less than 1.8 V, the value of this capacitor should be 100 pF. For voltages
greater than 1.8 V, the approximate value of this capacitor can be calculated as shown in Equation 3.
8.2.3 Application Curves
2
0
CNR = 0.001 mF
VOUT (mV)
VEN (V)
4
VIN = 3.8 V
VOUT = 2.8 V
IOUT = 200 mA
COUT = 2.2 mF
TJ = 25°C
3.8
IOUT = 200 mA
COUT = 2.2 mF
CNR = 0.01 mF
20
VIN (mV)
3
VOUT (V)
4.8
2
CNR = 0.0047 mF
1
dv
0.4 V
= ms
dt
0
-20
CNR = 0.01 mF
0
0
20 40
60 80 100 120 140 160 180 200
0
Time (ms)
20
30 40
50 60
70 80
90 100
Time (ms)
Figure 25. TPS79328 Output Voltage, Enable Voltage vs
Time (Start-Up)
16
10
Figure 26. TPS79328 Line Transient Response
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100
DVOUT (mV)
20
ESR, Equivalent Series Resistance (W)
VIN = 3.8 V
COUT = 10 mF
0
−20
−40
di
0.02A
= ms
dt
IOUT (mA)
300
200
1mA
100
0
0
COUT = 10 mF
VIN = 5.5 V
TJ = −40°C to 125°C
10
Region of Instability
1
0.1
Region of Stability
0.01
50 100 150 200 250 300 350 400 450 500
0
Time (ms)
0.02
0.04
0.06
0.08
0.20
IOUT (A)
Figure 27. TPS79328 Load Transient Response
Figure 28. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
8.3 Do's and Don'ts
Do place at least one, low ESR, 2.2-μF capacitor as close as possible between the OUT pin of the regulator and
the GND pin.
Do place at least one, low ESR, 0.1-μF capacitor as close as possible between the IN pin of the regulator and
the GND pin.
Do provide adequate thermal paths away from the device.
Do not place the input or output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not float the Enable (EN) pin.
Do not resistively or inductively load the NR pin.
Do not let the output voltage get more than 0.3 V above the input voltage.
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 2.7 V to 5.5 V. The input voltage
range must provide adequate headroom in order for the device to have a regulated output. This input supply
must be well-regulated and stable. A 0.1-µF input capacitor is required for stability; if the input supply is noisy,
additional input capacitors with low ESR can help improve the output noise performance.
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10 Layout
10.1 Layout Guidelines
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with
a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.
Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize
performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, CFF) must be placed as close as possible to
the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because these circuits may impact system performance
negatively, and even cause instability.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board
be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND
pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND
pin of the device.
10.2 Layout Example
Output Ground
Output Plane
Input Plane
IN
OUT
GND
FB
EN
NR
Input Ground
NR and FB
Ground
Denotes via
Figure 29. Layout Example (DBV Package)
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 4.
3D
9IN ± 9OUT u ,OUT
(4)
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Power Dissipation (continued)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
Figure 30 shows the maximum ambient temperature versus the power dissipation of the TPS730. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to ensure the TPS730 does not
operate above a junction temperature of 125°C.
Maximum Ambient Temperature (qC)
125
DBV Package
YZQ Package
100
75
50
0
0.1
0.2
0.3
Power Dissapation (W)
0.4
0.5
Figure 30. Maximum Ambient Temperature vs Power Dissipation
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in Thermal
Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and
the package than RθJA. The junction temperature can be estimated with Equation 5.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 4.
TT is the temperature at the center-top of the IC package.
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(5)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
Seven evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the
TPS793:
• TPS79301EVM
• TPS79318YEQEVM
• TPS79325YEQEVM
• TPS793285YEQEVM
• TPS79328EVM
• TPS79328YEQEVM
• TPS79330YEQEVM
These EVMs can be requested at the Texas Instruments website through the device product folders or
purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS793 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 4. Ordering Information (1) (2)
PRODUCT
TPS793xxyyyz
(1)
(2)
VOUT
XX(X) is the nominal output voltage (for example, 28 = 2.8 V; 285 = 2.85 V; 01 = adjustable version).
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
•
Application note, Using New Thermal Metrics, SBVA025.
Application note, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator, SBVA042.
TPS793xxYEQEVM User's Guide, SBVU001.
TPS79301EVM, TPS79328EVM LDO Linear Regulator Evaluation Module User's Guide, SLVU060A.
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA01085DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHJI
HPA01085DVBR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHJI
TPS79301DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGVI
TPS79301DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGVI
TPS79318DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
TPS79318DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
TPS79318DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
TPS79318DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
TPS79318YZQR
ACTIVE
DSBGA
YZQ
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E3
TPS79318YZQT
ACTIVE
DSBGA
YZQ
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E3
TPS79325DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGWI
TPS79325DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGWI
TPS79325YZQR
ACTIVE
DSBGA
YZQ
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E4
TPS793285DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHII
TPS793285DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHII
TPS793285DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHII
TPS793285DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHII
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS793285YZQR
ACTIVE
DSBGA
YZQ
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E5
TPS79328DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGXI
TPS79328DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGXI
TPS79328YZQR
ACTIVE
DSBGA
YZQ
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E2
TPS79328YZQT
ACTIVE
DSBGA
YZQ
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E2
TPS79330DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGYI
TPS79330DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGYI
TPS79330YZQR
ACTIVE
DSBGA
YZQ
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E6
TPS79330YZQT
ACTIVE
DSBGA
YZQ
5
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
E6
TPS79333DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHUI
TPS79333DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHUI
TPS793475DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHJI
TPS793475DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHJI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS793 :
• Automotive: TPS793-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS79301DBVR
SOT-23
DBV
6
3000
178.0
9.0
TPS79318DBVR
SOT-23
DBV
5
3000
178.0
TPS79318DBVT
SOT-23
DBV
5
250
178.0
TPS79318YZQR
DSBGA
YZQ
5
3000
TPS79318YZQT
DSBGA
YZQ
5
TPS79325DBVR
SOT-23
DBV
TPS79325YZQR
DSBGA
YZQ
TPS793285DBVR
SOT-23
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
250
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
5
3000
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS793285DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS793285YZQR
DSBGA
YZQ
5
3000
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
TPS79328DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79328YZQR
DSBGA
YZQ
5
3000
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
TPS79328YZQT
DSBGA
YZQ
5
250
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
TPS79330DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TPS79330YZQR
DSBGA
YZQ
5
3000
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
TPS79330YZQT
DSBGA
YZQ
5
250
178.0
8.4
0.98
1.46
0.69
4.0
8.0
Q1
TPS79333DBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS79333DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS793475DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
TPS793475DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
3.17
1.37
4.0
8.0
Q3
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS79301DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPS79318DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79318DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TPS79318YZQR
DSBGA
YZQ
5
3000
217.0
193.0
35.0
TPS79318YZQT
DSBGA
YZQ
5
250
217.0
193.0
35.0
TPS79325DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79325YZQR
DSBGA
YZQ
5
3000
217.0
193.0
35.0
TPS793285DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS793285DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
TPS793285YZQR
DSBGA
YZQ
5
3000
217.0
193.0
35.0
TPS79328DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79328YZQR
DSBGA
YZQ
5
3000
217.0
193.0
35.0
TPS79328YZQT
DSBGA
YZQ
5
250
217.0
193.0
35.0
TPS79330DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS79330YZQR
DSBGA
YZQ
5
3000
217.0
193.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS79330YZQT
DSBGA
YZQ
5
250
217.0
193.0
35.0
TPS79333DBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TPS79333DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TPS793475DBVR
SOT-23
DBV
5
3000
203.0
203.0
35.0
TPS793475DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 3
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